1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/error-report.h" 24 #include "qemu/main-loop.h" 25 #include "qapi/error.h" 26 #include "hw/sysbus.h" 27 #include "exec/address-spaces.h" 28 #include "intel_iommu_internal.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/qdev-properties.h" 32 #include "hw/i386/pc.h" 33 #include "hw/i386/apic-msidef.h" 34 #include "hw/i386/x86-iommu.h" 35 #include "hw/pci-host/q35.h" 36 #include "sysemu/kvm.h" 37 #include "sysemu/dma.h" 38 #include "sysemu/sysemu.h" 39 #include "hw/i386/apic_internal.h" 40 #include "kvm/kvm_i386.h" 41 #include "migration/vmstate.h" 42 #include "trace.h" 43 44 /* context entry operations */ 45 #define VTD_CE_GET_RID2PASID(ce) \ 46 ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK) 47 #define VTD_CE_GET_PASID_DIR_TABLE(ce) \ 48 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) 49 50 /* pe operations */ 51 #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) 52 #define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) 53 #define VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write) {\ 54 if (ret_fr) { \ 55 ret_fr = -ret_fr; \ 56 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { \ 57 trace_vtd_fault_disabled(); \ 58 } else { \ 59 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); \ 60 } \ 61 goto error; \ 62 } \ 63 } 64 65 static void vtd_address_space_refresh_all(IntelIOMMUState *s); 66 static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); 67 68 static void vtd_panic_require_caching_mode(void) 69 { 70 error_report("We need to set caching-mode=on for intel-iommu to enable " 71 "device assignment with IOMMU protection."); 72 exit(1); 73 } 74 75 static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val, 76 uint64_t wmask, uint64_t w1cmask) 77 { 78 stq_le_p(&s->csr[addr], val); 79 stq_le_p(&s->wmask[addr], wmask); 80 stq_le_p(&s->w1cmask[addr], w1cmask); 81 } 82 83 static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask) 84 { 85 stq_le_p(&s->womask[addr], mask); 86 } 87 88 static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val, 89 uint32_t wmask, uint32_t w1cmask) 90 { 91 stl_le_p(&s->csr[addr], val); 92 stl_le_p(&s->wmask[addr], wmask); 93 stl_le_p(&s->w1cmask[addr], w1cmask); 94 } 95 96 static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask) 97 { 98 stl_le_p(&s->womask[addr], mask); 99 } 100 101 /* "External" get/set operations */ 102 static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val) 103 { 104 uint64_t oldval = ldq_le_p(&s->csr[addr]); 105 uint64_t wmask = ldq_le_p(&s->wmask[addr]); 106 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]); 107 stq_le_p(&s->csr[addr], 108 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); 109 } 110 111 static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val) 112 { 113 uint32_t oldval = ldl_le_p(&s->csr[addr]); 114 uint32_t wmask = ldl_le_p(&s->wmask[addr]); 115 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]); 116 stl_le_p(&s->csr[addr], 117 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); 118 } 119 120 static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr) 121 { 122 uint64_t val = ldq_le_p(&s->csr[addr]); 123 uint64_t womask = ldq_le_p(&s->womask[addr]); 124 return val & ~womask; 125 } 126 127 static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr) 128 { 129 uint32_t val = ldl_le_p(&s->csr[addr]); 130 uint32_t womask = ldl_le_p(&s->womask[addr]); 131 return val & ~womask; 132 } 133 134 /* "Internal" get/set operations */ 135 static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr) 136 { 137 return ldq_le_p(&s->csr[addr]); 138 } 139 140 static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr) 141 { 142 return ldl_le_p(&s->csr[addr]); 143 } 144 145 static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val) 146 { 147 stq_le_p(&s->csr[addr], val); 148 } 149 150 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr, 151 uint32_t clear, uint32_t mask) 152 { 153 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask; 154 stl_le_p(&s->csr[addr], new_val); 155 return new_val; 156 } 157 158 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr, 159 uint64_t clear, uint64_t mask) 160 { 161 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask; 162 stq_le_p(&s->csr[addr], new_val); 163 return new_val; 164 } 165 166 static inline void vtd_iommu_lock(IntelIOMMUState *s) 167 { 168 qemu_mutex_lock(&s->iommu_lock); 169 } 170 171 static inline void vtd_iommu_unlock(IntelIOMMUState *s) 172 { 173 qemu_mutex_unlock(&s->iommu_lock); 174 } 175 176 static void vtd_update_scalable_state(IntelIOMMUState *s) 177 { 178 uint64_t val = vtd_get_quad_raw(s, DMAR_RTADDR_REG); 179 180 if (s->scalable_mode) { 181 s->root_scalable = val & VTD_RTADDR_SMT; 182 } 183 } 184 185 /* Whether the address space needs to notify new mappings */ 186 static inline gboolean vtd_as_has_map_notifier(VTDAddressSpace *as) 187 { 188 return as->notifier_flags & IOMMU_NOTIFIER_MAP; 189 } 190 191 /* GHashTable functions */ 192 static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2) 193 { 194 return *((const uint64_t *)v1) == *((const uint64_t *)v2); 195 } 196 197 static guint vtd_uint64_hash(gconstpointer v) 198 { 199 return (guint)*(const uint64_t *)v; 200 } 201 202 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, 203 gpointer user_data) 204 { 205 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; 206 uint16_t domain_id = *(uint16_t *)user_data; 207 return entry->domain_id == domain_id; 208 } 209 210 /* The shift of an addr for a certain level of paging structure */ 211 static inline uint32_t vtd_slpt_level_shift(uint32_t level) 212 { 213 assert(level != 0); 214 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS; 215 } 216 217 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level) 218 { 219 return ~((1ULL << vtd_slpt_level_shift(level)) - 1); 220 } 221 222 static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value, 223 gpointer user_data) 224 { 225 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; 226 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data; 227 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask; 228 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K; 229 return (entry->domain_id == info->domain_id) && 230 (((entry->gfn & info->mask) == gfn) || 231 (entry->gfn == gfn_tlb)); 232 } 233 234 /* Reset all the gen of VTDAddressSpace to zero and set the gen of 235 * IntelIOMMUState to 1. Must be called with IOMMU lock held. 236 */ 237 static void vtd_reset_context_cache_locked(IntelIOMMUState *s) 238 { 239 VTDAddressSpace *vtd_as; 240 VTDBus *vtd_bus; 241 GHashTableIter bus_it; 242 uint32_t devfn_it; 243 244 trace_vtd_context_cache_reset(); 245 246 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr); 247 248 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) { 249 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { 250 vtd_as = vtd_bus->dev_as[devfn_it]; 251 if (!vtd_as) { 252 continue; 253 } 254 vtd_as->context_cache_entry.context_cache_gen = 0; 255 } 256 } 257 s->context_cache_gen = 1; 258 } 259 260 /* Must be called with IOMMU lock held. */ 261 static void vtd_reset_iotlb_locked(IntelIOMMUState *s) 262 { 263 assert(s->iotlb); 264 g_hash_table_remove_all(s->iotlb); 265 } 266 267 static void vtd_reset_iotlb(IntelIOMMUState *s) 268 { 269 vtd_iommu_lock(s); 270 vtd_reset_iotlb_locked(s); 271 vtd_iommu_unlock(s); 272 } 273 274 static void vtd_reset_caches(IntelIOMMUState *s) 275 { 276 vtd_iommu_lock(s); 277 vtd_reset_iotlb_locked(s); 278 vtd_reset_context_cache_locked(s); 279 vtd_iommu_unlock(s); 280 } 281 282 static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id, 283 uint32_t level) 284 { 285 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) | 286 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT); 287 } 288 289 static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) 290 { 291 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K; 292 } 293 294 /* Must be called with IOMMU lock held */ 295 static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id, 296 hwaddr addr) 297 { 298 VTDIOTLBEntry *entry; 299 uint64_t key; 300 int level; 301 302 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) { 303 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level), 304 source_id, level); 305 entry = g_hash_table_lookup(s->iotlb, &key); 306 if (entry) { 307 goto out; 308 } 309 } 310 311 out: 312 return entry; 313 } 314 315 /* Must be with IOMMU lock held */ 316 static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id, 317 uint16_t domain_id, hwaddr addr, uint64_t slpte, 318 uint8_t access_flags, uint32_t level) 319 { 320 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry)); 321 uint64_t *key = g_malloc(sizeof(*key)); 322 uint64_t gfn = vtd_get_iotlb_gfn(addr, level); 323 324 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id); 325 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) { 326 trace_vtd_iotlb_reset("iotlb exceeds size limit"); 327 vtd_reset_iotlb_locked(s); 328 } 329 330 entry->gfn = gfn; 331 entry->domain_id = domain_id; 332 entry->slpte = slpte; 333 entry->access_flags = access_flags; 334 entry->mask = vtd_slpt_level_page_mask(level); 335 *key = vtd_get_iotlb_key(gfn, source_id, level); 336 g_hash_table_replace(s->iotlb, key, entry); 337 } 338 339 /* Given the reg addr of both the message data and address, generate an 340 * interrupt via MSI. 341 */ 342 static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg, 343 hwaddr mesg_data_reg) 344 { 345 MSIMessage msi; 346 347 assert(mesg_data_reg < DMAR_REG_SIZE); 348 assert(mesg_addr_reg < DMAR_REG_SIZE); 349 350 msi.address = vtd_get_long_raw(s, mesg_addr_reg); 351 msi.data = vtd_get_long_raw(s, mesg_data_reg); 352 353 trace_vtd_irq_generate(msi.address, msi.data); 354 355 apic_get_class()->send_msi(&msi); 356 } 357 358 /* Generate a fault event to software via MSI if conditions are met. 359 * Notice that the value of FSTS_REG being passed to it should be the one 360 * before any update. 361 */ 362 static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts) 363 { 364 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO || 365 pre_fsts & VTD_FSTS_IQE) { 366 error_report_once("There are previous interrupt conditions " 367 "to be serviced by software, fault event " 368 "is not generated"); 369 return; 370 } 371 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP); 372 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) { 373 error_report_once("Interrupt Mask set, irq is not generated"); 374 } else { 375 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG); 376 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); 377 } 378 } 379 380 /* Check if the Fault (F) field of the Fault Recording Register referenced by 381 * @index is Set. 382 */ 383 static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index) 384 { 385 /* Each reg is 128-bit */ 386 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); 387 addr += 8; /* Access the high 64-bit half */ 388 389 assert(index < DMAR_FRCD_REG_NR); 390 391 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F; 392 } 393 394 /* Update the PPF field of Fault Status Register. 395 * Should be called whenever change the F field of any fault recording 396 * registers. 397 */ 398 static void vtd_update_fsts_ppf(IntelIOMMUState *s) 399 { 400 uint32_t i; 401 uint32_t ppf_mask = 0; 402 403 for (i = 0; i < DMAR_FRCD_REG_NR; i++) { 404 if (vtd_is_frcd_set(s, i)) { 405 ppf_mask = VTD_FSTS_PPF; 406 break; 407 } 408 } 409 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask); 410 trace_vtd_fsts_ppf(!!ppf_mask); 411 } 412 413 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index) 414 { 415 /* Each reg is 128-bit */ 416 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); 417 addr += 8; /* Access the high 64-bit half */ 418 419 assert(index < DMAR_FRCD_REG_NR); 420 421 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F); 422 vtd_update_fsts_ppf(s); 423 } 424 425 /* Must not update F field now, should be done later */ 426 static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index, 427 uint16_t source_id, hwaddr addr, 428 VTDFaultReason fault, bool is_write) 429 { 430 uint64_t hi = 0, lo; 431 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); 432 433 assert(index < DMAR_FRCD_REG_NR); 434 435 lo = VTD_FRCD_FI(addr); 436 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault); 437 if (!is_write) { 438 hi |= VTD_FRCD_T; 439 } 440 vtd_set_quad_raw(s, frcd_reg_addr, lo); 441 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi); 442 443 trace_vtd_frr_new(index, hi, lo); 444 } 445 446 /* Try to collapse multiple pending faults from the same requester */ 447 static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id) 448 { 449 uint32_t i; 450 uint64_t frcd_reg; 451 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */ 452 453 for (i = 0; i < DMAR_FRCD_REG_NR; i++) { 454 frcd_reg = vtd_get_quad_raw(s, addr); 455 if ((frcd_reg & VTD_FRCD_F) && 456 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) { 457 return true; 458 } 459 addr += 16; /* 128-bit for each */ 460 } 461 return false; 462 } 463 464 /* Log and report an DMAR (address translation) fault to software */ 465 static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id, 466 hwaddr addr, VTDFaultReason fault, 467 bool is_write) 468 { 469 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); 470 471 assert(fault < VTD_FR_MAX); 472 473 if (fault == VTD_FR_RESERVED_ERR) { 474 /* This is not a normal fault reason case. Drop it. */ 475 return; 476 } 477 478 trace_vtd_dmar_fault(source_id, fault, addr, is_write); 479 480 if (fsts_reg & VTD_FSTS_PFO) { 481 error_report_once("New fault is not recorded due to " 482 "Primary Fault Overflow"); 483 return; 484 } 485 486 if (vtd_try_collapse_fault(s, source_id)) { 487 error_report_once("New fault is not recorded due to " 488 "compression of faults"); 489 return; 490 } 491 492 if (vtd_is_frcd_set(s, s->next_frcd_reg)) { 493 error_report_once("Next Fault Recording Reg is used, " 494 "new fault is not recorded, set PFO field"); 495 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO); 496 return; 497 } 498 499 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write); 500 501 if (fsts_reg & VTD_FSTS_PPF) { 502 error_report_once("There are pending faults already, " 503 "fault event is not generated"); 504 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); 505 s->next_frcd_reg++; 506 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) { 507 s->next_frcd_reg = 0; 508 } 509 } else { 510 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK, 511 VTD_FSTS_FRI(s->next_frcd_reg)); 512 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */ 513 s->next_frcd_reg++; 514 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) { 515 s->next_frcd_reg = 0; 516 } 517 /* This case actually cause the PPF to be Set. 518 * So generate fault event (interrupt). 519 */ 520 vtd_generate_fault_event(s, fsts_reg); 521 } 522 } 523 524 /* Handle Invalidation Queue Errors of queued invalidation interface error 525 * conditions. 526 */ 527 static void vtd_handle_inv_queue_error(IntelIOMMUState *s) 528 { 529 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); 530 531 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE); 532 vtd_generate_fault_event(s, fsts_reg); 533 } 534 535 /* Set the IWC field and try to generate an invalidation completion interrupt */ 536 static void vtd_generate_completion_event(IntelIOMMUState *s) 537 { 538 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) { 539 trace_vtd_inv_desc_wait_irq("One pending, skip current"); 540 return; 541 } 542 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC); 543 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP); 544 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) { 545 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, " 546 "new event not generated"); 547 return; 548 } else { 549 /* Generate the interrupt event */ 550 trace_vtd_inv_desc_wait_irq("Generating complete event"); 551 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG); 552 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); 553 } 554 } 555 556 static inline bool vtd_root_entry_present(IntelIOMMUState *s, 557 VTDRootEntry *re, 558 uint8_t devfn) 559 { 560 if (s->root_scalable && devfn > UINT8_MAX / 2) { 561 return re->hi & VTD_ROOT_ENTRY_P; 562 } 563 564 return re->lo & VTD_ROOT_ENTRY_P; 565 } 566 567 static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index, 568 VTDRootEntry *re) 569 { 570 dma_addr_t addr; 571 572 addr = s->root + index * sizeof(*re); 573 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) { 574 re->lo = 0; 575 return -VTD_FR_ROOT_TABLE_INV; 576 } 577 re->lo = le64_to_cpu(re->lo); 578 re->hi = le64_to_cpu(re->hi); 579 return 0; 580 } 581 582 static inline bool vtd_ce_present(VTDContextEntry *context) 583 { 584 return context->lo & VTD_CONTEXT_ENTRY_P; 585 } 586 587 static int vtd_get_context_entry_from_root(IntelIOMMUState *s, 588 VTDRootEntry *re, 589 uint8_t index, 590 VTDContextEntry *ce) 591 { 592 dma_addr_t addr, ce_size; 593 594 /* we have checked that root entry is present */ 595 ce_size = s->root_scalable ? VTD_CTX_ENTRY_SCALABLE_SIZE : 596 VTD_CTX_ENTRY_LEGACY_SIZE; 597 598 if (s->root_scalable && index > UINT8_MAX / 2) { 599 index = index & (~VTD_DEVFN_CHECK_MASK); 600 addr = re->hi & VTD_ROOT_ENTRY_CTP; 601 } else { 602 addr = re->lo & VTD_ROOT_ENTRY_CTP; 603 } 604 605 addr = addr + index * ce_size; 606 if (dma_memory_read(&address_space_memory, addr, ce, ce_size)) { 607 return -VTD_FR_CONTEXT_TABLE_INV; 608 } 609 610 ce->lo = le64_to_cpu(ce->lo); 611 ce->hi = le64_to_cpu(ce->hi); 612 if (ce_size == VTD_CTX_ENTRY_SCALABLE_SIZE) { 613 ce->val[2] = le64_to_cpu(ce->val[2]); 614 ce->val[3] = le64_to_cpu(ce->val[3]); 615 } 616 return 0; 617 } 618 619 static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce) 620 { 621 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR; 622 } 623 624 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw) 625 { 626 return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw); 627 } 628 629 /* Whether the pte indicates the address of the page frame */ 630 static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level) 631 { 632 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK); 633 } 634 635 /* Get the content of a spte located in @base_addr[@index] */ 636 static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index) 637 { 638 uint64_t slpte; 639 640 assert(index < VTD_SL_PT_ENTRY_NR); 641 642 if (dma_memory_read(&address_space_memory, 643 base_addr + index * sizeof(slpte), &slpte, 644 sizeof(slpte))) { 645 slpte = (uint64_t)-1; 646 return slpte; 647 } 648 slpte = le64_to_cpu(slpte); 649 return slpte; 650 } 651 652 /* Given an iova and the level of paging structure, return the offset 653 * of current level. 654 */ 655 static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level) 656 { 657 return (iova >> vtd_slpt_level_shift(level)) & 658 ((1ULL << VTD_SL_LEVEL_BITS) - 1); 659 } 660 661 /* Check Capability Register to see if the @level of page-table is supported */ 662 static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level) 663 { 664 return VTD_CAP_SAGAW_MASK & s->cap & 665 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT)); 666 } 667 668 /* Return true if check passed, otherwise false */ 669 static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu, 670 VTDPASIDEntry *pe) 671 { 672 switch (VTD_PE_GET_TYPE(pe)) { 673 case VTD_SM_PASID_ENTRY_FLT: 674 case VTD_SM_PASID_ENTRY_SLT: 675 case VTD_SM_PASID_ENTRY_NESTED: 676 break; 677 case VTD_SM_PASID_ENTRY_PT: 678 if (!x86_iommu->pt_supported) { 679 return false; 680 } 681 break; 682 default: 683 /* Unknwon type */ 684 return false; 685 } 686 return true; 687 } 688 689 static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) 690 { 691 return pdire->val & 1; 692 } 693 694 /** 695 * Caller of this function should check present bit if wants 696 * to use pdir entry for futher usage except for fpd bit check. 697 */ 698 static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, 699 uint32_t pasid, 700 VTDPASIDDirEntry *pdire) 701 { 702 uint32_t index; 703 dma_addr_t addr, entry_size; 704 705 index = VTD_PASID_DIR_INDEX(pasid); 706 entry_size = VTD_PASID_DIR_ENTRY_SIZE; 707 addr = pasid_dir_base + index * entry_size; 708 if (dma_memory_read(&address_space_memory, addr, pdire, entry_size)) { 709 return -VTD_FR_PASID_TABLE_INV; 710 } 711 712 return 0; 713 } 714 715 static inline bool vtd_pe_present(VTDPASIDEntry *pe) 716 { 717 return pe->val[0] & VTD_PASID_ENTRY_P; 718 } 719 720 static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, 721 uint32_t pasid, 722 dma_addr_t addr, 723 VTDPASIDEntry *pe) 724 { 725 uint32_t index; 726 dma_addr_t entry_size; 727 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 728 729 index = VTD_PASID_TABLE_INDEX(pasid); 730 entry_size = VTD_PASID_ENTRY_SIZE; 731 addr = addr + index * entry_size; 732 if (dma_memory_read(&address_space_memory, addr, pe, entry_size)) { 733 return -VTD_FR_PASID_TABLE_INV; 734 } 735 736 /* Do translation type check */ 737 if (!vtd_pe_type_check(x86_iommu, pe)) { 738 return -VTD_FR_PASID_TABLE_INV; 739 } 740 741 if (!vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) { 742 return -VTD_FR_PASID_TABLE_INV; 743 } 744 745 return 0; 746 } 747 748 /** 749 * Caller of this function should check present bit if wants 750 * to use pasid entry for futher usage except for fpd bit check. 751 */ 752 static int vtd_get_pe_from_pdire(IntelIOMMUState *s, 753 uint32_t pasid, 754 VTDPASIDDirEntry *pdire, 755 VTDPASIDEntry *pe) 756 { 757 dma_addr_t addr = pdire->val & VTD_PASID_TABLE_BASE_ADDR_MASK; 758 759 return vtd_get_pe_in_pasid_leaf_table(s, pasid, addr, pe); 760 } 761 762 /** 763 * This function gets a pasid entry from a specified pasid 764 * table (includes dir and leaf table) with a specified pasid. 765 * Sanity check should be done to ensure return a present 766 * pasid entry to caller. 767 */ 768 static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s, 769 dma_addr_t pasid_dir_base, 770 uint32_t pasid, 771 VTDPASIDEntry *pe) 772 { 773 int ret; 774 VTDPASIDDirEntry pdire; 775 776 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base, 777 pasid, &pdire); 778 if (ret) { 779 return ret; 780 } 781 782 if (!vtd_pdire_present(&pdire)) { 783 return -VTD_FR_PASID_TABLE_INV; 784 } 785 786 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, pe); 787 if (ret) { 788 return ret; 789 } 790 791 if (!vtd_pe_present(pe)) { 792 return -VTD_FR_PASID_TABLE_INV; 793 } 794 795 return 0; 796 } 797 798 static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, 799 VTDContextEntry *ce, 800 VTDPASIDEntry *pe) 801 { 802 uint32_t pasid; 803 dma_addr_t pasid_dir_base; 804 int ret = 0; 805 806 pasid = VTD_CE_GET_RID2PASID(ce); 807 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce); 808 ret = vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe); 809 810 return ret; 811 } 812 813 static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, 814 VTDContextEntry *ce, 815 bool *pe_fpd_set) 816 { 817 int ret; 818 uint32_t pasid; 819 dma_addr_t pasid_dir_base; 820 VTDPASIDDirEntry pdire; 821 VTDPASIDEntry pe; 822 823 pasid = VTD_CE_GET_RID2PASID(ce); 824 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce); 825 826 /* 827 * No present bit check since fpd is meaningful even 828 * if the present bit is clear. 829 */ 830 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base, pasid, &pdire); 831 if (ret) { 832 return ret; 833 } 834 835 if (pdire.val & VTD_PASID_DIR_FPD) { 836 *pe_fpd_set = true; 837 return 0; 838 } 839 840 if (!vtd_pdire_present(&pdire)) { 841 return -VTD_FR_PASID_TABLE_INV; 842 } 843 844 /* 845 * No present bit check since fpd is meaningful even 846 * if the present bit is clear. 847 */ 848 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, &pe); 849 if (ret) { 850 return ret; 851 } 852 853 if (pe.val[0] & VTD_PASID_ENTRY_FPD) { 854 *pe_fpd_set = true; 855 } 856 857 return 0; 858 } 859 860 /* Get the page-table level that hardware should use for the second-level 861 * page-table walk from the Address Width field of context-entry. 862 */ 863 static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce) 864 { 865 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW); 866 } 867 868 static uint32_t vtd_get_iova_level(IntelIOMMUState *s, 869 VTDContextEntry *ce) 870 { 871 VTDPASIDEntry pe; 872 873 if (s->root_scalable) { 874 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 875 return VTD_PE_GET_LEVEL(&pe); 876 } 877 878 return vtd_ce_get_level(ce); 879 } 880 881 static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce) 882 { 883 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9; 884 } 885 886 static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, 887 VTDContextEntry *ce) 888 { 889 VTDPASIDEntry pe; 890 891 if (s->root_scalable) { 892 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 893 return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; 894 } 895 896 return vtd_ce_get_agaw(ce); 897 } 898 899 static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce) 900 { 901 return ce->lo & VTD_CONTEXT_ENTRY_TT; 902 } 903 904 /* Only for Legacy Mode. Return true if check passed, otherwise false */ 905 static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu, 906 VTDContextEntry *ce) 907 { 908 switch (vtd_ce_get_type(ce)) { 909 case VTD_CONTEXT_TT_MULTI_LEVEL: 910 /* Always supported */ 911 break; 912 case VTD_CONTEXT_TT_DEV_IOTLB: 913 if (!x86_iommu->dt_supported) { 914 error_report_once("%s: DT specified but not supported", __func__); 915 return false; 916 } 917 break; 918 case VTD_CONTEXT_TT_PASS_THROUGH: 919 if (!x86_iommu->pt_supported) { 920 error_report_once("%s: PT specified but not supported", __func__); 921 return false; 922 } 923 break; 924 default: 925 /* Unknown type */ 926 error_report_once("%s: unknown ce type: %"PRIu32, __func__, 927 vtd_ce_get_type(ce)); 928 return false; 929 } 930 return true; 931 } 932 933 static inline uint64_t vtd_iova_limit(IntelIOMMUState *s, 934 VTDContextEntry *ce, uint8_t aw) 935 { 936 uint32_t ce_agaw = vtd_get_iova_agaw(s, ce); 937 return 1ULL << MIN(ce_agaw, aw); 938 } 939 940 /* Return true if IOVA passes range check, otherwise false. */ 941 static inline bool vtd_iova_range_check(IntelIOMMUState *s, 942 uint64_t iova, VTDContextEntry *ce, 943 uint8_t aw) 944 { 945 /* 946 * Check if @iova is above 2^X-1, where X is the minimum of MGAW 947 * in CAP_REG and AW in context-entry. 948 */ 949 return !(iova & ~(vtd_iova_limit(s, ce, aw) - 1)); 950 } 951 952 static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s, 953 VTDContextEntry *ce) 954 { 955 VTDPASIDEntry pe; 956 957 if (s->root_scalable) { 958 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 959 return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR; 960 } 961 962 return vtd_ce_get_slpt_base(ce); 963 } 964 965 /* 966 * Rsvd field masks for spte: 967 * vtd_spte_rsvd 4k pages 968 * vtd_spte_rsvd_large large pages 969 */ 970 static uint64_t vtd_spte_rsvd[5]; 971 static uint64_t vtd_spte_rsvd_large[5]; 972 973 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) 974 { 975 uint64_t rsvd_mask = vtd_spte_rsvd[level]; 976 977 if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) && 978 (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) { 979 /* large page */ 980 rsvd_mask = vtd_spte_rsvd_large[level]; 981 } 982 983 return slpte & rsvd_mask; 984 } 985 986 /* Find the VTD address space associated with a given bus number */ 987 static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num) 988 { 989 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num]; 990 GHashTableIter iter; 991 992 if (vtd_bus) { 993 return vtd_bus; 994 } 995 996 /* 997 * Iterate over the registered buses to find the one which 998 * currently holds this bus number and update the bus_num 999 * lookup table. 1000 */ 1001 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); 1002 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { 1003 if (pci_bus_num(vtd_bus->bus) == bus_num) { 1004 s->vtd_as_by_bus_num[bus_num] = vtd_bus; 1005 return vtd_bus; 1006 } 1007 } 1008 1009 return NULL; 1010 } 1011 1012 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level 1013 * of the translation, can be used for deciding the size of large page. 1014 */ 1015 static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce, 1016 uint64_t iova, bool is_write, 1017 uint64_t *slptep, uint32_t *slpte_level, 1018 bool *reads, bool *writes, uint8_t aw_bits) 1019 { 1020 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce); 1021 uint32_t level = vtd_get_iova_level(s, ce); 1022 uint32_t offset; 1023 uint64_t slpte; 1024 uint64_t access_right_check; 1025 1026 if (!vtd_iova_range_check(s, iova, ce, aw_bits)) { 1027 error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64 ")", 1028 __func__, iova); 1029 return -VTD_FR_ADDR_BEYOND_MGAW; 1030 } 1031 1032 /* FIXME: what is the Atomics request here? */ 1033 access_right_check = is_write ? VTD_SL_W : VTD_SL_R; 1034 1035 while (true) { 1036 offset = vtd_iova_level_offset(iova, level); 1037 slpte = vtd_get_slpte(addr, offset); 1038 1039 if (slpte == (uint64_t)-1) { 1040 error_report_once("%s: detected read error on DMAR slpte " 1041 "(iova=0x%" PRIx64 ")", __func__, iova); 1042 if (level == vtd_get_iova_level(s, ce)) { 1043 /* Invalid programming of context-entry */ 1044 return -VTD_FR_CONTEXT_ENTRY_INV; 1045 } else { 1046 return -VTD_FR_PAGING_ENTRY_INV; 1047 } 1048 } 1049 *reads = (*reads) && (slpte & VTD_SL_R); 1050 *writes = (*writes) && (slpte & VTD_SL_W); 1051 if (!(slpte & access_right_check)) { 1052 error_report_once("%s: detected slpte permission error " 1053 "(iova=0x%" PRIx64 ", level=0x%" PRIx32 ", " 1054 "slpte=0x%" PRIx64 ", write=%d)", __func__, 1055 iova, level, slpte, is_write); 1056 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ; 1057 } 1058 if (vtd_slpte_nonzero_rsvd(slpte, level)) { 1059 error_report_once("%s: detected splte reserve non-zero " 1060 "iova=0x%" PRIx64 ", level=0x%" PRIx32 1061 "slpte=0x%" PRIx64 ")", __func__, iova, 1062 level, slpte); 1063 return -VTD_FR_PAGING_ENTRY_RSVD; 1064 } 1065 1066 if (vtd_is_last_slpte(slpte, level)) { 1067 *slptep = slpte; 1068 *slpte_level = level; 1069 return 0; 1070 } 1071 addr = vtd_get_slpte_addr(slpte, aw_bits); 1072 level--; 1073 } 1074 } 1075 1076 typedef int (*vtd_page_walk_hook)(IOMMUTLBEvent *event, void *private); 1077 1078 /** 1079 * Constant information used during page walking 1080 * 1081 * @hook_fn: hook func to be called when detected page 1082 * @private: private data to be passed into hook func 1083 * @notify_unmap: whether we should notify invalid entries 1084 * @as: VT-d address space of the device 1085 * @aw: maximum address width 1086 * @domain: domain ID of the page walk 1087 */ 1088 typedef struct { 1089 VTDAddressSpace *as; 1090 vtd_page_walk_hook hook_fn; 1091 void *private; 1092 bool notify_unmap; 1093 uint8_t aw; 1094 uint16_t domain_id; 1095 } vtd_page_walk_info; 1096 1097 static int vtd_page_walk_one(IOMMUTLBEvent *event, vtd_page_walk_info *info) 1098 { 1099 VTDAddressSpace *as = info->as; 1100 vtd_page_walk_hook hook_fn = info->hook_fn; 1101 void *private = info->private; 1102 IOMMUTLBEntry *entry = &event->entry; 1103 DMAMap target = { 1104 .iova = entry->iova, 1105 .size = entry->addr_mask, 1106 .translated_addr = entry->translated_addr, 1107 .perm = entry->perm, 1108 }; 1109 DMAMap *mapped = iova_tree_find(as->iova_tree, &target); 1110 1111 if (event->type == IOMMU_NOTIFIER_UNMAP && !info->notify_unmap) { 1112 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask); 1113 return 0; 1114 } 1115 1116 assert(hook_fn); 1117 1118 /* Update local IOVA mapped ranges */ 1119 if (event->type == IOMMU_NOTIFIER_MAP) { 1120 if (mapped) { 1121 /* If it's exactly the same translation, skip */ 1122 if (!memcmp(mapped, &target, sizeof(target))) { 1123 trace_vtd_page_walk_one_skip_map(entry->iova, entry->addr_mask, 1124 entry->translated_addr); 1125 return 0; 1126 } else { 1127 /* 1128 * Translation changed. Normally this should not 1129 * happen, but it can happen when with buggy guest 1130 * OSes. Note that there will be a small window that 1131 * we don't have map at all. But that's the best 1132 * effort we can do. The ideal way to emulate this is 1133 * atomically modify the PTE to follow what has 1134 * changed, but we can't. One example is that vfio 1135 * driver only has VFIO_IOMMU_[UN]MAP_DMA but no 1136 * interface to modify a mapping (meanwhile it seems 1137 * meaningless to even provide one). Anyway, let's 1138 * mark this as a TODO in case one day we'll have 1139 * a better solution. 1140 */ 1141 IOMMUAccessFlags cache_perm = entry->perm; 1142 int ret; 1143 1144 /* Emulate an UNMAP */ 1145 event->type = IOMMU_NOTIFIER_UNMAP; 1146 entry->perm = IOMMU_NONE; 1147 trace_vtd_page_walk_one(info->domain_id, 1148 entry->iova, 1149 entry->translated_addr, 1150 entry->addr_mask, 1151 entry->perm); 1152 ret = hook_fn(event, private); 1153 if (ret) { 1154 return ret; 1155 } 1156 /* Drop any existing mapping */ 1157 iova_tree_remove(as->iova_tree, &target); 1158 /* Recover the correct type */ 1159 event->type = IOMMU_NOTIFIER_MAP; 1160 entry->perm = cache_perm; 1161 } 1162 } 1163 iova_tree_insert(as->iova_tree, &target); 1164 } else { 1165 if (!mapped) { 1166 /* Skip since we didn't map this range at all */ 1167 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask); 1168 return 0; 1169 } 1170 iova_tree_remove(as->iova_tree, &target); 1171 } 1172 1173 trace_vtd_page_walk_one(info->domain_id, entry->iova, 1174 entry->translated_addr, entry->addr_mask, 1175 entry->perm); 1176 return hook_fn(event, private); 1177 } 1178 1179 /** 1180 * vtd_page_walk_level - walk over specific level for IOVA range 1181 * 1182 * @addr: base GPA addr to start the walk 1183 * @start: IOVA range start address 1184 * @end: IOVA range end address (start <= addr < end) 1185 * @read: whether parent level has read permission 1186 * @write: whether parent level has write permission 1187 * @info: constant information for the page walk 1188 */ 1189 static int vtd_page_walk_level(dma_addr_t addr, uint64_t start, 1190 uint64_t end, uint32_t level, bool read, 1191 bool write, vtd_page_walk_info *info) 1192 { 1193 bool read_cur, write_cur, entry_valid; 1194 uint32_t offset; 1195 uint64_t slpte; 1196 uint64_t subpage_size, subpage_mask; 1197 IOMMUTLBEvent event; 1198 uint64_t iova = start; 1199 uint64_t iova_next; 1200 int ret = 0; 1201 1202 trace_vtd_page_walk_level(addr, level, start, end); 1203 1204 subpage_size = 1ULL << vtd_slpt_level_shift(level); 1205 subpage_mask = vtd_slpt_level_page_mask(level); 1206 1207 while (iova < end) { 1208 iova_next = (iova & subpage_mask) + subpage_size; 1209 1210 offset = vtd_iova_level_offset(iova, level); 1211 slpte = vtd_get_slpte(addr, offset); 1212 1213 if (slpte == (uint64_t)-1) { 1214 trace_vtd_page_walk_skip_read(iova, iova_next); 1215 goto next; 1216 } 1217 1218 if (vtd_slpte_nonzero_rsvd(slpte, level)) { 1219 trace_vtd_page_walk_skip_reserve(iova, iova_next); 1220 goto next; 1221 } 1222 1223 /* Permissions are stacked with parents' */ 1224 read_cur = read && (slpte & VTD_SL_R); 1225 write_cur = write && (slpte & VTD_SL_W); 1226 1227 /* 1228 * As long as we have either read/write permission, this is a 1229 * valid entry. The rule works for both page entries and page 1230 * table entries. 1231 */ 1232 entry_valid = read_cur | write_cur; 1233 1234 if (!vtd_is_last_slpte(slpte, level) && entry_valid) { 1235 /* 1236 * This is a valid PDE (or even bigger than PDE). We need 1237 * to walk one further level. 1238 */ 1239 ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw), 1240 iova, MIN(iova_next, end), level - 1, 1241 read_cur, write_cur, info); 1242 } else { 1243 /* 1244 * This means we are either: 1245 * 1246 * (1) the real page entry (either 4K page, or huge page) 1247 * (2) the whole range is invalid 1248 * 1249 * In either case, we send an IOTLB notification down. 1250 */ 1251 event.entry.target_as = &address_space_memory; 1252 event.entry.iova = iova & subpage_mask; 1253 event.entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur); 1254 event.entry.addr_mask = ~subpage_mask; 1255 /* NOTE: this is only meaningful if entry_valid == true */ 1256 event.entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw); 1257 event.type = event.entry.perm ? IOMMU_NOTIFIER_MAP : 1258 IOMMU_NOTIFIER_UNMAP; 1259 ret = vtd_page_walk_one(&event, info); 1260 } 1261 1262 if (ret < 0) { 1263 return ret; 1264 } 1265 1266 next: 1267 iova = iova_next; 1268 } 1269 1270 return 0; 1271 } 1272 1273 /** 1274 * vtd_page_walk - walk specific IOVA range, and call the hook 1275 * 1276 * @s: intel iommu state 1277 * @ce: context entry to walk upon 1278 * @start: IOVA address to start the walk 1279 * @end: IOVA range end address (start <= addr < end) 1280 * @info: page walking information struct 1281 */ 1282 static int vtd_page_walk(IntelIOMMUState *s, VTDContextEntry *ce, 1283 uint64_t start, uint64_t end, 1284 vtd_page_walk_info *info) 1285 { 1286 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce); 1287 uint32_t level = vtd_get_iova_level(s, ce); 1288 1289 if (!vtd_iova_range_check(s, start, ce, info->aw)) { 1290 return -VTD_FR_ADDR_BEYOND_MGAW; 1291 } 1292 1293 if (!vtd_iova_range_check(s, end, ce, info->aw)) { 1294 /* Fix end so that it reaches the maximum */ 1295 end = vtd_iova_limit(s, ce, info->aw); 1296 } 1297 1298 return vtd_page_walk_level(addr, start, end, level, true, true, info); 1299 } 1300 1301 static int vtd_root_entry_rsvd_bits_check(IntelIOMMUState *s, 1302 VTDRootEntry *re) 1303 { 1304 /* Legacy Mode reserved bits check */ 1305 if (!s->root_scalable && 1306 (re->hi || (re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)))) 1307 goto rsvd_err; 1308 1309 /* Scalable Mode reserved bits check */ 1310 if (s->root_scalable && 1311 ((re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)) || 1312 (re->hi & VTD_ROOT_ENTRY_RSVD(s->aw_bits)))) 1313 goto rsvd_err; 1314 1315 return 0; 1316 1317 rsvd_err: 1318 error_report_once("%s: invalid root entry: hi=0x%"PRIx64 1319 ", lo=0x%"PRIx64, 1320 __func__, re->hi, re->lo); 1321 return -VTD_FR_ROOT_ENTRY_RSVD; 1322 } 1323 1324 static inline int vtd_context_entry_rsvd_bits_check(IntelIOMMUState *s, 1325 VTDContextEntry *ce) 1326 { 1327 if (!s->root_scalable && 1328 (ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI || 1329 ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(s->aw_bits))) { 1330 error_report_once("%s: invalid context entry: hi=%"PRIx64 1331 ", lo=%"PRIx64" (reserved nonzero)", 1332 __func__, ce->hi, ce->lo); 1333 return -VTD_FR_CONTEXT_ENTRY_RSVD; 1334 } 1335 1336 if (s->root_scalable && 1337 (ce->val[0] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(s->aw_bits) || 1338 ce->val[1] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 || 1339 ce->val[2] || 1340 ce->val[3])) { 1341 error_report_once("%s: invalid context entry: val[3]=%"PRIx64 1342 ", val[2]=%"PRIx64 1343 ", val[1]=%"PRIx64 1344 ", val[0]=%"PRIx64" (reserved nonzero)", 1345 __func__, ce->val[3], ce->val[2], 1346 ce->val[1], ce->val[0]); 1347 return -VTD_FR_CONTEXT_ENTRY_RSVD; 1348 } 1349 1350 return 0; 1351 } 1352 1353 static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, 1354 VTDContextEntry *ce) 1355 { 1356 VTDPASIDEntry pe; 1357 1358 /* 1359 * Make sure in Scalable Mode, a present context entry 1360 * has valid rid2pasid setting, which includes valid 1361 * rid2pasid field and corresponding pasid entry setting 1362 */ 1363 return vtd_ce_get_rid2pasid_entry(s, ce, &pe); 1364 } 1365 1366 /* Map a device to its corresponding domain (context-entry) */ 1367 static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, 1368 uint8_t devfn, VTDContextEntry *ce) 1369 { 1370 VTDRootEntry re; 1371 int ret_fr; 1372 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 1373 1374 ret_fr = vtd_get_root_entry(s, bus_num, &re); 1375 if (ret_fr) { 1376 return ret_fr; 1377 } 1378 1379 if (!vtd_root_entry_present(s, &re, devfn)) { 1380 /* Not error - it's okay we don't have root entry. */ 1381 trace_vtd_re_not_present(bus_num); 1382 return -VTD_FR_ROOT_ENTRY_P; 1383 } 1384 1385 ret_fr = vtd_root_entry_rsvd_bits_check(s, &re); 1386 if (ret_fr) { 1387 return ret_fr; 1388 } 1389 1390 ret_fr = vtd_get_context_entry_from_root(s, &re, devfn, ce); 1391 if (ret_fr) { 1392 return ret_fr; 1393 } 1394 1395 if (!vtd_ce_present(ce)) { 1396 /* Not error - it's okay we don't have context entry. */ 1397 trace_vtd_ce_not_present(bus_num, devfn); 1398 return -VTD_FR_CONTEXT_ENTRY_P; 1399 } 1400 1401 ret_fr = vtd_context_entry_rsvd_bits_check(s, ce); 1402 if (ret_fr) { 1403 return ret_fr; 1404 } 1405 1406 /* Check if the programming of context-entry is valid */ 1407 if (!s->root_scalable && 1408 !vtd_is_level_supported(s, vtd_ce_get_level(ce))) { 1409 error_report_once("%s: invalid context entry: hi=%"PRIx64 1410 ", lo=%"PRIx64" (level %d not supported)", 1411 __func__, ce->hi, ce->lo, 1412 vtd_ce_get_level(ce)); 1413 return -VTD_FR_CONTEXT_ENTRY_INV; 1414 } 1415 1416 if (!s->root_scalable) { 1417 /* Do translation type check */ 1418 if (!vtd_ce_type_check(x86_iommu, ce)) { 1419 /* Errors dumped in vtd_ce_type_check() */ 1420 return -VTD_FR_CONTEXT_ENTRY_INV; 1421 } 1422 } else { 1423 /* 1424 * Check if the programming of context-entry.rid2pasid 1425 * and corresponding pasid setting is valid, and thus 1426 * avoids to check pasid entry fetching result in future 1427 * helper function calling. 1428 */ 1429 ret_fr = vtd_ce_rid2pasid_check(s, ce); 1430 if (ret_fr) { 1431 return ret_fr; 1432 } 1433 } 1434 1435 return 0; 1436 } 1437 1438 static int vtd_sync_shadow_page_hook(IOMMUTLBEvent *event, 1439 void *private) 1440 { 1441 memory_region_notify_iommu(private, 0, *event); 1442 return 0; 1443 } 1444 1445 static uint16_t vtd_get_domain_id(IntelIOMMUState *s, 1446 VTDContextEntry *ce) 1447 { 1448 VTDPASIDEntry pe; 1449 1450 if (s->root_scalable) { 1451 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 1452 return VTD_SM_PASID_ENTRY_DID(pe.val[1]); 1453 } 1454 1455 return VTD_CONTEXT_ENTRY_DID(ce->hi); 1456 } 1457 1458 static int vtd_sync_shadow_page_table_range(VTDAddressSpace *vtd_as, 1459 VTDContextEntry *ce, 1460 hwaddr addr, hwaddr size) 1461 { 1462 IntelIOMMUState *s = vtd_as->iommu_state; 1463 vtd_page_walk_info info = { 1464 .hook_fn = vtd_sync_shadow_page_hook, 1465 .private = (void *)&vtd_as->iommu, 1466 .notify_unmap = true, 1467 .aw = s->aw_bits, 1468 .as = vtd_as, 1469 .domain_id = vtd_get_domain_id(s, ce), 1470 }; 1471 1472 return vtd_page_walk(s, ce, addr, addr + size, &info); 1473 } 1474 1475 static int vtd_sync_shadow_page_table(VTDAddressSpace *vtd_as) 1476 { 1477 int ret; 1478 VTDContextEntry ce; 1479 IOMMUNotifier *n; 1480 1481 if (!(vtd_as->iommu.iommu_notify_flags & IOMMU_NOTIFIER_IOTLB_EVENTS)) { 1482 return 0; 1483 } 1484 1485 ret = vtd_dev_to_context_entry(vtd_as->iommu_state, 1486 pci_bus_num(vtd_as->bus), 1487 vtd_as->devfn, &ce); 1488 if (ret) { 1489 if (ret == -VTD_FR_CONTEXT_ENTRY_P) { 1490 /* 1491 * It's a valid scenario to have a context entry that is 1492 * not present. For example, when a device is removed 1493 * from an existing domain then the context entry will be 1494 * zeroed by the guest before it was put into another 1495 * domain. When this happens, instead of synchronizing 1496 * the shadow pages we should invalidate all existing 1497 * mappings and notify the backends. 1498 */ 1499 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) { 1500 vtd_address_space_unmap(vtd_as, n); 1501 } 1502 ret = 0; 1503 } 1504 return ret; 1505 } 1506 1507 return vtd_sync_shadow_page_table_range(vtd_as, &ce, 0, UINT64_MAX); 1508 } 1509 1510 /* 1511 * Check if specific device is configed to bypass address 1512 * translation for DMA requests. In Scalable Mode, bypass 1513 * 1st-level translation or 2nd-level translation, it depends 1514 * on PGTT setting. 1515 */ 1516 static bool vtd_dev_pt_enabled(VTDAddressSpace *as) 1517 { 1518 IntelIOMMUState *s; 1519 VTDContextEntry ce; 1520 VTDPASIDEntry pe; 1521 int ret; 1522 1523 assert(as); 1524 1525 s = as->iommu_state; 1526 ret = vtd_dev_to_context_entry(s, pci_bus_num(as->bus), 1527 as->devfn, &ce); 1528 if (ret) { 1529 /* 1530 * Possibly failed to parse the context entry for some reason 1531 * (e.g., during init, or any guest configuration errors on 1532 * context entries). We should assume PT not enabled for 1533 * safety. 1534 */ 1535 return false; 1536 } 1537 1538 if (s->root_scalable) { 1539 ret = vtd_ce_get_rid2pasid_entry(s, &ce, &pe); 1540 if (ret) { 1541 error_report_once("%s: vtd_ce_get_rid2pasid_entry error: %"PRId32, 1542 __func__, ret); 1543 return false; 1544 } 1545 return (VTD_PE_GET_TYPE(&pe) == VTD_SM_PASID_ENTRY_PT); 1546 } 1547 1548 return (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH); 1549 } 1550 1551 /* Return whether the device is using IOMMU translation. */ 1552 static bool vtd_switch_address_space(VTDAddressSpace *as) 1553 { 1554 bool use_iommu; 1555 /* Whether we need to take the BQL on our own */ 1556 bool take_bql = !qemu_mutex_iothread_locked(); 1557 1558 assert(as); 1559 1560 use_iommu = as->iommu_state->dmar_enabled && !vtd_dev_pt_enabled(as); 1561 1562 trace_vtd_switch_address_space(pci_bus_num(as->bus), 1563 VTD_PCI_SLOT(as->devfn), 1564 VTD_PCI_FUNC(as->devfn), 1565 use_iommu); 1566 1567 /* 1568 * It's possible that we reach here without BQL, e.g., when called 1569 * from vtd_pt_enable_fast_path(). However the memory APIs need 1570 * it. We'd better make sure we have had it already, or, take it. 1571 */ 1572 if (take_bql) { 1573 qemu_mutex_lock_iothread(); 1574 } 1575 1576 /* Turn off first then on the other */ 1577 if (use_iommu) { 1578 memory_region_set_enabled(&as->nodmar, false); 1579 memory_region_set_enabled(MEMORY_REGION(&as->iommu), true); 1580 } else { 1581 memory_region_set_enabled(MEMORY_REGION(&as->iommu), false); 1582 memory_region_set_enabled(&as->nodmar, true); 1583 } 1584 1585 if (take_bql) { 1586 qemu_mutex_unlock_iothread(); 1587 } 1588 1589 return use_iommu; 1590 } 1591 1592 static void vtd_switch_address_space_all(IntelIOMMUState *s) 1593 { 1594 GHashTableIter iter; 1595 VTDBus *vtd_bus; 1596 int i; 1597 1598 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); 1599 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { 1600 for (i = 0; i < PCI_DEVFN_MAX; i++) { 1601 if (!vtd_bus->dev_as[i]) { 1602 continue; 1603 } 1604 vtd_switch_address_space(vtd_bus->dev_as[i]); 1605 } 1606 } 1607 } 1608 1609 static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn) 1610 { 1611 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL); 1612 } 1613 1614 static const bool vtd_qualified_faults[] = { 1615 [VTD_FR_RESERVED] = false, 1616 [VTD_FR_ROOT_ENTRY_P] = false, 1617 [VTD_FR_CONTEXT_ENTRY_P] = true, 1618 [VTD_FR_CONTEXT_ENTRY_INV] = true, 1619 [VTD_FR_ADDR_BEYOND_MGAW] = true, 1620 [VTD_FR_WRITE] = true, 1621 [VTD_FR_READ] = true, 1622 [VTD_FR_PAGING_ENTRY_INV] = true, 1623 [VTD_FR_ROOT_TABLE_INV] = false, 1624 [VTD_FR_CONTEXT_TABLE_INV] = false, 1625 [VTD_FR_ROOT_ENTRY_RSVD] = false, 1626 [VTD_FR_PAGING_ENTRY_RSVD] = true, 1627 [VTD_FR_CONTEXT_ENTRY_TT] = true, 1628 [VTD_FR_PASID_TABLE_INV] = false, 1629 [VTD_FR_RESERVED_ERR] = false, 1630 [VTD_FR_MAX] = false, 1631 }; 1632 1633 /* To see if a fault condition is "qualified", which is reported to software 1634 * only if the FPD field in the context-entry used to process the faulting 1635 * request is 0. 1636 */ 1637 static inline bool vtd_is_qualified_fault(VTDFaultReason fault) 1638 { 1639 return vtd_qualified_faults[fault]; 1640 } 1641 1642 static inline bool vtd_is_interrupt_addr(hwaddr addr) 1643 { 1644 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST; 1645 } 1646 1647 static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id) 1648 { 1649 VTDBus *vtd_bus; 1650 VTDAddressSpace *vtd_as; 1651 bool success = false; 1652 1653 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id)); 1654 if (!vtd_bus) { 1655 goto out; 1656 } 1657 1658 vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)]; 1659 if (!vtd_as) { 1660 goto out; 1661 } 1662 1663 if (vtd_switch_address_space(vtd_as) == false) { 1664 /* We switched off IOMMU region successfully. */ 1665 success = true; 1666 } 1667 1668 out: 1669 trace_vtd_pt_enable_fast_path(source_id, success); 1670 } 1671 1672 /* Map dev to context-entry then do a paging-structures walk to do a iommu 1673 * translation. 1674 * 1675 * Called from RCU critical section. 1676 * 1677 * @bus_num: The bus number 1678 * @devfn: The devfn, which is the combined of device and function number 1679 * @is_write: The access is a write operation 1680 * @entry: IOMMUTLBEntry that contain the addr to be translated and result 1681 * 1682 * Returns true if translation is successful, otherwise false. 1683 */ 1684 static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus, 1685 uint8_t devfn, hwaddr addr, bool is_write, 1686 IOMMUTLBEntry *entry) 1687 { 1688 IntelIOMMUState *s = vtd_as->iommu_state; 1689 VTDContextEntry ce; 1690 uint8_t bus_num = pci_bus_num(bus); 1691 VTDContextCacheEntry *cc_entry; 1692 uint64_t slpte, page_mask; 1693 uint32_t level; 1694 uint16_t source_id = vtd_make_source_id(bus_num, devfn); 1695 int ret_fr; 1696 bool is_fpd_set = false; 1697 bool reads = true; 1698 bool writes = true; 1699 uint8_t access_flags; 1700 VTDIOTLBEntry *iotlb_entry; 1701 1702 /* 1703 * We have standalone memory region for interrupt addresses, we 1704 * should never receive translation requests in this region. 1705 */ 1706 assert(!vtd_is_interrupt_addr(addr)); 1707 1708 vtd_iommu_lock(s); 1709 1710 cc_entry = &vtd_as->context_cache_entry; 1711 1712 /* Try to fetch slpte form IOTLB */ 1713 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr); 1714 if (iotlb_entry) { 1715 trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, 1716 iotlb_entry->domain_id); 1717 slpte = iotlb_entry->slpte; 1718 access_flags = iotlb_entry->access_flags; 1719 page_mask = iotlb_entry->mask; 1720 goto out; 1721 } 1722 1723 /* Try to fetch context-entry from cache first */ 1724 if (cc_entry->context_cache_gen == s->context_cache_gen) { 1725 trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi, 1726 cc_entry->context_entry.lo, 1727 cc_entry->context_cache_gen); 1728 ce = cc_entry->context_entry; 1729 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD; 1730 if (!is_fpd_set && s->root_scalable) { 1731 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); 1732 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); 1733 } 1734 } else { 1735 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce); 1736 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD; 1737 if (!ret_fr && !is_fpd_set && s->root_scalable) { 1738 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); 1739 } 1740 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); 1741 /* Update context-cache */ 1742 trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo, 1743 cc_entry->context_cache_gen, 1744 s->context_cache_gen); 1745 cc_entry->context_entry = ce; 1746 cc_entry->context_cache_gen = s->context_cache_gen; 1747 } 1748 1749 /* 1750 * We don't need to translate for pass-through context entries. 1751 * Also, let's ignore IOTLB caching as well for PT devices. 1752 */ 1753 if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) { 1754 entry->iova = addr & VTD_PAGE_MASK_4K; 1755 entry->translated_addr = entry->iova; 1756 entry->addr_mask = ~VTD_PAGE_MASK_4K; 1757 entry->perm = IOMMU_RW; 1758 trace_vtd_translate_pt(source_id, entry->iova); 1759 1760 /* 1761 * When this happens, it means firstly caching-mode is not 1762 * enabled, and this is the first passthrough translation for 1763 * the device. Let's enable the fast path for passthrough. 1764 * 1765 * When passthrough is disabled again for the device, we can 1766 * capture it via the context entry invalidation, then the 1767 * IOMMU region can be swapped back. 1768 */ 1769 vtd_pt_enable_fast_path(s, source_id); 1770 vtd_iommu_unlock(s); 1771 return true; 1772 } 1773 1774 ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level, 1775 &reads, &writes, s->aw_bits); 1776 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); 1777 1778 page_mask = vtd_slpt_level_page_mask(level); 1779 access_flags = IOMMU_ACCESS_FLAG(reads, writes); 1780 vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce), addr, slpte, 1781 access_flags, level); 1782 out: 1783 vtd_iommu_unlock(s); 1784 entry->iova = addr & page_mask; 1785 entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask; 1786 entry->addr_mask = ~page_mask; 1787 entry->perm = access_flags; 1788 return true; 1789 1790 error: 1791 vtd_iommu_unlock(s); 1792 entry->iova = 0; 1793 entry->translated_addr = 0; 1794 entry->addr_mask = 0; 1795 entry->perm = IOMMU_NONE; 1796 return false; 1797 } 1798 1799 static void vtd_root_table_setup(IntelIOMMUState *s) 1800 { 1801 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG); 1802 s->root &= VTD_RTADDR_ADDR_MASK(s->aw_bits); 1803 1804 vtd_update_scalable_state(s); 1805 1806 trace_vtd_reg_dmar_root(s->root, s->root_scalable); 1807 } 1808 1809 static void vtd_iec_notify_all(IntelIOMMUState *s, bool global, 1810 uint32_t index, uint32_t mask) 1811 { 1812 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask); 1813 } 1814 1815 static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s) 1816 { 1817 uint64_t value = 0; 1818 value = vtd_get_quad_raw(s, DMAR_IRTA_REG); 1819 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1); 1820 s->intr_root = value & VTD_IRTA_ADDR_MASK(s->aw_bits); 1821 s->intr_eime = value & VTD_IRTA_EIME; 1822 1823 /* Notify global invalidation */ 1824 vtd_iec_notify_all(s, true, 0, 0); 1825 1826 trace_vtd_reg_ir_root(s->intr_root, s->intr_size); 1827 } 1828 1829 static void vtd_iommu_replay_all(IntelIOMMUState *s) 1830 { 1831 VTDAddressSpace *vtd_as; 1832 1833 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { 1834 vtd_sync_shadow_page_table(vtd_as); 1835 } 1836 } 1837 1838 static void vtd_context_global_invalidate(IntelIOMMUState *s) 1839 { 1840 trace_vtd_inv_desc_cc_global(); 1841 /* Protects context cache */ 1842 vtd_iommu_lock(s); 1843 s->context_cache_gen++; 1844 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) { 1845 vtd_reset_context_cache_locked(s); 1846 } 1847 vtd_iommu_unlock(s); 1848 vtd_address_space_refresh_all(s); 1849 /* 1850 * From VT-d spec 6.5.2.1, a global context entry invalidation 1851 * should be followed by a IOTLB global invalidation, so we should 1852 * be safe even without this. Hoewever, let's replay the region as 1853 * well to be safer, and go back here when we need finer tunes for 1854 * VT-d emulation codes. 1855 */ 1856 vtd_iommu_replay_all(s); 1857 } 1858 1859 /* Do a context-cache device-selective invalidation. 1860 * @func_mask: FM field after shifting 1861 */ 1862 static void vtd_context_device_invalidate(IntelIOMMUState *s, 1863 uint16_t source_id, 1864 uint16_t func_mask) 1865 { 1866 uint16_t mask; 1867 VTDBus *vtd_bus; 1868 VTDAddressSpace *vtd_as; 1869 uint8_t bus_n, devfn; 1870 uint16_t devfn_it; 1871 1872 trace_vtd_inv_desc_cc_devices(source_id, func_mask); 1873 1874 switch (func_mask & 3) { 1875 case 0: 1876 mask = 0; /* No bits in the SID field masked */ 1877 break; 1878 case 1: 1879 mask = 4; /* Mask bit 2 in the SID field */ 1880 break; 1881 case 2: 1882 mask = 6; /* Mask bit 2:1 in the SID field */ 1883 break; 1884 case 3: 1885 mask = 7; /* Mask bit 2:0 in the SID field */ 1886 break; 1887 default: 1888 g_assert_not_reached(); 1889 } 1890 mask = ~mask; 1891 1892 bus_n = VTD_SID_TO_BUS(source_id); 1893 vtd_bus = vtd_find_as_from_bus_num(s, bus_n); 1894 if (vtd_bus) { 1895 devfn = VTD_SID_TO_DEVFN(source_id); 1896 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { 1897 vtd_as = vtd_bus->dev_as[devfn_it]; 1898 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) { 1899 trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it), 1900 VTD_PCI_FUNC(devfn_it)); 1901 vtd_iommu_lock(s); 1902 vtd_as->context_cache_entry.context_cache_gen = 0; 1903 vtd_iommu_unlock(s); 1904 /* 1905 * Do switch address space when needed, in case if the 1906 * device passthrough bit is switched. 1907 */ 1908 vtd_switch_address_space(vtd_as); 1909 /* 1910 * So a device is moving out of (or moving into) a 1911 * domain, resync the shadow page table. 1912 * This won't bring bad even if we have no such 1913 * notifier registered - the IOMMU notification 1914 * framework will skip MAP notifications if that 1915 * happened. 1916 */ 1917 vtd_sync_shadow_page_table(vtd_as); 1918 } 1919 } 1920 } 1921 } 1922 1923 /* Context-cache invalidation 1924 * Returns the Context Actual Invalidation Granularity. 1925 * @val: the content of the CCMD_REG 1926 */ 1927 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val) 1928 { 1929 uint64_t caig; 1930 uint64_t type = val & VTD_CCMD_CIRG_MASK; 1931 1932 switch (type) { 1933 case VTD_CCMD_DOMAIN_INVL: 1934 /* Fall through */ 1935 case VTD_CCMD_GLOBAL_INVL: 1936 caig = VTD_CCMD_GLOBAL_INVL_A; 1937 vtd_context_global_invalidate(s); 1938 break; 1939 1940 case VTD_CCMD_DEVICE_INVL: 1941 caig = VTD_CCMD_DEVICE_INVL_A; 1942 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val)); 1943 break; 1944 1945 default: 1946 error_report_once("%s: invalid context: 0x%" PRIx64, 1947 __func__, val); 1948 caig = 0; 1949 } 1950 return caig; 1951 } 1952 1953 static void vtd_iotlb_global_invalidate(IntelIOMMUState *s) 1954 { 1955 trace_vtd_inv_desc_iotlb_global(); 1956 vtd_reset_iotlb(s); 1957 vtd_iommu_replay_all(s); 1958 } 1959 1960 static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id) 1961 { 1962 VTDContextEntry ce; 1963 VTDAddressSpace *vtd_as; 1964 1965 trace_vtd_inv_desc_iotlb_domain(domain_id); 1966 1967 vtd_iommu_lock(s); 1968 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain, 1969 &domain_id); 1970 vtd_iommu_unlock(s); 1971 1972 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { 1973 if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), 1974 vtd_as->devfn, &ce) && 1975 domain_id == vtd_get_domain_id(s, &ce)) { 1976 vtd_sync_shadow_page_table(vtd_as); 1977 } 1978 } 1979 } 1980 1981 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s, 1982 uint16_t domain_id, hwaddr addr, 1983 uint8_t am) 1984 { 1985 VTDAddressSpace *vtd_as; 1986 VTDContextEntry ce; 1987 int ret; 1988 hwaddr size = (1 << am) * VTD_PAGE_SIZE; 1989 1990 QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) { 1991 ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), 1992 vtd_as->devfn, &ce); 1993 if (!ret && domain_id == vtd_get_domain_id(s, &ce)) { 1994 if (vtd_as_has_map_notifier(vtd_as)) { 1995 /* 1996 * As long as we have MAP notifications registered in 1997 * any of our IOMMU notifiers, we need to sync the 1998 * shadow page table. 1999 */ 2000 vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size); 2001 } else { 2002 /* 2003 * For UNMAP-only notifiers, we don't need to walk the 2004 * page tables. We just deliver the PSI down to 2005 * invalidate caches. 2006 */ 2007 IOMMUTLBEvent event = { 2008 .type = IOMMU_NOTIFIER_UNMAP, 2009 .entry = { 2010 .target_as = &address_space_memory, 2011 .iova = addr, 2012 .translated_addr = 0, 2013 .addr_mask = size - 1, 2014 .perm = IOMMU_NONE, 2015 }, 2016 }; 2017 memory_region_notify_iommu(&vtd_as->iommu, 0, event); 2018 } 2019 } 2020 } 2021 } 2022 2023 static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id, 2024 hwaddr addr, uint8_t am) 2025 { 2026 VTDIOTLBPageInvInfo info; 2027 2028 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am); 2029 2030 assert(am <= VTD_MAMV); 2031 info.domain_id = domain_id; 2032 info.addr = addr; 2033 info.mask = ~((1 << am) - 1); 2034 vtd_iommu_lock(s); 2035 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info); 2036 vtd_iommu_unlock(s); 2037 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am); 2038 } 2039 2040 /* Flush IOTLB 2041 * Returns the IOTLB Actual Invalidation Granularity. 2042 * @val: the content of the IOTLB_REG 2043 */ 2044 static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val) 2045 { 2046 uint64_t iaig; 2047 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK; 2048 uint16_t domain_id; 2049 hwaddr addr; 2050 uint8_t am; 2051 2052 switch (type) { 2053 case VTD_TLB_GLOBAL_FLUSH: 2054 iaig = VTD_TLB_GLOBAL_FLUSH_A; 2055 vtd_iotlb_global_invalidate(s); 2056 break; 2057 2058 case VTD_TLB_DSI_FLUSH: 2059 domain_id = VTD_TLB_DID(val); 2060 iaig = VTD_TLB_DSI_FLUSH_A; 2061 vtd_iotlb_domain_invalidate(s, domain_id); 2062 break; 2063 2064 case VTD_TLB_PSI_FLUSH: 2065 domain_id = VTD_TLB_DID(val); 2066 addr = vtd_get_quad_raw(s, DMAR_IVA_REG); 2067 am = VTD_IVA_AM(addr); 2068 addr = VTD_IVA_ADDR(addr); 2069 if (am > VTD_MAMV) { 2070 error_report_once("%s: address mask overflow: 0x%" PRIx64, 2071 __func__, vtd_get_quad_raw(s, DMAR_IVA_REG)); 2072 iaig = 0; 2073 break; 2074 } 2075 iaig = VTD_TLB_PSI_FLUSH_A; 2076 vtd_iotlb_page_invalidate(s, domain_id, addr, am); 2077 break; 2078 2079 default: 2080 error_report_once("%s: invalid granularity: 0x%" PRIx64, 2081 __func__, val); 2082 iaig = 0; 2083 } 2084 return iaig; 2085 } 2086 2087 static void vtd_fetch_inv_desc(IntelIOMMUState *s); 2088 2089 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s) 2090 { 2091 return s->qi_enabled && (s->iq_tail == s->iq_head) && 2092 (s->iq_last_desc_type == VTD_INV_DESC_WAIT); 2093 } 2094 2095 static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en) 2096 { 2097 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG); 2098 2099 trace_vtd_inv_qi_enable(en); 2100 2101 if (en) { 2102 s->iq = iqa_val & VTD_IQA_IQA_MASK(s->aw_bits); 2103 /* 2^(x+8) entries */ 2104 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8 - (s->iq_dw ? 1 : 0)); 2105 s->qi_enabled = true; 2106 trace_vtd_inv_qi_setup(s->iq, s->iq_size); 2107 /* Ok - report back to driver */ 2108 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES); 2109 2110 if (s->iq_tail != 0) { 2111 /* 2112 * This is a spec violation but Windows guests are known to set up 2113 * Queued Invalidation this way so we allow the write and process 2114 * Invalidation Descriptors right away. 2115 */ 2116 trace_vtd_warn_invalid_qi_tail(s->iq_tail); 2117 if (!(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) { 2118 vtd_fetch_inv_desc(s); 2119 } 2120 } 2121 } else { 2122 if (vtd_queued_inv_disable_check(s)) { 2123 /* disable Queued Invalidation */ 2124 vtd_set_quad_raw(s, DMAR_IQH_REG, 0); 2125 s->iq_head = 0; 2126 s->qi_enabled = false; 2127 /* Ok - report back to driver */ 2128 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0); 2129 } else { 2130 error_report_once("%s: detected improper state when disable QI " 2131 "(head=0x%x, tail=0x%x, last_type=%d)", 2132 __func__, 2133 s->iq_head, s->iq_tail, s->iq_last_desc_type); 2134 } 2135 } 2136 } 2137 2138 /* Set Root Table Pointer */ 2139 static void vtd_handle_gcmd_srtp(IntelIOMMUState *s) 2140 { 2141 vtd_root_table_setup(s); 2142 /* Ok - report back to driver */ 2143 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS); 2144 vtd_reset_caches(s); 2145 vtd_address_space_refresh_all(s); 2146 } 2147 2148 /* Set Interrupt Remap Table Pointer */ 2149 static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s) 2150 { 2151 vtd_interrupt_remap_table_setup(s); 2152 /* Ok - report back to driver */ 2153 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS); 2154 } 2155 2156 /* Handle Translation Enable/Disable */ 2157 static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en) 2158 { 2159 if (s->dmar_enabled == en) { 2160 return; 2161 } 2162 2163 trace_vtd_dmar_enable(en); 2164 2165 if (en) { 2166 s->dmar_enabled = true; 2167 /* Ok - report back to driver */ 2168 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES); 2169 } else { 2170 s->dmar_enabled = false; 2171 2172 /* Clear the index of Fault Recording Register */ 2173 s->next_frcd_reg = 0; 2174 /* Ok - report back to driver */ 2175 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0); 2176 } 2177 2178 vtd_reset_caches(s); 2179 vtd_address_space_refresh_all(s); 2180 } 2181 2182 /* Handle Interrupt Remap Enable/Disable */ 2183 static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en) 2184 { 2185 trace_vtd_ir_enable(en); 2186 2187 if (en) { 2188 s->intr_enabled = true; 2189 /* Ok - report back to driver */ 2190 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES); 2191 } else { 2192 s->intr_enabled = false; 2193 /* Ok - report back to driver */ 2194 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0); 2195 } 2196 } 2197 2198 /* Handle write to Global Command Register */ 2199 static void vtd_handle_gcmd_write(IntelIOMMUState *s) 2200 { 2201 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG); 2202 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG); 2203 uint32_t changed = status ^ val; 2204 2205 trace_vtd_reg_write_gcmd(status, val); 2206 if (changed & VTD_GCMD_TE) { 2207 /* Translation enable/disable */ 2208 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE); 2209 } 2210 if (val & VTD_GCMD_SRTP) { 2211 /* Set/update the root-table pointer */ 2212 vtd_handle_gcmd_srtp(s); 2213 } 2214 if (changed & VTD_GCMD_QIE) { 2215 /* Queued Invalidation Enable */ 2216 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE); 2217 } 2218 if (val & VTD_GCMD_SIRTP) { 2219 /* Set/update the interrupt remapping root-table pointer */ 2220 vtd_handle_gcmd_sirtp(s); 2221 } 2222 if (changed & VTD_GCMD_IRE) { 2223 /* Interrupt remap enable/disable */ 2224 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE); 2225 } 2226 } 2227 2228 /* Handle write to Context Command Register */ 2229 static void vtd_handle_ccmd_write(IntelIOMMUState *s) 2230 { 2231 uint64_t ret; 2232 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG); 2233 2234 /* Context-cache invalidation request */ 2235 if (val & VTD_CCMD_ICC) { 2236 if (s->qi_enabled) { 2237 error_report_once("Queued Invalidation enabled, " 2238 "should not use register-based invalidation"); 2239 return; 2240 } 2241 ret = vtd_context_cache_invalidate(s, val); 2242 /* Invalidation completed. Change something to show */ 2243 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL); 2244 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK, 2245 ret); 2246 } 2247 } 2248 2249 /* Handle write to IOTLB Invalidation Register */ 2250 static void vtd_handle_iotlb_write(IntelIOMMUState *s) 2251 { 2252 uint64_t ret; 2253 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG); 2254 2255 /* IOTLB invalidation request */ 2256 if (val & VTD_TLB_IVT) { 2257 if (s->qi_enabled) { 2258 error_report_once("Queued Invalidation enabled, " 2259 "should not use register-based invalidation"); 2260 return; 2261 } 2262 ret = vtd_iotlb_flush(s, val); 2263 /* Invalidation completed. Change something to show */ 2264 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL); 2265 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, 2266 VTD_TLB_FLUSH_GRANU_MASK_A, ret); 2267 } 2268 } 2269 2270 /* Fetch an Invalidation Descriptor from the Invalidation Queue */ 2271 static bool vtd_get_inv_desc(IntelIOMMUState *s, 2272 VTDInvDesc *inv_desc) 2273 { 2274 dma_addr_t base_addr = s->iq; 2275 uint32_t offset = s->iq_head; 2276 uint32_t dw = s->iq_dw ? 32 : 16; 2277 dma_addr_t addr = base_addr + offset * dw; 2278 2279 if (dma_memory_read(&address_space_memory, addr, inv_desc, dw)) { 2280 error_report_once("Read INV DESC failed."); 2281 return false; 2282 } 2283 inv_desc->lo = le64_to_cpu(inv_desc->lo); 2284 inv_desc->hi = le64_to_cpu(inv_desc->hi); 2285 if (dw == 32) { 2286 inv_desc->val[2] = le64_to_cpu(inv_desc->val[2]); 2287 inv_desc->val[3] = le64_to_cpu(inv_desc->val[3]); 2288 } 2289 return true; 2290 } 2291 2292 static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) 2293 { 2294 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) || 2295 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) { 2296 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64 2297 " (reserved nonzero)", __func__, inv_desc->hi, 2298 inv_desc->lo); 2299 return false; 2300 } 2301 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) { 2302 /* Status Write */ 2303 uint32_t status_data = (uint32_t)(inv_desc->lo >> 2304 VTD_INV_DESC_WAIT_DATA_SHIFT); 2305 2306 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF)); 2307 2308 /* FIXME: need to be masked with HAW? */ 2309 dma_addr_t status_addr = inv_desc->hi; 2310 trace_vtd_inv_desc_wait_sw(status_addr, status_data); 2311 status_data = cpu_to_le32(status_data); 2312 if (dma_memory_write(&address_space_memory, status_addr, &status_data, 2313 sizeof(status_data))) { 2314 trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo); 2315 return false; 2316 } 2317 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) { 2318 /* Interrupt flag */ 2319 vtd_generate_completion_event(s); 2320 } else { 2321 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64 2322 " (unknown type)", __func__, inv_desc->hi, 2323 inv_desc->lo); 2324 return false; 2325 } 2326 return true; 2327 } 2328 2329 static bool vtd_process_context_cache_desc(IntelIOMMUState *s, 2330 VTDInvDesc *inv_desc) 2331 { 2332 uint16_t sid, fmask; 2333 2334 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) { 2335 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64 2336 " (reserved nonzero)", __func__, inv_desc->hi, 2337 inv_desc->lo); 2338 return false; 2339 } 2340 switch (inv_desc->lo & VTD_INV_DESC_CC_G) { 2341 case VTD_INV_DESC_CC_DOMAIN: 2342 trace_vtd_inv_desc_cc_domain( 2343 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo)); 2344 /* Fall through */ 2345 case VTD_INV_DESC_CC_GLOBAL: 2346 vtd_context_global_invalidate(s); 2347 break; 2348 2349 case VTD_INV_DESC_CC_DEVICE: 2350 sid = VTD_INV_DESC_CC_SID(inv_desc->lo); 2351 fmask = VTD_INV_DESC_CC_FM(inv_desc->lo); 2352 vtd_context_device_invalidate(s, sid, fmask); 2353 break; 2354 2355 default: 2356 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64 2357 " (invalid type)", __func__, inv_desc->hi, 2358 inv_desc->lo); 2359 return false; 2360 } 2361 return true; 2362 } 2363 2364 static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) 2365 { 2366 uint16_t domain_id; 2367 uint8_t am; 2368 hwaddr addr; 2369 2370 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) || 2371 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) { 2372 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 2373 ", lo=0x%"PRIx64" (reserved bits unzero)", 2374 __func__, inv_desc->hi, inv_desc->lo); 2375 return false; 2376 } 2377 2378 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) { 2379 case VTD_INV_DESC_IOTLB_GLOBAL: 2380 vtd_iotlb_global_invalidate(s); 2381 break; 2382 2383 case VTD_INV_DESC_IOTLB_DOMAIN: 2384 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo); 2385 vtd_iotlb_domain_invalidate(s, domain_id); 2386 break; 2387 2388 case VTD_INV_DESC_IOTLB_PAGE: 2389 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo); 2390 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi); 2391 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi); 2392 if (am > VTD_MAMV) { 2393 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 2394 ", lo=0x%"PRIx64" (am=%u > VTD_MAMV=%u)", 2395 __func__, inv_desc->hi, inv_desc->lo, 2396 am, (unsigned)VTD_MAMV); 2397 return false; 2398 } 2399 vtd_iotlb_page_invalidate(s, domain_id, addr, am); 2400 break; 2401 2402 default: 2403 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 2404 ", lo=0x%"PRIx64" (type mismatch: 0x%llx)", 2405 __func__, inv_desc->hi, inv_desc->lo, 2406 inv_desc->lo & VTD_INV_DESC_IOTLB_G); 2407 return false; 2408 } 2409 return true; 2410 } 2411 2412 static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, 2413 VTDInvDesc *inv_desc) 2414 { 2415 trace_vtd_inv_desc_iec(inv_desc->iec.granularity, 2416 inv_desc->iec.index, 2417 inv_desc->iec.index_mask); 2418 2419 vtd_iec_notify_all(s, !inv_desc->iec.granularity, 2420 inv_desc->iec.index, 2421 inv_desc->iec.index_mask); 2422 return true; 2423 } 2424 2425 static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s, 2426 VTDInvDesc *inv_desc) 2427 { 2428 VTDAddressSpace *vtd_dev_as; 2429 IOMMUTLBEvent event; 2430 struct VTDBus *vtd_bus; 2431 hwaddr addr; 2432 uint64_t sz; 2433 uint16_t sid; 2434 uint8_t devfn; 2435 bool size; 2436 uint8_t bus_num; 2437 2438 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi); 2439 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo); 2440 devfn = sid & 0xff; 2441 bus_num = sid >> 8; 2442 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi); 2443 2444 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) || 2445 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) { 2446 error_report_once("%s: invalid dev-iotlb inv desc: hi=%"PRIx64 2447 ", lo=%"PRIx64" (reserved nonzero)", __func__, 2448 inv_desc->hi, inv_desc->lo); 2449 return false; 2450 } 2451 2452 vtd_bus = vtd_find_as_from_bus_num(s, bus_num); 2453 if (!vtd_bus) { 2454 goto done; 2455 } 2456 2457 vtd_dev_as = vtd_bus->dev_as[devfn]; 2458 if (!vtd_dev_as) { 2459 goto done; 2460 } 2461 2462 /* According to ATS spec table 2.4: 2463 * S = 0, bits 15:12 = xxxx range size: 4K 2464 * S = 1, bits 15:12 = xxx0 range size: 8K 2465 * S = 1, bits 15:12 = xx01 range size: 16K 2466 * S = 1, bits 15:12 = x011 range size: 32K 2467 * S = 1, bits 15:12 = 0111 range size: 64K 2468 * ... 2469 */ 2470 if (size) { 2471 sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT); 2472 addr &= ~(sz - 1); 2473 } else { 2474 sz = VTD_PAGE_SIZE; 2475 } 2476 2477 event.type = IOMMU_NOTIFIER_DEVIOTLB_UNMAP; 2478 event.entry.target_as = &vtd_dev_as->as; 2479 event.entry.addr_mask = sz - 1; 2480 event.entry.iova = addr; 2481 event.entry.perm = IOMMU_NONE; 2482 event.entry.translated_addr = 0; 2483 memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event); 2484 2485 done: 2486 return true; 2487 } 2488 2489 static bool vtd_process_inv_desc(IntelIOMMUState *s) 2490 { 2491 VTDInvDesc inv_desc; 2492 uint8_t desc_type; 2493 2494 trace_vtd_inv_qi_head(s->iq_head); 2495 if (!vtd_get_inv_desc(s, &inv_desc)) { 2496 s->iq_last_desc_type = VTD_INV_DESC_NONE; 2497 return false; 2498 } 2499 2500 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE; 2501 /* FIXME: should update at first or at last? */ 2502 s->iq_last_desc_type = desc_type; 2503 2504 switch (desc_type) { 2505 case VTD_INV_DESC_CC: 2506 trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo); 2507 if (!vtd_process_context_cache_desc(s, &inv_desc)) { 2508 return false; 2509 } 2510 break; 2511 2512 case VTD_INV_DESC_IOTLB: 2513 trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo); 2514 if (!vtd_process_iotlb_desc(s, &inv_desc)) { 2515 return false; 2516 } 2517 break; 2518 2519 /* 2520 * TODO: the entity of below two cases will be implemented in future series. 2521 * To make guest (which integrates scalable mode support patch set in 2522 * iommu driver) work, just return true is enough so far. 2523 */ 2524 case VTD_INV_DESC_PC: 2525 break; 2526 2527 case VTD_INV_DESC_PIOTLB: 2528 break; 2529 2530 case VTD_INV_DESC_WAIT: 2531 trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo); 2532 if (!vtd_process_wait_desc(s, &inv_desc)) { 2533 return false; 2534 } 2535 break; 2536 2537 case VTD_INV_DESC_IEC: 2538 trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo); 2539 if (!vtd_process_inv_iec_desc(s, &inv_desc)) { 2540 return false; 2541 } 2542 break; 2543 2544 case VTD_INV_DESC_DEVICE: 2545 trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo); 2546 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) { 2547 return false; 2548 } 2549 break; 2550 2551 default: 2552 error_report_once("%s: invalid inv desc: hi=%"PRIx64", lo=%"PRIx64 2553 " (unknown type)", __func__, inv_desc.hi, 2554 inv_desc.lo); 2555 return false; 2556 } 2557 s->iq_head++; 2558 if (s->iq_head == s->iq_size) { 2559 s->iq_head = 0; 2560 } 2561 return true; 2562 } 2563 2564 /* Try to fetch and process more Invalidation Descriptors */ 2565 static void vtd_fetch_inv_desc(IntelIOMMUState *s) 2566 { 2567 int qi_shift; 2568 2569 /* Refer to 10.4.23 of VT-d spec 3.0 */ 2570 qi_shift = s->iq_dw ? VTD_IQH_QH_SHIFT_5 : VTD_IQH_QH_SHIFT_4; 2571 2572 trace_vtd_inv_qi_fetch(); 2573 2574 if (s->iq_tail >= s->iq_size) { 2575 /* Detects an invalid Tail pointer */ 2576 error_report_once("%s: detected invalid QI tail " 2577 "(tail=0x%x, size=0x%x)", 2578 __func__, s->iq_tail, s->iq_size); 2579 vtd_handle_inv_queue_error(s); 2580 return; 2581 } 2582 while (s->iq_head != s->iq_tail) { 2583 if (!vtd_process_inv_desc(s)) { 2584 /* Invalidation Queue Errors */ 2585 vtd_handle_inv_queue_error(s); 2586 break; 2587 } 2588 /* Must update the IQH_REG in time */ 2589 vtd_set_quad_raw(s, DMAR_IQH_REG, 2590 (((uint64_t)(s->iq_head)) << qi_shift) & 2591 VTD_IQH_QH_MASK); 2592 } 2593 } 2594 2595 /* Handle write to Invalidation Queue Tail Register */ 2596 static void vtd_handle_iqt_write(IntelIOMMUState *s) 2597 { 2598 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG); 2599 2600 if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) { 2601 error_report_once("%s: RSV bit is set: val=0x%"PRIx64, 2602 __func__, val); 2603 return; 2604 } 2605 s->iq_tail = VTD_IQT_QT(s->iq_dw, val); 2606 trace_vtd_inv_qi_tail(s->iq_tail); 2607 2608 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) { 2609 /* Process Invalidation Queue here */ 2610 vtd_fetch_inv_desc(s); 2611 } 2612 } 2613 2614 static void vtd_handle_fsts_write(IntelIOMMUState *s) 2615 { 2616 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); 2617 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG); 2618 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE; 2619 2620 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) { 2621 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); 2622 trace_vtd_fsts_clear_ip(); 2623 } 2624 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation 2625 * Descriptors if there are any when Queued Invalidation is enabled? 2626 */ 2627 } 2628 2629 static void vtd_handle_fectl_write(IntelIOMMUState *s) 2630 { 2631 uint32_t fectl_reg; 2632 /* FIXME: when software clears the IM field, check the IP field. But do we 2633 * need to compare the old value and the new value to conclude that 2634 * software clears the IM field? Or just check if the IM field is zero? 2635 */ 2636 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG); 2637 2638 trace_vtd_reg_write_fectl(fectl_reg); 2639 2640 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) { 2641 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG); 2642 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); 2643 } 2644 } 2645 2646 static void vtd_handle_ics_write(IntelIOMMUState *s) 2647 { 2648 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG); 2649 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG); 2650 2651 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) { 2652 trace_vtd_reg_ics_clear_ip(); 2653 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); 2654 } 2655 } 2656 2657 static void vtd_handle_iectl_write(IntelIOMMUState *s) 2658 { 2659 uint32_t iectl_reg; 2660 /* FIXME: when software clears the IM field, check the IP field. But do we 2661 * need to compare the old value and the new value to conclude that 2662 * software clears the IM field? Or just check if the IM field is zero? 2663 */ 2664 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG); 2665 2666 trace_vtd_reg_write_iectl(iectl_reg); 2667 2668 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) { 2669 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG); 2670 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); 2671 } 2672 } 2673 2674 static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size) 2675 { 2676 IntelIOMMUState *s = opaque; 2677 uint64_t val; 2678 2679 trace_vtd_reg_read(addr, size); 2680 2681 if (addr + size > DMAR_REG_SIZE) { 2682 error_report_once("%s: MMIO over range: addr=0x%" PRIx64 2683 " size=0x%x", __func__, addr, size); 2684 return (uint64_t)-1; 2685 } 2686 2687 switch (addr) { 2688 /* Root Table Address Register, 64-bit */ 2689 case DMAR_RTADDR_REG: 2690 val = vtd_get_quad_raw(s, DMAR_RTADDR_REG); 2691 if (size == 4) { 2692 val = val & ((1ULL << 32) - 1); 2693 } 2694 break; 2695 2696 case DMAR_RTADDR_REG_HI: 2697 assert(size == 4); 2698 val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32; 2699 break; 2700 2701 /* Invalidation Queue Address Register, 64-bit */ 2702 case DMAR_IQA_REG: 2703 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS); 2704 if (size == 4) { 2705 val = val & ((1ULL << 32) - 1); 2706 } 2707 break; 2708 2709 case DMAR_IQA_REG_HI: 2710 assert(size == 4); 2711 val = s->iq >> 32; 2712 break; 2713 2714 default: 2715 if (size == 4) { 2716 val = vtd_get_long(s, addr); 2717 } else { 2718 val = vtd_get_quad(s, addr); 2719 } 2720 } 2721 2722 return val; 2723 } 2724 2725 static void vtd_mem_write(void *opaque, hwaddr addr, 2726 uint64_t val, unsigned size) 2727 { 2728 IntelIOMMUState *s = opaque; 2729 2730 trace_vtd_reg_write(addr, size, val); 2731 2732 if (addr + size > DMAR_REG_SIZE) { 2733 error_report_once("%s: MMIO over range: addr=0x%" PRIx64 2734 " size=0x%x", __func__, addr, size); 2735 return; 2736 } 2737 2738 switch (addr) { 2739 /* Global Command Register, 32-bit */ 2740 case DMAR_GCMD_REG: 2741 vtd_set_long(s, addr, val); 2742 vtd_handle_gcmd_write(s); 2743 break; 2744 2745 /* Context Command Register, 64-bit */ 2746 case DMAR_CCMD_REG: 2747 if (size == 4) { 2748 vtd_set_long(s, addr, val); 2749 } else { 2750 vtd_set_quad(s, addr, val); 2751 vtd_handle_ccmd_write(s); 2752 } 2753 break; 2754 2755 case DMAR_CCMD_REG_HI: 2756 assert(size == 4); 2757 vtd_set_long(s, addr, val); 2758 vtd_handle_ccmd_write(s); 2759 break; 2760 2761 /* IOTLB Invalidation Register, 64-bit */ 2762 case DMAR_IOTLB_REG: 2763 if (size == 4) { 2764 vtd_set_long(s, addr, val); 2765 } else { 2766 vtd_set_quad(s, addr, val); 2767 vtd_handle_iotlb_write(s); 2768 } 2769 break; 2770 2771 case DMAR_IOTLB_REG_HI: 2772 assert(size == 4); 2773 vtd_set_long(s, addr, val); 2774 vtd_handle_iotlb_write(s); 2775 break; 2776 2777 /* Invalidate Address Register, 64-bit */ 2778 case DMAR_IVA_REG: 2779 if (size == 4) { 2780 vtd_set_long(s, addr, val); 2781 } else { 2782 vtd_set_quad(s, addr, val); 2783 } 2784 break; 2785 2786 case DMAR_IVA_REG_HI: 2787 assert(size == 4); 2788 vtd_set_long(s, addr, val); 2789 break; 2790 2791 /* Fault Status Register, 32-bit */ 2792 case DMAR_FSTS_REG: 2793 assert(size == 4); 2794 vtd_set_long(s, addr, val); 2795 vtd_handle_fsts_write(s); 2796 break; 2797 2798 /* Fault Event Control Register, 32-bit */ 2799 case DMAR_FECTL_REG: 2800 assert(size == 4); 2801 vtd_set_long(s, addr, val); 2802 vtd_handle_fectl_write(s); 2803 break; 2804 2805 /* Fault Event Data Register, 32-bit */ 2806 case DMAR_FEDATA_REG: 2807 assert(size == 4); 2808 vtd_set_long(s, addr, val); 2809 break; 2810 2811 /* Fault Event Address Register, 32-bit */ 2812 case DMAR_FEADDR_REG: 2813 if (size == 4) { 2814 vtd_set_long(s, addr, val); 2815 } else { 2816 /* 2817 * While the register is 32-bit only, some guests (Xen...) write to 2818 * it with 64-bit. 2819 */ 2820 vtd_set_quad(s, addr, val); 2821 } 2822 break; 2823 2824 /* Fault Event Upper Address Register, 32-bit */ 2825 case DMAR_FEUADDR_REG: 2826 assert(size == 4); 2827 vtd_set_long(s, addr, val); 2828 break; 2829 2830 /* Protected Memory Enable Register, 32-bit */ 2831 case DMAR_PMEN_REG: 2832 assert(size == 4); 2833 vtd_set_long(s, addr, val); 2834 break; 2835 2836 /* Root Table Address Register, 64-bit */ 2837 case DMAR_RTADDR_REG: 2838 if (size == 4) { 2839 vtd_set_long(s, addr, val); 2840 } else { 2841 vtd_set_quad(s, addr, val); 2842 } 2843 break; 2844 2845 case DMAR_RTADDR_REG_HI: 2846 assert(size == 4); 2847 vtd_set_long(s, addr, val); 2848 break; 2849 2850 /* Invalidation Queue Tail Register, 64-bit */ 2851 case DMAR_IQT_REG: 2852 if (size == 4) { 2853 vtd_set_long(s, addr, val); 2854 } else { 2855 vtd_set_quad(s, addr, val); 2856 } 2857 vtd_handle_iqt_write(s); 2858 break; 2859 2860 case DMAR_IQT_REG_HI: 2861 assert(size == 4); 2862 vtd_set_long(s, addr, val); 2863 /* 19:63 of IQT_REG is RsvdZ, do nothing here */ 2864 break; 2865 2866 /* Invalidation Queue Address Register, 64-bit */ 2867 case DMAR_IQA_REG: 2868 if (size == 4) { 2869 vtd_set_long(s, addr, val); 2870 } else { 2871 vtd_set_quad(s, addr, val); 2872 } 2873 if (s->ecap & VTD_ECAP_SMTS && 2874 val & VTD_IQA_DW_MASK) { 2875 s->iq_dw = true; 2876 } else { 2877 s->iq_dw = false; 2878 } 2879 break; 2880 2881 case DMAR_IQA_REG_HI: 2882 assert(size == 4); 2883 vtd_set_long(s, addr, val); 2884 break; 2885 2886 /* Invalidation Completion Status Register, 32-bit */ 2887 case DMAR_ICS_REG: 2888 assert(size == 4); 2889 vtd_set_long(s, addr, val); 2890 vtd_handle_ics_write(s); 2891 break; 2892 2893 /* Invalidation Event Control Register, 32-bit */ 2894 case DMAR_IECTL_REG: 2895 assert(size == 4); 2896 vtd_set_long(s, addr, val); 2897 vtd_handle_iectl_write(s); 2898 break; 2899 2900 /* Invalidation Event Data Register, 32-bit */ 2901 case DMAR_IEDATA_REG: 2902 assert(size == 4); 2903 vtd_set_long(s, addr, val); 2904 break; 2905 2906 /* Invalidation Event Address Register, 32-bit */ 2907 case DMAR_IEADDR_REG: 2908 assert(size == 4); 2909 vtd_set_long(s, addr, val); 2910 break; 2911 2912 /* Invalidation Event Upper Address Register, 32-bit */ 2913 case DMAR_IEUADDR_REG: 2914 assert(size == 4); 2915 vtd_set_long(s, addr, val); 2916 break; 2917 2918 /* Fault Recording Registers, 128-bit */ 2919 case DMAR_FRCD_REG_0_0: 2920 if (size == 4) { 2921 vtd_set_long(s, addr, val); 2922 } else { 2923 vtd_set_quad(s, addr, val); 2924 } 2925 break; 2926 2927 case DMAR_FRCD_REG_0_1: 2928 assert(size == 4); 2929 vtd_set_long(s, addr, val); 2930 break; 2931 2932 case DMAR_FRCD_REG_0_2: 2933 if (size == 4) { 2934 vtd_set_long(s, addr, val); 2935 } else { 2936 vtd_set_quad(s, addr, val); 2937 /* May clear bit 127 (Fault), update PPF */ 2938 vtd_update_fsts_ppf(s); 2939 } 2940 break; 2941 2942 case DMAR_FRCD_REG_0_3: 2943 assert(size == 4); 2944 vtd_set_long(s, addr, val); 2945 /* May clear bit 127 (Fault), update PPF */ 2946 vtd_update_fsts_ppf(s); 2947 break; 2948 2949 case DMAR_IRTA_REG: 2950 if (size == 4) { 2951 vtd_set_long(s, addr, val); 2952 } else { 2953 vtd_set_quad(s, addr, val); 2954 } 2955 break; 2956 2957 case DMAR_IRTA_REG_HI: 2958 assert(size == 4); 2959 vtd_set_long(s, addr, val); 2960 break; 2961 2962 default: 2963 if (size == 4) { 2964 vtd_set_long(s, addr, val); 2965 } else { 2966 vtd_set_quad(s, addr, val); 2967 } 2968 } 2969 } 2970 2971 static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr, 2972 IOMMUAccessFlags flag, int iommu_idx) 2973 { 2974 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); 2975 IntelIOMMUState *s = vtd_as->iommu_state; 2976 IOMMUTLBEntry iotlb = { 2977 /* We'll fill in the rest later. */ 2978 .target_as = &address_space_memory, 2979 }; 2980 bool success; 2981 2982 if (likely(s->dmar_enabled)) { 2983 success = vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, 2984 addr, flag & IOMMU_WO, &iotlb); 2985 } else { 2986 /* DMAR disabled, passthrough, use 4k-page*/ 2987 iotlb.iova = addr & VTD_PAGE_MASK_4K; 2988 iotlb.translated_addr = addr & VTD_PAGE_MASK_4K; 2989 iotlb.addr_mask = ~VTD_PAGE_MASK_4K; 2990 iotlb.perm = IOMMU_RW; 2991 success = true; 2992 } 2993 2994 if (likely(success)) { 2995 trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus), 2996 VTD_PCI_SLOT(vtd_as->devfn), 2997 VTD_PCI_FUNC(vtd_as->devfn), 2998 iotlb.iova, iotlb.translated_addr, 2999 iotlb.addr_mask); 3000 } else { 3001 error_report_once("%s: detected translation failure " 3002 "(dev=%02x:%02x:%02x, iova=0x%" PRIx64 ")", 3003 __func__, pci_bus_num(vtd_as->bus), 3004 VTD_PCI_SLOT(vtd_as->devfn), 3005 VTD_PCI_FUNC(vtd_as->devfn), 3006 addr); 3007 } 3008 3009 return iotlb; 3010 } 3011 3012 static int vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu, 3013 IOMMUNotifierFlag old, 3014 IOMMUNotifierFlag new, 3015 Error **errp) 3016 { 3017 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); 3018 IntelIOMMUState *s = vtd_as->iommu_state; 3019 3020 /* Update per-address-space notifier flags */ 3021 vtd_as->notifier_flags = new; 3022 3023 if (old == IOMMU_NOTIFIER_NONE) { 3024 QLIST_INSERT_HEAD(&s->vtd_as_with_notifiers, vtd_as, next); 3025 } else if (new == IOMMU_NOTIFIER_NONE) { 3026 QLIST_REMOVE(vtd_as, next); 3027 } 3028 return 0; 3029 } 3030 3031 static int vtd_post_load(void *opaque, int version_id) 3032 { 3033 IntelIOMMUState *iommu = opaque; 3034 3035 /* 3036 * Memory regions are dynamically turned on/off depending on 3037 * context entry configurations from the guest. After migration, 3038 * we need to make sure the memory regions are still correct. 3039 */ 3040 vtd_switch_address_space_all(iommu); 3041 3042 /* 3043 * We don't need to migrate the root_scalable because we can 3044 * simply do the calculation after the loading is complete. We 3045 * can actually do similar things with root, dmar_enabled, etc. 3046 * however since we've had them already so we'd better keep them 3047 * for compatibility of migration. 3048 */ 3049 vtd_update_scalable_state(iommu); 3050 3051 return 0; 3052 } 3053 3054 static const VMStateDescription vtd_vmstate = { 3055 .name = "iommu-intel", 3056 .version_id = 1, 3057 .minimum_version_id = 1, 3058 .priority = MIG_PRI_IOMMU, 3059 .post_load = vtd_post_load, 3060 .fields = (VMStateField[]) { 3061 VMSTATE_UINT64(root, IntelIOMMUState), 3062 VMSTATE_UINT64(intr_root, IntelIOMMUState), 3063 VMSTATE_UINT64(iq, IntelIOMMUState), 3064 VMSTATE_UINT32(intr_size, IntelIOMMUState), 3065 VMSTATE_UINT16(iq_head, IntelIOMMUState), 3066 VMSTATE_UINT16(iq_tail, IntelIOMMUState), 3067 VMSTATE_UINT16(iq_size, IntelIOMMUState), 3068 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState), 3069 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE), 3070 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState), 3071 VMSTATE_UNUSED(1), /* bool root_extended is obsolete by VT-d */ 3072 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState), 3073 VMSTATE_BOOL(qi_enabled, IntelIOMMUState), 3074 VMSTATE_BOOL(intr_enabled, IntelIOMMUState), 3075 VMSTATE_BOOL(intr_eime, IntelIOMMUState), 3076 VMSTATE_END_OF_LIST() 3077 } 3078 }; 3079 3080 static const MemoryRegionOps vtd_mem_ops = { 3081 .read = vtd_mem_read, 3082 .write = vtd_mem_write, 3083 .endianness = DEVICE_LITTLE_ENDIAN, 3084 .impl = { 3085 .min_access_size = 4, 3086 .max_access_size = 8, 3087 }, 3088 .valid = { 3089 .min_access_size = 4, 3090 .max_access_size = 8, 3091 }, 3092 }; 3093 3094 static Property vtd_properties[] = { 3095 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0), 3096 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim, 3097 ON_OFF_AUTO_AUTO), 3098 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), 3099 DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits, 3100 VTD_HOST_ADDRESS_WIDTH), 3101 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), 3102 DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE), 3103 DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), 3104 DEFINE_PROP_END_OF_LIST(), 3105 }; 3106 3107 /* Read IRTE entry with specific index */ 3108 static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index, 3109 VTD_IR_TableEntry *entry, uint16_t sid) 3110 { 3111 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \ 3112 {0xffff, 0xfffb, 0xfff9, 0xfff8}; 3113 dma_addr_t addr = 0x00; 3114 uint16_t mask, source_id; 3115 uint8_t bus, bus_max, bus_min; 3116 3117 if (index >= iommu->intr_size) { 3118 error_report_once("%s: index too large: ind=0x%x", 3119 __func__, index); 3120 return -VTD_FR_IR_INDEX_OVER; 3121 } 3122 3123 addr = iommu->intr_root + index * sizeof(*entry); 3124 if (dma_memory_read(&address_space_memory, addr, entry, 3125 sizeof(*entry))) { 3126 error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64, 3127 __func__, index, addr); 3128 return -VTD_FR_IR_ROOT_INVAL; 3129 } 3130 3131 trace_vtd_ir_irte_get(index, le64_to_cpu(entry->data[1]), 3132 le64_to_cpu(entry->data[0])); 3133 3134 if (!entry->irte.present) { 3135 error_report_once("%s: detected non-present IRTE " 3136 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")", 3137 __func__, index, le64_to_cpu(entry->data[1]), 3138 le64_to_cpu(entry->data[0])); 3139 return -VTD_FR_IR_ENTRY_P; 3140 } 3141 3142 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 || 3143 entry->irte.__reserved_2) { 3144 error_report_once("%s: detected non-zero reserved IRTE " 3145 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")", 3146 __func__, index, le64_to_cpu(entry->data[1]), 3147 le64_to_cpu(entry->data[0])); 3148 return -VTD_FR_IR_IRTE_RSVD; 3149 } 3150 3151 if (sid != X86_IOMMU_SID_INVALID) { 3152 /* Validate IRTE SID */ 3153 source_id = le32_to_cpu(entry->irte.source_id); 3154 switch (entry->irte.sid_vtype) { 3155 case VTD_SVT_NONE: 3156 break; 3157 3158 case VTD_SVT_ALL: 3159 mask = vtd_svt_mask[entry->irte.sid_q]; 3160 if ((source_id & mask) != (sid & mask)) { 3161 error_report_once("%s: invalid IRTE SID " 3162 "(index=%u, sid=%u, source_id=%u)", 3163 __func__, index, sid, source_id); 3164 return -VTD_FR_IR_SID_ERR; 3165 } 3166 break; 3167 3168 case VTD_SVT_BUS: 3169 bus_max = source_id >> 8; 3170 bus_min = source_id & 0xff; 3171 bus = sid >> 8; 3172 if (bus > bus_max || bus < bus_min) { 3173 error_report_once("%s: invalid SVT_BUS " 3174 "(index=%u, bus=%u, min=%u, max=%u)", 3175 __func__, index, bus, bus_min, bus_max); 3176 return -VTD_FR_IR_SID_ERR; 3177 } 3178 break; 3179 3180 default: 3181 error_report_once("%s: detected invalid IRTE SVT " 3182 "(index=%u, type=%d)", __func__, 3183 index, entry->irte.sid_vtype); 3184 /* Take this as verification failure. */ 3185 return -VTD_FR_IR_SID_ERR; 3186 } 3187 } 3188 3189 return 0; 3190 } 3191 3192 /* Fetch IRQ information of specific IR index */ 3193 static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index, 3194 X86IOMMUIrq *irq, uint16_t sid) 3195 { 3196 VTD_IR_TableEntry irte = {}; 3197 int ret = 0; 3198 3199 ret = vtd_irte_get(iommu, index, &irte, sid); 3200 if (ret) { 3201 return ret; 3202 } 3203 3204 irq->trigger_mode = irte.irte.trigger_mode; 3205 irq->vector = irte.irte.vector; 3206 irq->delivery_mode = irte.irte.delivery_mode; 3207 irq->dest = le32_to_cpu(irte.irte.dest_id); 3208 if (!iommu->intr_eime) { 3209 #define VTD_IR_APIC_DEST_MASK (0xff00ULL) 3210 #define VTD_IR_APIC_DEST_SHIFT (8) 3211 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >> 3212 VTD_IR_APIC_DEST_SHIFT; 3213 } 3214 irq->dest_mode = irte.irte.dest_mode; 3215 irq->redir_hint = irte.irte.redir_hint; 3216 3217 trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector, 3218 irq->delivery_mode, irq->dest, irq->dest_mode); 3219 3220 return 0; 3221 } 3222 3223 /* Interrupt remapping for MSI/MSI-X entry */ 3224 static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu, 3225 MSIMessage *origin, 3226 MSIMessage *translated, 3227 uint16_t sid) 3228 { 3229 int ret = 0; 3230 VTD_IR_MSIAddress addr; 3231 uint16_t index; 3232 X86IOMMUIrq irq = {}; 3233 3234 assert(origin && translated); 3235 3236 trace_vtd_ir_remap_msi_req(origin->address, origin->data); 3237 3238 if (!iommu || !iommu->intr_enabled) { 3239 memcpy(translated, origin, sizeof(*origin)); 3240 goto out; 3241 } 3242 3243 if (origin->address & VTD_MSI_ADDR_HI_MASK) { 3244 error_report_once("%s: MSI address high 32 bits non-zero detected: " 3245 "address=0x%" PRIx64, __func__, origin->address); 3246 return -VTD_FR_IR_REQ_RSVD; 3247 } 3248 3249 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK; 3250 if (addr.addr.__head != 0xfee) { 3251 error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32, 3252 __func__, addr.data); 3253 return -VTD_FR_IR_REQ_RSVD; 3254 } 3255 3256 /* This is compatible mode. */ 3257 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) { 3258 memcpy(translated, origin, sizeof(*origin)); 3259 goto out; 3260 } 3261 3262 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l); 3263 3264 #define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff) 3265 #define VTD_IR_MSI_DATA_RESERVED (0xffff0000) 3266 3267 if (addr.addr.sub_valid) { 3268 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */ 3269 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE; 3270 } 3271 3272 ret = vtd_remap_irq_get(iommu, index, &irq, sid); 3273 if (ret) { 3274 return ret; 3275 } 3276 3277 if (addr.addr.sub_valid) { 3278 trace_vtd_ir_remap_type("MSI"); 3279 if (origin->data & VTD_IR_MSI_DATA_RESERVED) { 3280 error_report_once("%s: invalid IR MSI " 3281 "(sid=%u, address=0x%" PRIx64 3282 ", data=0x%" PRIx32 ")", 3283 __func__, sid, origin->address, origin->data); 3284 return -VTD_FR_IR_REQ_RSVD; 3285 } 3286 } else { 3287 uint8_t vector = origin->data & 0xff; 3288 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; 3289 3290 trace_vtd_ir_remap_type("IOAPIC"); 3291 /* IOAPIC entry vector should be aligned with IRTE vector 3292 * (see vt-d spec 5.1.5.1). */ 3293 if (vector != irq.vector) { 3294 trace_vtd_warn_ir_vector(sid, index, vector, irq.vector); 3295 } 3296 3297 /* The Trigger Mode field must match the Trigger Mode in the IRTE. 3298 * (see vt-d spec 5.1.5.1). */ 3299 if (trigger_mode != irq.trigger_mode) { 3300 trace_vtd_warn_ir_trigger(sid, index, trigger_mode, 3301 irq.trigger_mode); 3302 } 3303 } 3304 3305 /* 3306 * We'd better keep the last two bits, assuming that guest OS 3307 * might modify it. Keep it does not hurt after all. 3308 */ 3309 irq.msi_addr_last_bits = addr.addr.__not_care; 3310 3311 /* Translate X86IOMMUIrq to MSI message */ 3312 x86_iommu_irq_to_msi_message(&irq, translated); 3313 3314 out: 3315 trace_vtd_ir_remap_msi(origin->address, origin->data, 3316 translated->address, translated->data); 3317 return 0; 3318 } 3319 3320 static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src, 3321 MSIMessage *dst, uint16_t sid) 3322 { 3323 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu), 3324 src, dst, sid); 3325 } 3326 3327 static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr, 3328 uint64_t *data, unsigned size, 3329 MemTxAttrs attrs) 3330 { 3331 return MEMTX_OK; 3332 } 3333 3334 static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr, 3335 uint64_t value, unsigned size, 3336 MemTxAttrs attrs) 3337 { 3338 int ret = 0; 3339 MSIMessage from = {}, to = {}; 3340 uint16_t sid = X86_IOMMU_SID_INVALID; 3341 3342 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST; 3343 from.data = (uint32_t) value; 3344 3345 if (!attrs.unspecified) { 3346 /* We have explicit Source ID */ 3347 sid = attrs.requester_id; 3348 } 3349 3350 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid); 3351 if (ret) { 3352 /* TODO: report error */ 3353 /* Drop this interrupt */ 3354 return MEMTX_ERROR; 3355 } 3356 3357 apic_get_class()->send_msi(&to); 3358 3359 return MEMTX_OK; 3360 } 3361 3362 static const MemoryRegionOps vtd_mem_ir_ops = { 3363 .read_with_attrs = vtd_mem_ir_read, 3364 .write_with_attrs = vtd_mem_ir_write, 3365 .endianness = DEVICE_LITTLE_ENDIAN, 3366 .impl = { 3367 .min_access_size = 4, 3368 .max_access_size = 4, 3369 }, 3370 .valid = { 3371 .min_access_size = 4, 3372 .max_access_size = 4, 3373 }, 3374 }; 3375 3376 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn) 3377 { 3378 uintptr_t key = (uintptr_t)bus; 3379 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key); 3380 VTDAddressSpace *vtd_dev_as; 3381 char name[128]; 3382 3383 if (!vtd_bus) { 3384 uintptr_t *new_key = g_malloc(sizeof(*new_key)); 3385 *new_key = (uintptr_t)bus; 3386 /* No corresponding free() */ 3387 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \ 3388 PCI_DEVFN_MAX); 3389 vtd_bus->bus = bus; 3390 g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus); 3391 } 3392 3393 vtd_dev_as = vtd_bus->dev_as[devfn]; 3394 3395 if (!vtd_dev_as) { 3396 snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn), 3397 PCI_FUNC(devfn)); 3398 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace)); 3399 3400 vtd_dev_as->bus = bus; 3401 vtd_dev_as->devfn = (uint8_t)devfn; 3402 vtd_dev_as->iommu_state = s; 3403 vtd_dev_as->context_cache_entry.context_cache_gen = 0; 3404 vtd_dev_as->iova_tree = iova_tree_new(); 3405 3406 memory_region_init(&vtd_dev_as->root, OBJECT(s), name, UINT64_MAX); 3407 address_space_init(&vtd_dev_as->as, &vtd_dev_as->root, "vtd-root"); 3408 3409 /* 3410 * Build the DMAR-disabled container with aliases to the 3411 * shared MRs. Note that aliasing to a shared memory region 3412 * could help the memory API to detect same FlatViews so we 3413 * can have devices to share the same FlatView when DMAR is 3414 * disabled (either by not providing "intel_iommu=on" or with 3415 * "iommu=pt"). It will greatly reduce the total number of 3416 * FlatViews of the system hence VM runs faster. 3417 */ 3418 memory_region_init_alias(&vtd_dev_as->nodmar, OBJECT(s), 3419 "vtd-nodmar", &s->mr_nodmar, 0, 3420 memory_region_size(&s->mr_nodmar)); 3421 3422 /* 3423 * Build the per-device DMAR-enabled container. 3424 * 3425 * TODO: currently we have per-device IOMMU memory region only 3426 * because we have per-device IOMMU notifiers for devices. If 3427 * one day we can abstract the IOMMU notifiers out of the 3428 * memory regions then we can also share the same memory 3429 * region here just like what we've done above with the nodmar 3430 * region. 3431 */ 3432 strcat(name, "-dmar"); 3433 memory_region_init_iommu(&vtd_dev_as->iommu, sizeof(vtd_dev_as->iommu), 3434 TYPE_INTEL_IOMMU_MEMORY_REGION, OBJECT(s), 3435 name, UINT64_MAX); 3436 memory_region_init_alias(&vtd_dev_as->iommu_ir, OBJECT(s), "vtd-ir", 3437 &s->mr_ir, 0, memory_region_size(&s->mr_ir)); 3438 memory_region_add_subregion_overlap(MEMORY_REGION(&vtd_dev_as->iommu), 3439 VTD_INTERRUPT_ADDR_FIRST, 3440 &vtd_dev_as->iommu_ir, 1); 3441 3442 /* 3443 * Hook both the containers under the root container, we 3444 * switch between DMAR & noDMAR by enable/disable 3445 * corresponding sub-containers 3446 */ 3447 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0, 3448 MEMORY_REGION(&vtd_dev_as->iommu), 3449 0); 3450 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0, 3451 &vtd_dev_as->nodmar, 0); 3452 3453 vtd_switch_address_space(vtd_dev_as); 3454 } 3455 return vtd_dev_as; 3456 } 3457 3458 /* Unmap the whole range in the notifier's scope. */ 3459 static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n) 3460 { 3461 hwaddr size, remain; 3462 hwaddr start = n->start; 3463 hwaddr end = n->end; 3464 IntelIOMMUState *s = as->iommu_state; 3465 DMAMap map; 3466 3467 /* 3468 * Note: all the codes in this function has a assumption that IOVA 3469 * bits are no more than VTD_MGAW bits (which is restricted by 3470 * VT-d spec), otherwise we need to consider overflow of 64 bits. 3471 */ 3472 3473 if (end > VTD_ADDRESS_SIZE(s->aw_bits) - 1) { 3474 /* 3475 * Don't need to unmap regions that is bigger than the whole 3476 * VT-d supported address space size 3477 */ 3478 end = VTD_ADDRESS_SIZE(s->aw_bits) - 1; 3479 } 3480 3481 assert(start <= end); 3482 size = remain = end - start + 1; 3483 3484 while (remain >= VTD_PAGE_SIZE) { 3485 IOMMUTLBEvent event; 3486 uint64_t mask = dma_aligned_pow2_mask(start, end, s->aw_bits); 3487 uint64_t size = mask + 1; 3488 3489 assert(size); 3490 3491 event.type = IOMMU_NOTIFIER_UNMAP; 3492 event.entry.iova = start; 3493 event.entry.addr_mask = mask; 3494 event.entry.target_as = &address_space_memory; 3495 event.entry.perm = IOMMU_NONE; 3496 /* This field is meaningless for unmap */ 3497 event.entry.translated_addr = 0; 3498 3499 memory_region_notify_iommu_one(n, &event); 3500 3501 start += size; 3502 remain -= size; 3503 } 3504 3505 assert(!remain); 3506 3507 trace_vtd_as_unmap_whole(pci_bus_num(as->bus), 3508 VTD_PCI_SLOT(as->devfn), 3509 VTD_PCI_FUNC(as->devfn), 3510 n->start, size); 3511 3512 map.iova = n->start; 3513 map.size = size; 3514 iova_tree_remove(as->iova_tree, &map); 3515 } 3516 3517 static void vtd_address_space_unmap_all(IntelIOMMUState *s) 3518 { 3519 VTDAddressSpace *vtd_as; 3520 IOMMUNotifier *n; 3521 3522 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { 3523 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) { 3524 vtd_address_space_unmap(vtd_as, n); 3525 } 3526 } 3527 } 3528 3529 static void vtd_address_space_refresh_all(IntelIOMMUState *s) 3530 { 3531 vtd_address_space_unmap_all(s); 3532 vtd_switch_address_space_all(s); 3533 } 3534 3535 static int vtd_replay_hook(IOMMUTLBEvent *event, void *private) 3536 { 3537 memory_region_notify_iommu_one(private, event); 3538 return 0; 3539 } 3540 3541 static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) 3542 { 3543 VTDAddressSpace *vtd_as = container_of(iommu_mr, VTDAddressSpace, iommu); 3544 IntelIOMMUState *s = vtd_as->iommu_state; 3545 uint8_t bus_n = pci_bus_num(vtd_as->bus); 3546 VTDContextEntry ce; 3547 3548 /* 3549 * The replay can be triggered by either a invalidation or a newly 3550 * created entry. No matter what, we release existing mappings 3551 * (it means flushing caches for UNMAP-only registers). 3552 */ 3553 vtd_address_space_unmap(vtd_as, n); 3554 3555 if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) { 3556 trace_vtd_replay_ce_valid(s->root_scalable ? "scalable mode" : 3557 "legacy mode", 3558 bus_n, PCI_SLOT(vtd_as->devfn), 3559 PCI_FUNC(vtd_as->devfn), 3560 vtd_get_domain_id(s, &ce), 3561 ce.hi, ce.lo); 3562 if (vtd_as_has_map_notifier(vtd_as)) { 3563 /* This is required only for MAP typed notifiers */ 3564 vtd_page_walk_info info = { 3565 .hook_fn = vtd_replay_hook, 3566 .private = (void *)n, 3567 .notify_unmap = false, 3568 .aw = s->aw_bits, 3569 .as = vtd_as, 3570 .domain_id = vtd_get_domain_id(s, &ce), 3571 }; 3572 3573 vtd_page_walk(s, &ce, 0, ~0ULL, &info); 3574 } 3575 } else { 3576 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn), 3577 PCI_FUNC(vtd_as->devfn)); 3578 } 3579 3580 return; 3581 } 3582 3583 /* Do the initialization. It will also be called when reset, so pay 3584 * attention when adding new initialization stuff. 3585 */ 3586 static void vtd_init(IntelIOMMUState *s) 3587 { 3588 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 3589 3590 memset(s->csr, 0, DMAR_REG_SIZE); 3591 memset(s->wmask, 0, DMAR_REG_SIZE); 3592 memset(s->w1cmask, 0, DMAR_REG_SIZE); 3593 memset(s->womask, 0, DMAR_REG_SIZE); 3594 3595 s->root = 0; 3596 s->root_scalable = false; 3597 s->dmar_enabled = false; 3598 s->intr_enabled = false; 3599 s->iq_head = 0; 3600 s->iq_tail = 0; 3601 s->iq = 0; 3602 s->iq_size = 0; 3603 s->qi_enabled = false; 3604 s->iq_last_desc_type = VTD_INV_DESC_NONE; 3605 s->iq_dw = false; 3606 s->next_frcd_reg = 0; 3607 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | 3608 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | 3609 VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(s->aw_bits); 3610 if (s->dma_drain) { 3611 s->cap |= VTD_CAP_DRAIN; 3612 } 3613 if (s->aw_bits == VTD_HOST_AW_48BIT) { 3614 s->cap |= VTD_CAP_SAGAW_48bit; 3615 } 3616 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; 3617 3618 /* 3619 * Rsvd field masks for spte 3620 */ 3621 vtd_spte_rsvd[0] = ~0ULL; 3622 vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, 3623 x86_iommu->dt_supported); 3624 vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); 3625 vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); 3626 vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); 3627 3628 vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, 3629 x86_iommu->dt_supported); 3630 vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, 3631 x86_iommu->dt_supported); 3632 3633 if (x86_iommu_ir_supported(x86_iommu)) { 3634 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV; 3635 if (s->intr_eim == ON_OFF_AUTO_ON) { 3636 s->ecap |= VTD_ECAP_EIM; 3637 } 3638 assert(s->intr_eim != ON_OFF_AUTO_AUTO); 3639 } 3640 3641 if (x86_iommu->dt_supported) { 3642 s->ecap |= VTD_ECAP_DT; 3643 } 3644 3645 if (x86_iommu->pt_supported) { 3646 s->ecap |= VTD_ECAP_PT; 3647 } 3648 3649 if (s->caching_mode) { 3650 s->cap |= VTD_CAP_CM; 3651 } 3652 3653 /* TODO: read cap/ecap from host to decide which cap to be exposed. */ 3654 if (s->scalable_mode) { 3655 s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS; 3656 } 3657 3658 vtd_reset_caches(s); 3659 3660 /* Define registers with default values and bit semantics */ 3661 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0); 3662 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0); 3663 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0); 3664 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0); 3665 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL); 3666 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0); 3667 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffffc00ULL, 0); 3668 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0); 3669 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL); 3670 3671 /* Advanced Fault Logging not supported */ 3672 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL); 3673 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0); 3674 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0); 3675 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0); 3676 3677 /* Treated as RsvdZ when EIM in ECAP_REG is not supported 3678 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0); 3679 */ 3680 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0); 3681 3682 /* Treated as RO for implementations that PLMR and PHMR fields reported 3683 * as Clear in the CAP_REG. 3684 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0); 3685 */ 3686 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0); 3687 3688 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0); 3689 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0); 3690 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff807ULL, 0); 3691 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL); 3692 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0); 3693 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0); 3694 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0); 3695 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */ 3696 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0); 3697 3698 /* IOTLB registers */ 3699 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0); 3700 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0); 3701 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL); 3702 3703 /* Fault Recording Registers, 128-bit */ 3704 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0); 3705 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL); 3706 3707 /* 3708 * Interrupt remapping registers. 3709 */ 3710 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0); 3711 } 3712 3713 /* Should not reset address_spaces when reset because devices will still use 3714 * the address space they got at first (won't ask the bus again). 3715 */ 3716 static void vtd_reset(DeviceState *dev) 3717 { 3718 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev); 3719 3720 vtd_init(s); 3721 vtd_address_space_refresh_all(s); 3722 } 3723 3724 static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) 3725 { 3726 IntelIOMMUState *s = opaque; 3727 VTDAddressSpace *vtd_as; 3728 3729 assert(0 <= devfn && devfn < PCI_DEVFN_MAX); 3730 3731 vtd_as = vtd_find_add_as(s, bus, devfn); 3732 return &vtd_as->as; 3733 } 3734 3735 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) 3736 { 3737 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 3738 3739 if (s->intr_eim == ON_OFF_AUTO_ON && !x86_iommu_ir_supported(x86_iommu)) { 3740 error_setg(errp, "eim=on cannot be selected without intremap=on"); 3741 return false; 3742 } 3743 3744 if (s->intr_eim == ON_OFF_AUTO_AUTO) { 3745 s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim) 3746 && x86_iommu_ir_supported(x86_iommu) ? 3747 ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 3748 } 3749 if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) { 3750 if (!kvm_irqchip_in_kernel()) { 3751 error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split"); 3752 return false; 3753 } 3754 if (!kvm_enable_x2apic()) { 3755 error_setg(errp, "eim=on requires support on the KVM side" 3756 "(X2APIC_API, first shipped in v4.7)"); 3757 return false; 3758 } 3759 } 3760 3761 /* Currently only address widths supported are 39 and 48 bits */ 3762 if ((s->aw_bits != VTD_HOST_AW_39BIT) && 3763 (s->aw_bits != VTD_HOST_AW_48BIT)) { 3764 error_setg(errp, "Supported values for aw-bits are: %d, %d", 3765 VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT); 3766 return false; 3767 } 3768 3769 if (s->scalable_mode && !s->dma_drain) { 3770 error_setg(errp, "Need to set dma_drain for scalable mode"); 3771 return false; 3772 } 3773 3774 return true; 3775 } 3776 3777 static int vtd_machine_done_notify_one(Object *child, void *unused) 3778 { 3779 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 3780 3781 /* 3782 * We hard-coded here because vfio-pci is the only special case 3783 * here. Let's be more elegant in the future when we can, but so 3784 * far there seems to be no better way. 3785 */ 3786 if (object_dynamic_cast(child, "vfio-pci") && !iommu->caching_mode) { 3787 vtd_panic_require_caching_mode(); 3788 } 3789 3790 return 0; 3791 } 3792 3793 static void vtd_machine_done_hook(Notifier *notifier, void *unused) 3794 { 3795 object_child_foreach_recursive(object_get_root(), 3796 vtd_machine_done_notify_one, NULL); 3797 } 3798 3799 static Notifier vtd_machine_done_notify = { 3800 .notify = vtd_machine_done_hook, 3801 }; 3802 3803 static void vtd_realize(DeviceState *dev, Error **errp) 3804 { 3805 MachineState *ms = MACHINE(qdev_get_machine()); 3806 PCMachineState *pcms = PC_MACHINE(ms); 3807 X86MachineState *x86ms = X86_MACHINE(ms); 3808 PCIBus *bus = pcms->bus; 3809 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev); 3810 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev); 3811 3812 x86_iommu->type = TYPE_INTEL; 3813 3814 if (!vtd_decide_config(s, errp)) { 3815 return; 3816 } 3817 3818 QLIST_INIT(&s->vtd_as_with_notifiers); 3819 qemu_mutex_init(&s->iommu_lock); 3820 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num)); 3821 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s, 3822 "intel_iommu", DMAR_REG_SIZE); 3823 3824 /* Create the shared memory regions by all devices */ 3825 memory_region_init(&s->mr_nodmar, OBJECT(s), "vtd-nodmar", 3826 UINT64_MAX); 3827 memory_region_init_io(&s->mr_ir, OBJECT(s), &vtd_mem_ir_ops, 3828 s, "vtd-ir", VTD_INTERRUPT_ADDR_SIZE); 3829 memory_region_init_alias(&s->mr_sys_alias, OBJECT(s), 3830 "vtd-sys-alias", get_system_memory(), 0, 3831 memory_region_size(get_system_memory())); 3832 memory_region_add_subregion_overlap(&s->mr_nodmar, 0, 3833 &s->mr_sys_alias, 0); 3834 memory_region_add_subregion_overlap(&s->mr_nodmar, 3835 VTD_INTERRUPT_ADDR_FIRST, 3836 &s->mr_ir, 1); 3837 3838 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem); 3839 /* No corresponding destroy */ 3840 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal, 3841 g_free, g_free); 3842 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal, 3843 g_free, g_free); 3844 vtd_init(s); 3845 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); 3846 pci_setup_iommu(bus, vtd_host_dma_iommu, dev); 3847 /* Pseudo address space under root PCI bus. */ 3848 x86ms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC); 3849 qemu_add_machine_init_done_notifier(&vtd_machine_done_notify); 3850 } 3851 3852 static void vtd_class_init(ObjectClass *klass, void *data) 3853 { 3854 DeviceClass *dc = DEVICE_CLASS(klass); 3855 X86IOMMUClass *x86_class = X86_IOMMU_DEVICE_CLASS(klass); 3856 3857 dc->reset = vtd_reset; 3858 dc->vmsd = &vtd_vmstate; 3859 device_class_set_props(dc, vtd_properties); 3860 dc->hotpluggable = false; 3861 x86_class->realize = vtd_realize; 3862 x86_class->int_remap = vtd_int_remap; 3863 /* Supported by the pc-q35-* machine types */ 3864 dc->user_creatable = true; 3865 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 3866 dc->desc = "Intel IOMMU (VT-d) DMA Remapping device"; 3867 } 3868 3869 static const TypeInfo vtd_info = { 3870 .name = TYPE_INTEL_IOMMU_DEVICE, 3871 .parent = TYPE_X86_IOMMU_DEVICE, 3872 .instance_size = sizeof(IntelIOMMUState), 3873 .class_init = vtd_class_init, 3874 }; 3875 3876 static void vtd_iommu_memory_region_class_init(ObjectClass *klass, 3877 void *data) 3878 { 3879 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 3880 3881 imrc->translate = vtd_iommu_translate; 3882 imrc->notify_flag_changed = vtd_iommu_notify_flag_changed; 3883 imrc->replay = vtd_iommu_replay; 3884 } 3885 3886 static const TypeInfo vtd_iommu_memory_region_info = { 3887 .parent = TYPE_IOMMU_MEMORY_REGION, 3888 .name = TYPE_INTEL_IOMMU_MEMORY_REGION, 3889 .class_init = vtd_iommu_memory_region_class_init, 3890 }; 3891 3892 static void vtd_register_types(void) 3893 { 3894 type_register_static(&vtd_info); 3895 type_register_static(&vtd_iommu_memory_region_info); 3896 } 3897 3898 type_init(vtd_register_types) 3899