1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/irq.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 #include "qom/object.h" 18 #include "trace.h" 19 20 static const uint8_t pl061_id[12] = 21 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 22 static const uint8_t pl061_id_luminary[12] = 23 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 24 25 #define TYPE_PL061 "pl061" 26 OBJECT_DECLARE_SIMPLE_TYPE(PL061State, PL061) 27 28 #define N_GPIOS 8 29 30 struct PL061State { 31 SysBusDevice parent_obj; 32 33 MemoryRegion iomem; 34 uint32_t locked; 35 uint32_t data; 36 uint32_t old_out_data; 37 uint32_t old_in_data; 38 uint32_t dir; 39 uint32_t isense; 40 uint32_t ibe; 41 uint32_t iev; 42 uint32_t im; 43 uint32_t istate; 44 uint32_t afsel; 45 uint32_t dr2r; 46 uint32_t dr4r; 47 uint32_t dr8r; 48 uint32_t odr; 49 uint32_t pur; 50 uint32_t pdr; 51 uint32_t slr; 52 uint32_t den; 53 uint32_t cr; 54 uint32_t amsel; 55 qemu_irq irq; 56 qemu_irq out[N_GPIOS]; 57 const unsigned char *id; 58 }; 59 60 static const VMStateDescription vmstate_pl061 = { 61 .name = "pl061", 62 .version_id = 4, 63 .minimum_version_id = 4, 64 .fields = (VMStateField[]) { 65 VMSTATE_UINT32(locked, PL061State), 66 VMSTATE_UINT32(data, PL061State), 67 VMSTATE_UINT32(old_out_data, PL061State), 68 VMSTATE_UINT32(old_in_data, PL061State), 69 VMSTATE_UINT32(dir, PL061State), 70 VMSTATE_UINT32(isense, PL061State), 71 VMSTATE_UINT32(ibe, PL061State), 72 VMSTATE_UINT32(iev, PL061State), 73 VMSTATE_UINT32(im, PL061State), 74 VMSTATE_UINT32(istate, PL061State), 75 VMSTATE_UINT32(afsel, PL061State), 76 VMSTATE_UINT32(dr2r, PL061State), 77 VMSTATE_UINT32(dr4r, PL061State), 78 VMSTATE_UINT32(dr8r, PL061State), 79 VMSTATE_UINT32(odr, PL061State), 80 VMSTATE_UINT32(pur, PL061State), 81 VMSTATE_UINT32(pdr, PL061State), 82 VMSTATE_UINT32(slr, PL061State), 83 VMSTATE_UINT32(den, PL061State), 84 VMSTATE_UINT32(cr, PL061State), 85 VMSTATE_UINT32_V(amsel, PL061State, 2), 86 VMSTATE_END_OF_LIST() 87 } 88 }; 89 90 static void pl061_update(PL061State *s) 91 { 92 uint8_t changed; 93 uint8_t mask; 94 uint8_t out; 95 int i; 96 97 trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data); 98 99 /* Outputs float high. */ 100 /* FIXME: This is board dependent. */ 101 out = (s->data & s->dir) | ~s->dir; 102 changed = s->old_out_data ^ out; 103 if (changed) { 104 s->old_out_data = out; 105 for (i = 0; i < N_GPIOS; i++) { 106 mask = 1 << i; 107 if (changed & mask) { 108 int level = (out & mask) != 0; 109 trace_pl061_set_output(DEVICE(s)->canonical_path, i, level); 110 qemu_set_irq(s->out[i], level); 111 } 112 } 113 } 114 115 /* Inputs */ 116 changed = (s->old_in_data ^ s->data) & ~s->dir; 117 if (changed) { 118 s->old_in_data = s->data; 119 for (i = 0; i < N_GPIOS; i++) { 120 mask = 1 << i; 121 if (changed & mask) { 122 trace_pl061_input_change(DEVICE(s)->canonical_path, i, 123 (s->data & mask) != 0); 124 125 if (!(s->isense & mask)) { 126 /* Edge interrupt */ 127 if (s->ibe & mask) { 128 /* Any edge triggers the interrupt */ 129 s->istate |= mask; 130 } else { 131 /* Edge is selected by IEV */ 132 s->istate |= ~(s->data ^ s->iev) & mask; 133 } 134 } 135 } 136 } 137 } 138 139 /* Level interrupt */ 140 s->istate |= ~(s->data ^ s->iev) & s->isense; 141 142 trace_pl061_update_istate(DEVICE(s)->canonical_path, 143 s->istate, s->im, (s->istate & s->im) != 0); 144 145 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 146 } 147 148 static uint64_t pl061_read(void *opaque, hwaddr offset, 149 unsigned size) 150 { 151 PL061State *s = (PL061State *)opaque; 152 uint64_t r = 0; 153 154 switch (offset) { 155 case 0x0 ... 0x3ff: /* Data */ 156 r = s->data & (offset >> 2); 157 break; 158 case 0x400: /* Direction */ 159 r = s->dir; 160 break; 161 case 0x404: /* Interrupt sense */ 162 r = s->isense; 163 break; 164 case 0x408: /* Interrupt both edges */ 165 r = s->ibe; 166 break; 167 case 0x40c: /* Interrupt event */ 168 r = s->iev; 169 break; 170 case 0x410: /* Interrupt mask */ 171 r = s->im; 172 break; 173 case 0x414: /* Raw interrupt status */ 174 r = s->istate; 175 break; 176 case 0x418: /* Masked interrupt status */ 177 r = s->istate & s->im; 178 break; 179 case 0x420: /* Alternate function select */ 180 r = s->afsel; 181 break; 182 case 0x500: /* 2mA drive */ 183 if (s->id != pl061_id_luminary) { 184 goto bad_offset; 185 } 186 r = s->dr2r; 187 break; 188 case 0x504: /* 4mA drive */ 189 if (s->id != pl061_id_luminary) { 190 goto bad_offset; 191 } 192 r = s->dr4r; 193 break; 194 case 0x508: /* 8mA drive */ 195 if (s->id != pl061_id_luminary) { 196 goto bad_offset; 197 } 198 r = s->dr8r; 199 break; 200 case 0x50c: /* Open drain */ 201 if (s->id != pl061_id_luminary) { 202 goto bad_offset; 203 } 204 r = s->odr; 205 break; 206 case 0x510: /* Pull-up */ 207 if (s->id != pl061_id_luminary) { 208 goto bad_offset; 209 } 210 r = s->pur; 211 break; 212 case 0x514: /* Pull-down */ 213 if (s->id != pl061_id_luminary) { 214 goto bad_offset; 215 } 216 r = s->pdr; 217 break; 218 case 0x518: /* Slew rate control */ 219 if (s->id != pl061_id_luminary) { 220 goto bad_offset; 221 } 222 r = s->slr; 223 break; 224 case 0x51c: /* Digital enable */ 225 if (s->id != pl061_id_luminary) { 226 goto bad_offset; 227 } 228 r = s->den; 229 break; 230 case 0x520: /* Lock */ 231 if (s->id != pl061_id_luminary) { 232 goto bad_offset; 233 } 234 r = s->locked; 235 break; 236 case 0x524: /* Commit */ 237 if (s->id != pl061_id_luminary) { 238 goto bad_offset; 239 } 240 r = s->cr; 241 break; 242 case 0x528: /* Analog mode select */ 243 if (s->id != pl061_id_luminary) { 244 goto bad_offset; 245 } 246 r = s->amsel; 247 break; 248 case 0xfd0 ... 0xfff: /* ID registers */ 249 r = s->id[(offset - 0xfd0) >> 2]; 250 break; 251 default: 252 bad_offset: 253 qemu_log_mask(LOG_GUEST_ERROR, 254 "pl061_read: Bad offset %x\n", (int)offset); 255 break; 256 } 257 258 trace_pl061_read(DEVICE(s)->canonical_path, offset, r); 259 return r; 260 } 261 262 static void pl061_write(void *opaque, hwaddr offset, 263 uint64_t value, unsigned size) 264 { 265 PL061State *s = (PL061State *)opaque; 266 uint8_t mask; 267 268 trace_pl061_write(DEVICE(s)->canonical_path, offset, value); 269 270 switch (offset) { 271 case 0 ... 0x3ff: 272 mask = (offset >> 2) & s->dir; 273 s->data = (s->data & ~mask) | (value & mask); 274 pl061_update(s); 275 return; 276 case 0x400: /* Direction */ 277 s->dir = value & 0xff; 278 break; 279 case 0x404: /* Interrupt sense */ 280 s->isense = value & 0xff; 281 break; 282 case 0x408: /* Interrupt both edges */ 283 s->ibe = value & 0xff; 284 break; 285 case 0x40c: /* Interrupt event */ 286 s->iev = value & 0xff; 287 break; 288 case 0x410: /* Interrupt mask */ 289 s->im = value & 0xff; 290 break; 291 case 0x41c: /* Interrupt clear */ 292 s->istate &= ~value; 293 break; 294 case 0x420: /* Alternate function select */ 295 mask = s->cr; 296 s->afsel = (s->afsel & ~mask) | (value & mask); 297 break; 298 case 0x500: /* 2mA drive */ 299 if (s->id != pl061_id_luminary) { 300 goto bad_offset; 301 } 302 s->dr2r = value & 0xff; 303 break; 304 case 0x504: /* 4mA drive */ 305 if (s->id != pl061_id_luminary) { 306 goto bad_offset; 307 } 308 s->dr4r = value & 0xff; 309 break; 310 case 0x508: /* 8mA drive */ 311 if (s->id != pl061_id_luminary) { 312 goto bad_offset; 313 } 314 s->dr8r = value & 0xff; 315 break; 316 case 0x50c: /* Open drain */ 317 if (s->id != pl061_id_luminary) { 318 goto bad_offset; 319 } 320 s->odr = value & 0xff; 321 break; 322 case 0x510: /* Pull-up */ 323 if (s->id != pl061_id_luminary) { 324 goto bad_offset; 325 } 326 s->pur = value & 0xff; 327 break; 328 case 0x514: /* Pull-down */ 329 if (s->id != pl061_id_luminary) { 330 goto bad_offset; 331 } 332 s->pdr = value & 0xff; 333 break; 334 case 0x518: /* Slew rate control */ 335 if (s->id != pl061_id_luminary) { 336 goto bad_offset; 337 } 338 s->slr = value & 0xff; 339 break; 340 case 0x51c: /* Digital enable */ 341 if (s->id != pl061_id_luminary) { 342 goto bad_offset; 343 } 344 s->den = value & 0xff; 345 break; 346 case 0x520: /* Lock */ 347 if (s->id != pl061_id_luminary) { 348 goto bad_offset; 349 } 350 s->locked = (value != 0xacce551); 351 break; 352 case 0x524: /* Commit */ 353 if (s->id != pl061_id_luminary) { 354 goto bad_offset; 355 } 356 if (!s->locked) 357 s->cr = value & 0xff; 358 break; 359 case 0x528: 360 if (s->id != pl061_id_luminary) { 361 goto bad_offset; 362 } 363 s->amsel = value & 0xff; 364 break; 365 default: 366 bad_offset: 367 qemu_log_mask(LOG_GUEST_ERROR, 368 "pl061_write: Bad offset %x\n", (int)offset); 369 return; 370 } 371 pl061_update(s); 372 return; 373 } 374 375 static void pl061_reset(DeviceState *dev) 376 { 377 PL061State *s = PL061(dev); 378 379 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 380 s->data = 0; 381 s->old_out_data = 0; 382 s->old_in_data = 0; 383 s->dir = 0; 384 s->isense = 0; 385 s->ibe = 0; 386 s->iev = 0; 387 s->im = 0; 388 s->istate = 0; 389 s->afsel = 0; 390 s->dr2r = 0xff; 391 s->dr4r = 0; 392 s->dr8r = 0; 393 s->odr = 0; 394 s->pur = 0; 395 s->pdr = 0; 396 s->slr = 0; 397 s->den = 0; 398 s->locked = 1; 399 s->cr = 0xff; 400 s->amsel = 0; 401 } 402 403 static void pl061_set_irq(void * opaque, int irq, int level) 404 { 405 PL061State *s = (PL061State *)opaque; 406 uint8_t mask; 407 408 mask = 1 << irq; 409 if ((s->dir & mask) == 0) { 410 s->data &= ~mask; 411 if (level) 412 s->data |= mask; 413 pl061_update(s); 414 } 415 } 416 417 static const MemoryRegionOps pl061_ops = { 418 .read = pl061_read, 419 .write = pl061_write, 420 .endianness = DEVICE_NATIVE_ENDIAN, 421 }; 422 423 static void pl061_luminary_init(Object *obj) 424 { 425 PL061State *s = PL061(obj); 426 427 s->id = pl061_id_luminary; 428 } 429 430 static void pl061_init(Object *obj) 431 { 432 PL061State *s = PL061(obj); 433 DeviceState *dev = DEVICE(obj); 434 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 435 436 s->id = pl061_id; 437 438 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); 439 sysbus_init_mmio(sbd, &s->iomem); 440 sysbus_init_irq(sbd, &s->irq); 441 qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS); 442 qdev_init_gpio_out(dev, s->out, N_GPIOS); 443 } 444 445 static void pl061_class_init(ObjectClass *klass, void *data) 446 { 447 DeviceClass *dc = DEVICE_CLASS(klass); 448 449 dc->vmsd = &vmstate_pl061; 450 dc->reset = &pl061_reset; 451 } 452 453 static const TypeInfo pl061_info = { 454 .name = TYPE_PL061, 455 .parent = TYPE_SYS_BUS_DEVICE, 456 .instance_size = sizeof(PL061State), 457 .instance_init = pl061_init, 458 .class_init = pl061_class_init, 459 }; 460 461 static const TypeInfo pl061_luminary_info = { 462 .name = "pl061_luminary", 463 .parent = TYPE_PL061, 464 .instance_init = pl061_luminary_init, 465 }; 466 467 static void pl061_register_types(void) 468 { 469 type_register_static(&pl061_info); 470 type_register_static(&pl061_luminary_info); 471 } 472 473 type_init(pl061_register_types) 474