1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 * 10 * QEMU interface: 11 * + sysbus MMIO region 0: the device registers 12 * + sysbus IRQ: the GPIOINTR interrupt line 13 * + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines 14 * + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as 15 * outputs 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/irq.h" 20 #include "hw/sysbus.h" 21 #include "migration/vmstate.h" 22 #include "qemu/log.h" 23 #include "qemu/module.h" 24 #include "qom/object.h" 25 #include "trace.h" 26 27 static const uint8_t pl061_id[12] = 28 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 29 static const uint8_t pl061_id_luminary[12] = 30 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 31 32 #define TYPE_PL061 "pl061" 33 OBJECT_DECLARE_SIMPLE_TYPE(PL061State, PL061) 34 35 #define N_GPIOS 8 36 37 struct PL061State { 38 SysBusDevice parent_obj; 39 40 MemoryRegion iomem; 41 uint32_t locked; 42 uint32_t data; 43 uint32_t old_out_data; 44 uint32_t old_in_data; 45 uint32_t dir; 46 uint32_t isense; 47 uint32_t ibe; 48 uint32_t iev; 49 uint32_t im; 50 uint32_t istate; 51 uint32_t afsel; 52 uint32_t dr2r; 53 uint32_t dr4r; 54 uint32_t dr8r; 55 uint32_t odr; 56 uint32_t pur; 57 uint32_t pdr; 58 uint32_t slr; 59 uint32_t den; 60 uint32_t cr; 61 uint32_t amsel; 62 qemu_irq irq; 63 qemu_irq out[N_GPIOS]; 64 const unsigned char *id; 65 }; 66 67 static const VMStateDescription vmstate_pl061 = { 68 .name = "pl061", 69 .version_id = 4, 70 .minimum_version_id = 4, 71 .fields = (VMStateField[]) { 72 VMSTATE_UINT32(locked, PL061State), 73 VMSTATE_UINT32(data, PL061State), 74 VMSTATE_UINT32(old_out_data, PL061State), 75 VMSTATE_UINT32(old_in_data, PL061State), 76 VMSTATE_UINT32(dir, PL061State), 77 VMSTATE_UINT32(isense, PL061State), 78 VMSTATE_UINT32(ibe, PL061State), 79 VMSTATE_UINT32(iev, PL061State), 80 VMSTATE_UINT32(im, PL061State), 81 VMSTATE_UINT32(istate, PL061State), 82 VMSTATE_UINT32(afsel, PL061State), 83 VMSTATE_UINT32(dr2r, PL061State), 84 VMSTATE_UINT32(dr4r, PL061State), 85 VMSTATE_UINT32(dr8r, PL061State), 86 VMSTATE_UINT32(odr, PL061State), 87 VMSTATE_UINT32(pur, PL061State), 88 VMSTATE_UINT32(pdr, PL061State), 89 VMSTATE_UINT32(slr, PL061State), 90 VMSTATE_UINT32(den, PL061State), 91 VMSTATE_UINT32(cr, PL061State), 92 VMSTATE_UINT32_V(amsel, PL061State, 2), 93 VMSTATE_END_OF_LIST() 94 } 95 }; 96 97 static void pl061_update(PL061State *s) 98 { 99 uint8_t changed; 100 uint8_t mask; 101 uint8_t out; 102 int i; 103 104 trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data); 105 106 /* Outputs float high. */ 107 /* FIXME: This is board dependent. */ 108 out = (s->data & s->dir) | ~s->dir; 109 changed = s->old_out_data ^ out; 110 if (changed) { 111 s->old_out_data = out; 112 for (i = 0; i < N_GPIOS; i++) { 113 mask = 1 << i; 114 if (changed & mask) { 115 int level = (out & mask) != 0; 116 trace_pl061_set_output(DEVICE(s)->canonical_path, i, level); 117 qemu_set_irq(s->out[i], level); 118 } 119 } 120 } 121 122 /* Inputs */ 123 changed = (s->old_in_data ^ s->data) & ~s->dir; 124 if (changed) { 125 s->old_in_data = s->data; 126 for (i = 0; i < N_GPIOS; i++) { 127 mask = 1 << i; 128 if (changed & mask) { 129 trace_pl061_input_change(DEVICE(s)->canonical_path, i, 130 (s->data & mask) != 0); 131 132 if (!(s->isense & mask)) { 133 /* Edge interrupt */ 134 if (s->ibe & mask) { 135 /* Any edge triggers the interrupt */ 136 s->istate |= mask; 137 } else { 138 /* Edge is selected by IEV */ 139 s->istate |= ~(s->data ^ s->iev) & mask; 140 } 141 } 142 } 143 } 144 } 145 146 /* Level interrupt */ 147 s->istate |= ~(s->data ^ s->iev) & s->isense; 148 149 trace_pl061_update_istate(DEVICE(s)->canonical_path, 150 s->istate, s->im, (s->istate & s->im) != 0); 151 152 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 153 } 154 155 static uint64_t pl061_read(void *opaque, hwaddr offset, 156 unsigned size) 157 { 158 PL061State *s = (PL061State *)opaque; 159 uint64_t r = 0; 160 161 switch (offset) { 162 case 0x0 ... 0x3ff: /* Data */ 163 r = s->data & (offset >> 2); 164 break; 165 case 0x400: /* Direction */ 166 r = s->dir; 167 break; 168 case 0x404: /* Interrupt sense */ 169 r = s->isense; 170 break; 171 case 0x408: /* Interrupt both edges */ 172 r = s->ibe; 173 break; 174 case 0x40c: /* Interrupt event */ 175 r = s->iev; 176 break; 177 case 0x410: /* Interrupt mask */ 178 r = s->im; 179 break; 180 case 0x414: /* Raw interrupt status */ 181 r = s->istate; 182 break; 183 case 0x418: /* Masked interrupt status */ 184 r = s->istate & s->im; 185 break; 186 case 0x420: /* Alternate function select */ 187 r = s->afsel; 188 break; 189 case 0x500: /* 2mA drive */ 190 if (s->id != pl061_id_luminary) { 191 goto bad_offset; 192 } 193 r = s->dr2r; 194 break; 195 case 0x504: /* 4mA drive */ 196 if (s->id != pl061_id_luminary) { 197 goto bad_offset; 198 } 199 r = s->dr4r; 200 break; 201 case 0x508: /* 8mA drive */ 202 if (s->id != pl061_id_luminary) { 203 goto bad_offset; 204 } 205 r = s->dr8r; 206 break; 207 case 0x50c: /* Open drain */ 208 if (s->id != pl061_id_luminary) { 209 goto bad_offset; 210 } 211 r = s->odr; 212 break; 213 case 0x510: /* Pull-up */ 214 if (s->id != pl061_id_luminary) { 215 goto bad_offset; 216 } 217 r = s->pur; 218 break; 219 case 0x514: /* Pull-down */ 220 if (s->id != pl061_id_luminary) { 221 goto bad_offset; 222 } 223 r = s->pdr; 224 break; 225 case 0x518: /* Slew rate control */ 226 if (s->id != pl061_id_luminary) { 227 goto bad_offset; 228 } 229 r = s->slr; 230 break; 231 case 0x51c: /* Digital enable */ 232 if (s->id != pl061_id_luminary) { 233 goto bad_offset; 234 } 235 r = s->den; 236 break; 237 case 0x520: /* Lock */ 238 if (s->id != pl061_id_luminary) { 239 goto bad_offset; 240 } 241 r = s->locked; 242 break; 243 case 0x524: /* Commit */ 244 if (s->id != pl061_id_luminary) { 245 goto bad_offset; 246 } 247 r = s->cr; 248 break; 249 case 0x528: /* Analog mode select */ 250 if (s->id != pl061_id_luminary) { 251 goto bad_offset; 252 } 253 r = s->amsel; 254 break; 255 case 0xfd0 ... 0xfff: /* ID registers */ 256 r = s->id[(offset - 0xfd0) >> 2]; 257 break; 258 default: 259 bad_offset: 260 qemu_log_mask(LOG_GUEST_ERROR, 261 "pl061_read: Bad offset %x\n", (int)offset); 262 break; 263 } 264 265 trace_pl061_read(DEVICE(s)->canonical_path, offset, r); 266 return r; 267 } 268 269 static void pl061_write(void *opaque, hwaddr offset, 270 uint64_t value, unsigned size) 271 { 272 PL061State *s = (PL061State *)opaque; 273 uint8_t mask; 274 275 trace_pl061_write(DEVICE(s)->canonical_path, offset, value); 276 277 switch (offset) { 278 case 0 ... 0x3ff: 279 mask = (offset >> 2) & s->dir; 280 s->data = (s->data & ~mask) | (value & mask); 281 pl061_update(s); 282 return; 283 case 0x400: /* Direction */ 284 s->dir = value & 0xff; 285 break; 286 case 0x404: /* Interrupt sense */ 287 s->isense = value & 0xff; 288 break; 289 case 0x408: /* Interrupt both edges */ 290 s->ibe = value & 0xff; 291 break; 292 case 0x40c: /* Interrupt event */ 293 s->iev = value & 0xff; 294 break; 295 case 0x410: /* Interrupt mask */ 296 s->im = value & 0xff; 297 break; 298 case 0x41c: /* Interrupt clear */ 299 s->istate &= ~value; 300 break; 301 case 0x420: /* Alternate function select */ 302 mask = s->cr; 303 s->afsel = (s->afsel & ~mask) | (value & mask); 304 break; 305 case 0x500: /* 2mA drive */ 306 if (s->id != pl061_id_luminary) { 307 goto bad_offset; 308 } 309 s->dr2r = value & 0xff; 310 break; 311 case 0x504: /* 4mA drive */ 312 if (s->id != pl061_id_luminary) { 313 goto bad_offset; 314 } 315 s->dr4r = value & 0xff; 316 break; 317 case 0x508: /* 8mA drive */ 318 if (s->id != pl061_id_luminary) { 319 goto bad_offset; 320 } 321 s->dr8r = value & 0xff; 322 break; 323 case 0x50c: /* Open drain */ 324 if (s->id != pl061_id_luminary) { 325 goto bad_offset; 326 } 327 s->odr = value & 0xff; 328 break; 329 case 0x510: /* Pull-up */ 330 if (s->id != pl061_id_luminary) { 331 goto bad_offset; 332 } 333 s->pur = value & 0xff; 334 break; 335 case 0x514: /* Pull-down */ 336 if (s->id != pl061_id_luminary) { 337 goto bad_offset; 338 } 339 s->pdr = value & 0xff; 340 break; 341 case 0x518: /* Slew rate control */ 342 if (s->id != pl061_id_luminary) { 343 goto bad_offset; 344 } 345 s->slr = value & 0xff; 346 break; 347 case 0x51c: /* Digital enable */ 348 if (s->id != pl061_id_luminary) { 349 goto bad_offset; 350 } 351 s->den = value & 0xff; 352 break; 353 case 0x520: /* Lock */ 354 if (s->id != pl061_id_luminary) { 355 goto bad_offset; 356 } 357 s->locked = (value != 0xacce551); 358 break; 359 case 0x524: /* Commit */ 360 if (s->id != pl061_id_luminary) { 361 goto bad_offset; 362 } 363 if (!s->locked) 364 s->cr = value & 0xff; 365 break; 366 case 0x528: 367 if (s->id != pl061_id_luminary) { 368 goto bad_offset; 369 } 370 s->amsel = value & 0xff; 371 break; 372 default: 373 bad_offset: 374 qemu_log_mask(LOG_GUEST_ERROR, 375 "pl061_write: Bad offset %x\n", (int)offset); 376 return; 377 } 378 pl061_update(s); 379 return; 380 } 381 382 static void pl061_reset(DeviceState *dev) 383 { 384 PL061State *s = PL061(dev); 385 386 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 387 s->data = 0; 388 s->old_out_data = 0; 389 s->old_in_data = 0; 390 s->dir = 0; 391 s->isense = 0; 392 s->ibe = 0; 393 s->iev = 0; 394 s->im = 0; 395 s->istate = 0; 396 s->afsel = 0; 397 s->dr2r = 0xff; 398 s->dr4r = 0; 399 s->dr8r = 0; 400 s->odr = 0; 401 s->pur = 0; 402 s->pdr = 0; 403 s->slr = 0; 404 s->den = 0; 405 s->locked = 1; 406 s->cr = 0xff; 407 s->amsel = 0; 408 } 409 410 static void pl061_set_irq(void * opaque, int irq, int level) 411 { 412 PL061State *s = (PL061State *)opaque; 413 uint8_t mask; 414 415 mask = 1 << irq; 416 if ((s->dir & mask) == 0) { 417 s->data &= ~mask; 418 if (level) 419 s->data |= mask; 420 pl061_update(s); 421 } 422 } 423 424 static const MemoryRegionOps pl061_ops = { 425 .read = pl061_read, 426 .write = pl061_write, 427 .endianness = DEVICE_NATIVE_ENDIAN, 428 }; 429 430 static void pl061_luminary_init(Object *obj) 431 { 432 PL061State *s = PL061(obj); 433 434 s->id = pl061_id_luminary; 435 } 436 437 static void pl061_init(Object *obj) 438 { 439 PL061State *s = PL061(obj); 440 DeviceState *dev = DEVICE(obj); 441 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 442 443 s->id = pl061_id; 444 445 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); 446 sysbus_init_mmio(sbd, &s->iomem); 447 sysbus_init_irq(sbd, &s->irq); 448 qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS); 449 qdev_init_gpio_out(dev, s->out, N_GPIOS); 450 } 451 452 static void pl061_class_init(ObjectClass *klass, void *data) 453 { 454 DeviceClass *dc = DEVICE_CLASS(klass); 455 456 dc->vmsd = &vmstate_pl061; 457 dc->reset = &pl061_reset; 458 } 459 460 static const TypeInfo pl061_info = { 461 .name = TYPE_PL061, 462 .parent = TYPE_SYS_BUS_DEVICE, 463 .instance_size = sizeof(PL061State), 464 .instance_init = pl061_init, 465 .class_init = pl061_class_init, 466 }; 467 468 static const TypeInfo pl061_luminary_info = { 469 .name = "pl061_luminary", 470 .parent = TYPE_PL061, 471 .instance_init = pl061_luminary_init, 472 }; 473 474 static void pl061_register_types(void) 475 { 476 type_register_static(&pl061_info); 477 type_register_static(&pl061_luminary_info); 478 } 479 480 type_init(pl061_register_types) 481