19ee6e8bbSpbrook /* 29ee6e8bbSpbrook * Arm PrimeCell PL061 General Purpose IO with additional 39ee6e8bbSpbrook * Luminary Micro Stellaris bits. 49ee6e8bbSpbrook * 59ee6e8bbSpbrook * Copyright (c) 2007 CodeSourcery. 69ee6e8bbSpbrook * Written by Paul Brook 79ee6e8bbSpbrook * 88e31bf38SMatthew Fernandez * This code is licensed under the GPL. 99ee6e8bbSpbrook */ 109ee6e8bbSpbrook 118ef94f0bSPeter Maydell #include "qemu/osdep.h" 12*64552b6bSMarkus Armbruster #include "hw/irq.h" 1383c9f4caSPaolo Bonzini #include "hw/sysbus.h" 1403dd024fSPaolo Bonzini #include "qemu/log.h" 150b8fa32fSMarkus Armbruster #include "qemu/module.h" 169ee6e8bbSpbrook 179ee6e8bbSpbrook //#define DEBUG_PL061 1 189ee6e8bbSpbrook 199ee6e8bbSpbrook #ifdef DEBUG_PL061 20001faf32SBlue Swirl #define DPRINTF(fmt, ...) \ 21001faf32SBlue Swirl do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) 22001faf32SBlue Swirl #define BADF(fmt, ...) \ 23001faf32SBlue Swirl do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 249ee6e8bbSpbrook #else 25001faf32SBlue Swirl #define DPRINTF(fmt, ...) do {} while(0) 26001faf32SBlue Swirl #define BADF(fmt, ...) \ 27001faf32SBlue Swirl do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) 289ee6e8bbSpbrook #endif 299ee6e8bbSpbrook 309ee6e8bbSpbrook static const uint8_t pl061_id[12] = 317063f49fSPeter Maydell { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 327063f49fSPeter Maydell static const uint8_t pl061_id_luminary[12] = 339ee6e8bbSpbrook { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 349ee6e8bbSpbrook 35692a76d1SAndreas Färber #define TYPE_PL061 "pl061" 36692a76d1SAndreas Färber #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061) 37692a76d1SAndreas Färber 38ee663e96SAndreas Färber typedef struct PL061State { 39692a76d1SAndreas Färber SysBusDevice parent_obj; 40692a76d1SAndreas Färber 413cf89f8aSAvi Kivity MemoryRegion iomem; 42a35faa94SPeter Maydell uint32_t locked; 43a35faa94SPeter Maydell uint32_t data; 44bfb27e60SColin Leitner uint32_t old_out_data; 45bfb27e60SColin Leitner uint32_t old_in_data; 46a35faa94SPeter Maydell uint32_t dir; 47a35faa94SPeter Maydell uint32_t isense; 48a35faa94SPeter Maydell uint32_t ibe; 49a35faa94SPeter Maydell uint32_t iev; 50a35faa94SPeter Maydell uint32_t im; 51a35faa94SPeter Maydell uint32_t istate; 52a35faa94SPeter Maydell uint32_t afsel; 53a35faa94SPeter Maydell uint32_t dr2r; 54a35faa94SPeter Maydell uint32_t dr4r; 55a35faa94SPeter Maydell uint32_t dr8r; 56a35faa94SPeter Maydell uint32_t odr; 57a35faa94SPeter Maydell uint32_t pur; 58a35faa94SPeter Maydell uint32_t pdr; 59a35faa94SPeter Maydell uint32_t slr; 60a35faa94SPeter Maydell uint32_t den; 61a35faa94SPeter Maydell uint32_t cr; 62b3aaff11SPeter Maydell uint32_t amsel; 639ee6e8bbSpbrook qemu_irq irq; 649ee6e8bbSpbrook qemu_irq out[8]; 657063f49fSPeter Maydell const unsigned char *id; 6609aa3bf3SWei Huang uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ 67ee663e96SAndreas Färber } PL061State; 689ee6e8bbSpbrook 69a35faa94SPeter Maydell static const VMStateDescription vmstate_pl061 = { 70a35faa94SPeter Maydell .name = "pl061", 71c3a86b35SWei Huang .version_id = 4, 72c3a86b35SWei Huang .minimum_version_id = 4, 73a35faa94SPeter Maydell .fields = (VMStateField[]) { 74ee663e96SAndreas Färber VMSTATE_UINT32(locked, PL061State), 75ee663e96SAndreas Färber VMSTATE_UINT32(data, PL061State), 76bfb27e60SColin Leitner VMSTATE_UINT32(old_out_data, PL061State), 77bfb27e60SColin Leitner VMSTATE_UINT32(old_in_data, PL061State), 78ee663e96SAndreas Färber VMSTATE_UINT32(dir, PL061State), 79ee663e96SAndreas Färber VMSTATE_UINT32(isense, PL061State), 80ee663e96SAndreas Färber VMSTATE_UINT32(ibe, PL061State), 81ee663e96SAndreas Färber VMSTATE_UINT32(iev, PL061State), 82ee663e96SAndreas Färber VMSTATE_UINT32(im, PL061State), 83ee663e96SAndreas Färber VMSTATE_UINT32(istate, PL061State), 84ee663e96SAndreas Färber VMSTATE_UINT32(afsel, PL061State), 85ee663e96SAndreas Färber VMSTATE_UINT32(dr2r, PL061State), 86ee663e96SAndreas Färber VMSTATE_UINT32(dr4r, PL061State), 87ee663e96SAndreas Färber VMSTATE_UINT32(dr8r, PL061State), 88ee663e96SAndreas Färber VMSTATE_UINT32(odr, PL061State), 89ee663e96SAndreas Färber VMSTATE_UINT32(pur, PL061State), 90ee663e96SAndreas Färber VMSTATE_UINT32(pdr, PL061State), 91ee663e96SAndreas Färber VMSTATE_UINT32(slr, PL061State), 92ee663e96SAndreas Färber VMSTATE_UINT32(den, PL061State), 93ee663e96SAndreas Färber VMSTATE_UINT32(cr, PL061State), 94ee663e96SAndreas Färber VMSTATE_UINT32_V(amsel, PL061State, 2), 95a35faa94SPeter Maydell VMSTATE_END_OF_LIST() 96a35faa94SPeter Maydell } 97a35faa94SPeter Maydell }; 98a35faa94SPeter Maydell 99ee663e96SAndreas Färber static void pl061_update(PL061State *s) 1009ee6e8bbSpbrook { 1019ee6e8bbSpbrook uint8_t changed; 1029ee6e8bbSpbrook uint8_t mask; 103775616c3Spbrook uint8_t out; 1049ee6e8bbSpbrook int i; 1059ee6e8bbSpbrook 106bfb27e60SColin Leitner DPRINTF("dir = %d, data = %d\n", s->dir, s->data); 107bfb27e60SColin Leitner 108775616c3Spbrook /* Outputs float high. */ 109775616c3Spbrook /* FIXME: This is board dependent. */ 110775616c3Spbrook out = (s->data & s->dir) | ~s->dir; 111bfb27e60SColin Leitner changed = s->old_out_data ^ out; 112bfb27e60SColin Leitner if (changed) { 113bfb27e60SColin Leitner s->old_out_data = out; 1149ee6e8bbSpbrook for (i = 0; i < 8; i++) { 1159ee6e8bbSpbrook mask = 1 << i; 116b78c2b3aSPeter Maydell if (changed & mask) { 117775616c3Spbrook DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); 118775616c3Spbrook qemu_set_irq(s->out[i], (out & mask) != 0); 1199ee6e8bbSpbrook } 1209ee6e8bbSpbrook } 121bfb27e60SColin Leitner } 1229ee6e8bbSpbrook 123bfb27e60SColin Leitner /* Inputs */ 124bfb27e60SColin Leitner changed = (s->old_in_data ^ s->data) & ~s->dir; 125bfb27e60SColin Leitner if (changed) { 126bfb27e60SColin Leitner s->old_in_data = s->data; 127bfb27e60SColin Leitner for (i = 0; i < 8; i++) { 128bfb27e60SColin Leitner mask = 1 << i; 129bfb27e60SColin Leitner if (changed & mask) { 130bfb27e60SColin Leitner DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); 131bfb27e60SColin Leitner 132bfb27e60SColin Leitner if (!(s->isense & mask)) { 133bfb27e60SColin Leitner /* Edge interrupt */ 134bfb27e60SColin Leitner if (s->ibe & mask) { 135bfb27e60SColin Leitner /* Any edge triggers the interrupt */ 136bfb27e60SColin Leitner s->istate |= mask; 137bfb27e60SColin Leitner } else { 138bfb27e60SColin Leitner /* Edge is selected by IEV */ 139bfb27e60SColin Leitner s->istate |= ~(s->data ^ s->iev) & mask; 140bfb27e60SColin Leitner } 141bfb27e60SColin Leitner } 142bfb27e60SColin Leitner } 143bfb27e60SColin Leitner } 144bfb27e60SColin Leitner } 145bfb27e60SColin Leitner 146bfb27e60SColin Leitner /* Level interrupt */ 147bfb27e60SColin Leitner s->istate |= ~(s->data ^ s->iev) & s->isense; 148bfb27e60SColin Leitner 149bfb27e60SColin Leitner DPRINTF("istate = %02X\n", s->istate); 150bfb27e60SColin Leitner 151bfb27e60SColin Leitner qemu_set_irq(s->irq, (s->istate & s->im) != 0); 1529ee6e8bbSpbrook } 1539ee6e8bbSpbrook 154a8170e5eSAvi Kivity static uint64_t pl061_read(void *opaque, hwaddr offset, 1553cf89f8aSAvi Kivity unsigned size) 1569ee6e8bbSpbrook { 157ee663e96SAndreas Färber PL061State *s = (PL061State *)opaque; 1589ee6e8bbSpbrook 1599ee6e8bbSpbrook if (offset < 0x400) { 1609ee6e8bbSpbrook return s->data & (offset >> 2); 1619ee6e8bbSpbrook } 16209aa3bf3SWei Huang if (offset >= s->rsvd_start && offset <= 0xfcc) { 16309aa3bf3SWei Huang goto err_out; 16409aa3bf3SWei Huang } 16509aa3bf3SWei Huang if (offset >= 0xfd0 && offset < 0x1000) { 16609aa3bf3SWei Huang return s->id[(offset - 0xfd0) >> 2]; 16709aa3bf3SWei Huang } 1689ee6e8bbSpbrook switch (offset) { 1699ee6e8bbSpbrook case 0x400: /* Direction */ 1709ee6e8bbSpbrook return s->dir; 1719ee6e8bbSpbrook case 0x404: /* Interrupt sense */ 1729ee6e8bbSpbrook return s->isense; 1739ee6e8bbSpbrook case 0x408: /* Interrupt both edges */ 1749ee6e8bbSpbrook return s->ibe; 175ff2712baSStefan Weil case 0x40c: /* Interrupt event */ 1769ee6e8bbSpbrook return s->iev; 1779ee6e8bbSpbrook case 0x410: /* Interrupt mask */ 1789ee6e8bbSpbrook return s->im; 1799ee6e8bbSpbrook case 0x414: /* Raw interrupt status */ 1809ee6e8bbSpbrook return s->istate; 1819ee6e8bbSpbrook case 0x418: /* Masked interrupt status */ 1820b2ff2ceSVictor CLEMENT return s->istate & s->im; 1839ee6e8bbSpbrook case 0x420: /* Alternate function select */ 1849ee6e8bbSpbrook return s->afsel; 1859ee6e8bbSpbrook case 0x500: /* 2mA drive */ 1869ee6e8bbSpbrook return s->dr2r; 1879ee6e8bbSpbrook case 0x504: /* 4mA drive */ 1889ee6e8bbSpbrook return s->dr4r; 1899ee6e8bbSpbrook case 0x508: /* 8mA drive */ 1909ee6e8bbSpbrook return s->dr8r; 1919ee6e8bbSpbrook case 0x50c: /* Open drain */ 1929ee6e8bbSpbrook return s->odr; 1939ee6e8bbSpbrook case 0x510: /* Pull-up */ 1949ee6e8bbSpbrook return s->pur; 1959ee6e8bbSpbrook case 0x514: /* Pull-down */ 1969ee6e8bbSpbrook return s->pdr; 1979ee6e8bbSpbrook case 0x518: /* Slew rate control */ 1989ee6e8bbSpbrook return s->slr; 1999ee6e8bbSpbrook case 0x51c: /* Digital enable */ 2009ee6e8bbSpbrook return s->den; 2019ee6e8bbSpbrook case 0x520: /* Lock */ 2029ee6e8bbSpbrook return s->locked; 2039ee6e8bbSpbrook case 0x524: /* Commit */ 2049ee6e8bbSpbrook return s->cr; 205b3aaff11SPeter Maydell case 0x528: /* Analog mode select */ 206b3aaff11SPeter Maydell return s->amsel; 2079ee6e8bbSpbrook default: 20809aa3bf3SWei Huang break; 20909aa3bf3SWei Huang } 21009aa3bf3SWei Huang err_out: 211abff909cSPeter Maydell qemu_log_mask(LOG_GUEST_ERROR, 212abff909cSPeter Maydell "pl061_read: Bad offset %x\n", (int)offset); 2139ee6e8bbSpbrook return 0; 2149ee6e8bbSpbrook } 2159ee6e8bbSpbrook 216a8170e5eSAvi Kivity static void pl061_write(void *opaque, hwaddr offset, 2173cf89f8aSAvi Kivity uint64_t value, unsigned size) 2189ee6e8bbSpbrook { 219ee663e96SAndreas Färber PL061State *s = (PL061State *)opaque; 2209ee6e8bbSpbrook uint8_t mask; 2219ee6e8bbSpbrook 2229ee6e8bbSpbrook if (offset < 0x400) { 2239ee6e8bbSpbrook mask = (offset >> 2) & s->dir; 2249ee6e8bbSpbrook s->data = (s->data & ~mask) | (value & mask); 2259ee6e8bbSpbrook pl061_update(s); 2269ee6e8bbSpbrook return; 2279ee6e8bbSpbrook } 22809aa3bf3SWei Huang if (offset >= s->rsvd_start) { 22909aa3bf3SWei Huang goto err_out; 23009aa3bf3SWei Huang } 2319ee6e8bbSpbrook switch (offset) { 2329ee6e8bbSpbrook case 0x400: /* Direction */ 233a35faa94SPeter Maydell s->dir = value & 0xff; 2349ee6e8bbSpbrook break; 2359ee6e8bbSpbrook case 0x404: /* Interrupt sense */ 236a35faa94SPeter Maydell s->isense = value & 0xff; 2379ee6e8bbSpbrook break; 2389ee6e8bbSpbrook case 0x408: /* Interrupt both edges */ 239a35faa94SPeter Maydell s->ibe = value & 0xff; 2409ee6e8bbSpbrook break; 241ff2712baSStefan Weil case 0x40c: /* Interrupt event */ 242a35faa94SPeter Maydell s->iev = value & 0xff; 2439ee6e8bbSpbrook break; 2449ee6e8bbSpbrook case 0x410: /* Interrupt mask */ 245a35faa94SPeter Maydell s->im = value & 0xff; 2469ee6e8bbSpbrook break; 2479ee6e8bbSpbrook case 0x41c: /* Interrupt clear */ 2489ee6e8bbSpbrook s->istate &= ~value; 2499ee6e8bbSpbrook break; 2509ee6e8bbSpbrook case 0x420: /* Alternate function select */ 2519ee6e8bbSpbrook mask = s->cr; 2529ee6e8bbSpbrook s->afsel = (s->afsel & ~mask) | (value & mask); 2539ee6e8bbSpbrook break; 2549ee6e8bbSpbrook case 0x500: /* 2mA drive */ 255a35faa94SPeter Maydell s->dr2r = value & 0xff; 2569ee6e8bbSpbrook break; 2579ee6e8bbSpbrook case 0x504: /* 4mA drive */ 258a35faa94SPeter Maydell s->dr4r = value & 0xff; 2599ee6e8bbSpbrook break; 2609ee6e8bbSpbrook case 0x508: /* 8mA drive */ 261a35faa94SPeter Maydell s->dr8r = value & 0xff; 2629ee6e8bbSpbrook break; 2639ee6e8bbSpbrook case 0x50c: /* Open drain */ 264a35faa94SPeter Maydell s->odr = value & 0xff; 2659ee6e8bbSpbrook break; 2669ee6e8bbSpbrook case 0x510: /* Pull-up */ 267a35faa94SPeter Maydell s->pur = value & 0xff; 2689ee6e8bbSpbrook break; 2699ee6e8bbSpbrook case 0x514: /* Pull-down */ 270a35faa94SPeter Maydell s->pdr = value & 0xff; 2719ee6e8bbSpbrook break; 2729ee6e8bbSpbrook case 0x518: /* Slew rate control */ 273a35faa94SPeter Maydell s->slr = value & 0xff; 2749ee6e8bbSpbrook break; 2759ee6e8bbSpbrook case 0x51c: /* Digital enable */ 276a35faa94SPeter Maydell s->den = value & 0xff; 2779ee6e8bbSpbrook break; 2789ee6e8bbSpbrook case 0x520: /* Lock */ 2799ee6e8bbSpbrook s->locked = (value != 0xacce551); 2809ee6e8bbSpbrook break; 2819ee6e8bbSpbrook case 0x524: /* Commit */ 2829ee6e8bbSpbrook if (!s->locked) 283a35faa94SPeter Maydell s->cr = value & 0xff; 2849ee6e8bbSpbrook break; 285b3aaff11SPeter Maydell case 0x528: 286b3aaff11SPeter Maydell s->amsel = value & 0xff; 287b3aaff11SPeter Maydell break; 2889ee6e8bbSpbrook default: 28909aa3bf3SWei Huang goto err_out; 2909ee6e8bbSpbrook } 2919ee6e8bbSpbrook pl061_update(s); 29209aa3bf3SWei Huang return; 29309aa3bf3SWei Huang err_out: 29409aa3bf3SWei Huang qemu_log_mask(LOG_GUEST_ERROR, 29509aa3bf3SWei Huang "pl061_write: Bad offset %x\n", (int)offset); 2969ee6e8bbSpbrook } 2979ee6e8bbSpbrook 298b527db44SWei Huang static void pl061_reset(DeviceState *dev) 2999ee6e8bbSpbrook { 300b527db44SWei Huang PL061State *s = PL061(dev); 301b527db44SWei Huang 302b527db44SWei Huang /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 303b527db44SWei Huang s->data = 0; 304b527db44SWei Huang s->old_out_data = 0; 305b527db44SWei Huang s->old_in_data = 0; 306b527db44SWei Huang s->dir = 0; 307b527db44SWei Huang s->isense = 0; 308b527db44SWei Huang s->ibe = 0; 309b527db44SWei Huang s->iev = 0; 310b527db44SWei Huang s->im = 0; 311b527db44SWei Huang s->istate = 0; 312b527db44SWei Huang s->afsel = 0; 313b527db44SWei Huang s->dr2r = 0xff; 314b527db44SWei Huang s->dr4r = 0; 315b527db44SWei Huang s->dr8r = 0; 316b527db44SWei Huang s->odr = 0; 317b527db44SWei Huang s->pur = 0; 318b527db44SWei Huang s->pdr = 0; 319b527db44SWei Huang s->slr = 0; 320b527db44SWei Huang s->den = 0; 3219ee6e8bbSpbrook s->locked = 1; 3229ee6e8bbSpbrook s->cr = 0xff; 323b527db44SWei Huang s->amsel = 0; 3249ee6e8bbSpbrook } 3259ee6e8bbSpbrook 3269596ebb7Spbrook static void pl061_set_irq(void * opaque, int irq, int level) 3279ee6e8bbSpbrook { 328ee663e96SAndreas Färber PL061State *s = (PL061State *)opaque; 3299ee6e8bbSpbrook uint8_t mask; 3309ee6e8bbSpbrook 3319ee6e8bbSpbrook mask = 1 << irq; 3329ee6e8bbSpbrook if ((s->dir & mask) == 0) { 3339ee6e8bbSpbrook s->data &= ~mask; 3349ee6e8bbSpbrook if (level) 3359ee6e8bbSpbrook s->data |= mask; 3369ee6e8bbSpbrook pl061_update(s); 3379ee6e8bbSpbrook } 3389ee6e8bbSpbrook } 3399ee6e8bbSpbrook 3403cf89f8aSAvi Kivity static const MemoryRegionOps pl061_ops = { 3413cf89f8aSAvi Kivity .read = pl061_read, 3423cf89f8aSAvi Kivity .write = pl061_write, 3433cf89f8aSAvi Kivity .endianness = DEVICE_NATIVE_ENDIAN, 3449ee6e8bbSpbrook }; 3459ee6e8bbSpbrook 346692a76d1SAndreas Färber static void pl061_luminary_init(Object *obj) 3477063f49fSPeter Maydell { 348692a76d1SAndreas Färber PL061State *s = PL061(obj); 349692a76d1SAndreas Färber 350692a76d1SAndreas Färber s->id = pl061_id_luminary; 35109aa3bf3SWei Huang s->rsvd_start = 0x52c; 3527063f49fSPeter Maydell } 3537063f49fSPeter Maydell 354692a76d1SAndreas Färber static void pl061_init(Object *obj) 3557063f49fSPeter Maydell { 356692a76d1SAndreas Färber PL061State *s = PL061(obj); 35709e6fb3eSxiaoqiang zhao DeviceState *dev = DEVICE(obj); 35809e6fb3eSxiaoqiang zhao SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 359692a76d1SAndreas Färber 360692a76d1SAndreas Färber s->id = pl061_id; 36109aa3bf3SWei Huang s->rsvd_start = 0x424; 36209e6fb3eSxiaoqiang zhao 36309e6fb3eSxiaoqiang zhao memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); 36409e6fb3eSxiaoqiang zhao sysbus_init_mmio(sbd, &s->iomem); 36509e6fb3eSxiaoqiang zhao sysbus_init_irq(sbd, &s->irq); 36609e6fb3eSxiaoqiang zhao qdev_init_gpio_in(dev, pl061_set_irq, 8); 36709e6fb3eSxiaoqiang zhao qdev_init_gpio_out(dev, s->out, 8); 3687063f49fSPeter Maydell } 3697063f49fSPeter Maydell 370999e12bbSAnthony Liguori static void pl061_class_init(ObjectClass *klass, void *data) 371999e12bbSAnthony Liguori { 37239bffca2SAnthony Liguori DeviceClass *dc = DEVICE_CLASS(klass); 373999e12bbSAnthony Liguori 37439bffca2SAnthony Liguori dc->vmsd = &vmstate_pl061; 375b527db44SWei Huang dc->reset = &pl061_reset; 376999e12bbSAnthony Liguori } 377999e12bbSAnthony Liguori 3788c43a6f0SAndreas Färber static const TypeInfo pl061_info = { 379692a76d1SAndreas Färber .name = TYPE_PL061, 38039bffca2SAnthony Liguori .parent = TYPE_SYS_BUS_DEVICE, 381ee663e96SAndreas Färber .instance_size = sizeof(PL061State), 382692a76d1SAndreas Färber .instance_init = pl061_init, 383999e12bbSAnthony Liguori .class_init = pl061_class_init, 384a35faa94SPeter Maydell }; 385a35faa94SPeter Maydell 3868c43a6f0SAndreas Färber static const TypeInfo pl061_luminary_info = { 387999e12bbSAnthony Liguori .name = "pl061_luminary", 388692a76d1SAndreas Färber .parent = TYPE_PL061, 389692a76d1SAndreas Färber .instance_init = pl061_luminary_init, 390a35faa94SPeter Maydell }; 391a35faa94SPeter Maydell 39283f7d43aSAndreas Färber static void pl061_register_types(void) 39340905a6aSPaul Brook { 39439bffca2SAnthony Liguori type_register_static(&pl061_info); 39539bffca2SAnthony Liguori type_register_static(&pl061_luminary_info); 39640905a6aSPaul Brook } 39740905a6aSPaul Brook 39883f7d43aSAndreas Färber type_init(pl061_register_types) 399