1 /* 2 * ASPEED GPIO Controller 3 * 4 * Copyright (C) 2017-2019 IBM Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/host-utils.h" 11 #include "qemu/log.h" 12 #include "hw/gpio/aspeed_gpio.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "qapi/error.h" 15 #include "qapi/visitor.h" 16 #include "hw/irq.h" 17 #include "migration/vmstate.h" 18 #include "trace.h" 19 #include "hw/registerfields.h" 20 21 #define GPIOS_PER_GROUP 8 22 23 /* GPIO Source Types */ 24 #define ASPEED_CMD_SRC_MASK 0x01010101 25 #define ASPEED_SOURCE_ARM 0 26 #define ASPEED_SOURCE_LPC 1 27 #define ASPEED_SOURCE_COPROCESSOR 2 28 #define ASPEED_SOURCE_RESERVED 3 29 30 /* GPIO Interrupt Triggers */ 31 /* 32 * For each set of gpios there are three sensitivity registers that control 33 * the interrupt trigger mode. 34 * 35 * | 2 | 1 | 0 | trigger mode 36 * ----------------------------- 37 * | 0 | 0 | 0 | falling-edge 38 * | 0 | 0 | 1 | rising-edge 39 * | 0 | 1 | 0 | level-low 40 * | 0 | 1 | 1 | level-high 41 * | 1 | X | X | dual-edge 42 */ 43 #define ASPEED_FALLING_EDGE 0 44 #define ASPEED_RISING_EDGE 1 45 #define ASPEED_LEVEL_LOW 2 46 #define ASPEED_LEVEL_HIGH 3 47 #define ASPEED_DUAL_EDGE 4 48 49 /* GPIO Register Address Offsets */ 50 #define GPIO_ABCD_DATA_VALUE (0x000 >> 2) 51 #define GPIO_ABCD_DIRECTION (0x004 >> 2) 52 #define GPIO_ABCD_INT_ENABLE (0x008 >> 2) 53 #define GPIO_ABCD_INT_SENS_0 (0x00C >> 2) 54 #define GPIO_ABCD_INT_SENS_1 (0x010 >> 2) 55 #define GPIO_ABCD_INT_SENS_2 (0x014 >> 2) 56 #define GPIO_ABCD_INT_STATUS (0x018 >> 2) 57 #define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2) 58 #define GPIO_EFGH_DATA_VALUE (0x020 >> 2) 59 #define GPIO_EFGH_DIRECTION (0x024 >> 2) 60 #define GPIO_EFGH_INT_ENABLE (0x028 >> 2) 61 #define GPIO_EFGH_INT_SENS_0 (0x02C >> 2) 62 #define GPIO_EFGH_INT_SENS_1 (0x030 >> 2) 63 #define GPIO_EFGH_INT_SENS_2 (0x034 >> 2) 64 #define GPIO_EFGH_INT_STATUS (0x038 >> 2) 65 #define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2) 66 #define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2) 67 #define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2) 68 #define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2) 69 #define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2) 70 #define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2) 71 #define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2) 72 #define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2) 73 #define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2) 74 #define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2) 75 #define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2) 76 #define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2) 77 #define GPIO_IJKL_DATA_VALUE (0x070 >> 2) 78 #define GPIO_IJKL_DIRECTION (0x074 >> 2) 79 #define GPIO_MNOP_DATA_VALUE (0x078 >> 2) 80 #define GPIO_MNOP_DIRECTION (0x07C >> 2) 81 #define GPIO_QRST_DATA_VALUE (0x080 >> 2) 82 #define GPIO_QRST_DIRECTION (0x084 >> 2) 83 #define GPIO_UVWX_DATA_VALUE (0x088 >> 2) 84 #define GPIO_UVWX_DIRECTION (0x08C >> 2) 85 #define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2) 86 #define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2) 87 #define GPIO_IJKL_INT_ENABLE (0x098 >> 2) 88 #define GPIO_IJKL_INT_SENS_0 (0x09C >> 2) 89 #define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2) 90 #define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2) 91 #define GPIO_IJKL_INT_STATUS (0x0A8 >> 2) 92 #define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2) 93 #define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2) 94 #define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2) 95 #define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2) 96 #define GPIO_ABCD_DATA_READ (0x0C0 >> 2) 97 #define GPIO_EFGH_DATA_READ (0x0C4 >> 2) 98 #define GPIO_IJKL_DATA_READ (0x0C8 >> 2) 99 #define GPIO_MNOP_DATA_READ (0x0CC >> 2) 100 #define GPIO_QRST_DATA_READ (0x0D0 >> 2) 101 #define GPIO_UVWX_DATA_READ (0x0D4 >> 2) 102 #define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2) 103 #define GPIO_AC_DATA_READ (0x0DC >> 2) 104 #define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2) 105 #define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2) 106 #define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2) 107 #define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2) 108 #define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2) 109 #define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2) 110 #define GPIO_MNOP_INT_STATUS (0x0F8 >> 2) 111 #define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2) 112 #define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2) 113 #define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2) 114 #define GPIO_MNOP_INPUT_MASK (0x108 >> 2) 115 #define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2) 116 #define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2) 117 #define GPIO_QRST_INT_ENABLE (0x118 >> 2) 118 #define GPIO_QRST_INT_SENS_0 (0x11C >> 2) 119 #define GPIO_QRST_INT_SENS_1 (0x120 >> 2) 120 #define GPIO_QRST_INT_SENS_2 (0x124 >> 2) 121 #define GPIO_QRST_INT_STATUS (0x128 >> 2) 122 #define GPIO_QRST_RESET_TOLERANT (0x12C >> 2) 123 #define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2) 124 #define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2) 125 #define GPIO_QRST_INPUT_MASK (0x138 >> 2) 126 #define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2) 127 #define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2) 128 #define GPIO_UVWX_INT_ENABLE (0x148 >> 2) 129 #define GPIO_UVWX_INT_SENS_0 (0x14C >> 2) 130 #define GPIO_UVWX_INT_SENS_1 (0x150 >> 2) 131 #define GPIO_UVWX_INT_SENS_2 (0x154 >> 2) 132 #define GPIO_UVWX_INT_STATUS (0x158 >> 2) 133 #define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2) 134 #define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2) 135 #define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2) 136 #define GPIO_UVWX_INPUT_MASK (0x168 >> 2) 137 #define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2) 138 #define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2) 139 #define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2) 140 #define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2) 141 #define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2) 142 #define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2) 143 #define GPIO_YZAAAB_INT_STATUS (0x188 >> 2) 144 #define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2) 145 #define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2) 146 #define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2) 147 #define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2) 148 #define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2) 149 #define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2) 150 #define GPIO_AC_INT_ENABLE (0x1A8 >> 2) 151 #define GPIO_AC_INT_SENS_0 (0x1AC >> 2) 152 #define GPIO_AC_INT_SENS_1 (0x1B0 >> 2) 153 #define GPIO_AC_INT_SENS_2 (0x1B4 >> 2) 154 #define GPIO_AC_INT_STATUS (0x1B8 >> 2) 155 #define GPIO_AC_RESET_TOLERANT (0x1BC >> 2) 156 #define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2) 157 #define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2) 158 #define GPIO_AC_INPUT_MASK (0x1C8 >> 2) 159 #define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2) 160 #define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2) 161 #define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2) 162 #define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2) 163 #define GPIO_AC_DATA_VALUE (0x1E8 >> 2) 164 #define GPIO_AC_DIRECTION (0x1EC >> 2) 165 #define GPIO_3_3V_MEM_SIZE 0x1F0 166 #define GPIO_3_3V_REG_ARRAY_SIZE (GPIO_3_3V_MEM_SIZE >> 2) 167 168 /* AST2600 only - 1.8V gpios */ 169 /* 170 * The AST2600 two copies of the GPIO controller: the same 3.3V gpios as the 171 * AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios 172 * (memory offsets 0x800-0x9D4). 173 */ 174 #define GPIO_1_8V_ABCD_DATA_VALUE (0x000 >> 2) 175 #define GPIO_1_8V_ABCD_DIRECTION (0x004 >> 2) 176 #define GPIO_1_8V_ABCD_INT_ENABLE (0x008 >> 2) 177 #define GPIO_1_8V_ABCD_INT_SENS_0 (0x00C >> 2) 178 #define GPIO_1_8V_ABCD_INT_SENS_1 (0x010 >> 2) 179 #define GPIO_1_8V_ABCD_INT_SENS_2 (0x014 >> 2) 180 #define GPIO_1_8V_ABCD_INT_STATUS (0x018 >> 2) 181 #define GPIO_1_8V_ABCD_RESET_TOLERANT (0x01C >> 2) 182 #define GPIO_1_8V_E_DATA_VALUE (0x020 >> 2) 183 #define GPIO_1_8V_E_DIRECTION (0x024 >> 2) 184 #define GPIO_1_8V_E_INT_ENABLE (0x028 >> 2) 185 #define GPIO_1_8V_E_INT_SENS_0 (0x02C >> 2) 186 #define GPIO_1_8V_E_INT_SENS_1 (0x030 >> 2) 187 #define GPIO_1_8V_E_INT_SENS_2 (0x034 >> 2) 188 #define GPIO_1_8V_E_INT_STATUS (0x038 >> 2) 189 #define GPIO_1_8V_E_RESET_TOLERANT (0x03C >> 2) 190 #define GPIO_1_8V_ABCD_DEBOUNCE_1 (0x040 >> 2) 191 #define GPIO_1_8V_ABCD_DEBOUNCE_2 (0x044 >> 2) 192 #define GPIO_1_8V_E_DEBOUNCE_1 (0x048 >> 2) 193 #define GPIO_1_8V_E_DEBOUNCE_2 (0x04C >> 2) 194 #define GPIO_1_8V_DEBOUNCE_TIME_1 (0x050 >> 2) 195 #define GPIO_1_8V_DEBOUNCE_TIME_2 (0x054 >> 2) 196 #define GPIO_1_8V_DEBOUNCE_TIME_3 (0x058 >> 2) 197 #define GPIO_1_8V_ABCD_COMMAND_SRC_0 (0x060 >> 2) 198 #define GPIO_1_8V_ABCD_COMMAND_SRC_1 (0x064 >> 2) 199 #define GPIO_1_8V_E_COMMAND_SRC_0 (0x068 >> 2) 200 #define GPIO_1_8V_E_COMMAND_SRC_1 (0x06C >> 2) 201 #define GPIO_1_8V_ABCD_DATA_READ (0x0C0 >> 2) 202 #define GPIO_1_8V_E_DATA_READ (0x0C4 >> 2) 203 #define GPIO_1_8V_ABCD_INPUT_MASK (0x1D0 >> 2) 204 #define GPIO_1_8V_E_INPUT_MASK (0x1D4 >> 2) 205 #define GPIO_1_8V_MEM_SIZE 0x1D8 206 #define GPIO_1_8V_REG_ARRAY_SIZE (GPIO_1_8V_MEM_SIZE >> 2) 207 208 /* 209 * GPIO index mode support 210 * It only supports write operation 211 */ 212 REG32(GPIO_INDEX_REG, 0x2AC) 213 FIELD(GPIO_INDEX_REG, NUMBER, 0, 8) 214 FIELD(GPIO_INDEX_REG, COMMAND, 12, 1) 215 FIELD(GPIO_INDEX_REG, TYPE, 16, 4) 216 FIELD(GPIO_INDEX_REG, DATA_VALUE, 20, 1) 217 FIELD(GPIO_INDEX_REG, DIRECTION, 20, 1) 218 FIELD(GPIO_INDEX_REG, INT_ENABLE, 20, 1) 219 FIELD(GPIO_INDEX_REG, INT_SENS_0, 21, 1) 220 FIELD(GPIO_INDEX_REG, INT_SENS_1, 22, 1) 221 FIELD(GPIO_INDEX_REG, INT_SENS_2, 23, 1) 222 FIELD(GPIO_INDEX_REG, INT_STATUS, 24, 1) 223 FIELD(GPIO_INDEX_REG, DEBOUNCE_1, 20, 1) 224 FIELD(GPIO_INDEX_REG, DEBOUNCE_2, 21, 1) 225 FIELD(GPIO_INDEX_REG, RESET_TOLERANT, 20, 1) 226 FIELD(GPIO_INDEX_REG, COMMAND_SRC_0, 20, 1) 227 FIELD(GPIO_INDEX_REG, COMMAND_SRC_1, 21, 1) 228 FIELD(GPIO_INDEX_REG, INPUT_MASK, 20, 1) 229 230 static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) 231 { 232 uint32_t falling_edge = 0, rising_edge = 0; 233 uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1) 234 | extract32(regs->int_sens_1, gpio, 1) << 1 235 | extract32(regs->int_sens_2, gpio, 1) << 2; 236 uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1); 237 uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1); 238 239 if (!gpio_int_enabled) { 240 return 0; 241 } 242 243 /* Detect edges */ 244 if (gpio_curr_high && !gpio_prev_high) { 245 rising_edge = 1; 246 } else if (!gpio_curr_high && gpio_prev_high) { 247 falling_edge = 1; 248 } 249 250 if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) || 251 ((int_trigger == ASPEED_RISING_EDGE) && rising_edge) || 252 ((int_trigger == ASPEED_LEVEL_LOW) && !gpio_curr_high) || 253 ((int_trigger == ASPEED_LEVEL_HIGH) && gpio_curr_high) || 254 ((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge))) 255 { 256 regs->int_status = deposit32(regs->int_status, gpio, 1, 1); 257 return 1; 258 } 259 return 0; 260 } 261 262 #define nested_struct_index(ta, pa, m, tb, pb) \ 263 (pb - ((tb *)(((char *)pa) + offsetof(ta, m)))) 264 265 static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s, GPIOSets *regs) 266 { 267 return nested_struct_index(AspeedGPIOState, s, sets, GPIOSets, regs); 268 } 269 270 static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs, 271 uint32_t value, uint32_t mode_mask) 272 { 273 uint32_t input_mask = regs->input_mask; 274 uint32_t direction = regs->direction; 275 uint32_t old = regs->data_value; 276 uint32_t new = value; 277 uint32_t diff; 278 int gpio; 279 280 diff = (old ^ new); 281 diff &= mode_mask; 282 if (diff) { 283 for (gpio = 0; gpio < ASPEED_GPIOS_PER_SET; gpio++) { 284 uint32_t mask = 1U << gpio; 285 286 /* If the gpio needs to be updated... */ 287 if (!(diff & mask)) { 288 continue; 289 } 290 291 /* ...and we're output or not input-masked... */ 292 if (!(direction & mask) && (input_mask & mask)) { 293 continue; 294 } 295 296 /* ...then update the state. */ 297 if (mask & new) { 298 regs->data_value |= mask; 299 } else { 300 regs->data_value &= ~mask; 301 } 302 303 /* If the gpio is set to output... */ 304 if (direction & mask) { 305 /* ...trigger the line-state IRQ */ 306 ptrdiff_t set = aspeed_gpio_set_idx(s, regs); 307 qemu_set_irq(s->gpios[set][gpio], !!(new & mask)); 308 } else { 309 /* ...otherwise if we meet the line's current IRQ policy... */ 310 if (aspeed_evaluate_irq(regs, old & mask, gpio)) { 311 /* ...trigger the VIC IRQ */ 312 s->pending++; 313 } 314 } 315 } 316 } 317 qemu_set_irq(s->irq, !!(s->pending)); 318 } 319 320 static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx, 321 uint32_t pin) 322 { 323 uint32_t reg_val; 324 uint32_t pin_mask = 1 << pin; 325 326 reg_val = s->sets[set_idx].data_value; 327 328 return !!(reg_val & pin_mask); 329 } 330 331 static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx, 332 uint32_t pin, bool level) 333 { 334 uint32_t value = s->sets[set_idx].data_value; 335 uint32_t pin_mask = 1 << pin; 336 337 if (level) { 338 value |= pin_mask; 339 } else { 340 value &= ~pin_mask; 341 } 342 343 aspeed_gpio_update(s, &s->sets[set_idx], value, 344 ~s->sets[set_idx].direction); 345 } 346 347 /* 348 * | src_1 | src_2 | source | 349 * |-----------------------------| 350 * | 0 | 0 | ARM | 351 * | 0 | 1 | LPC | 352 * | 1 | 0 | Coprocessor| 353 * | 1 | 1 | Reserved | 354 * 355 * Once the source of a set is programmed, corresponding bits in the 356 * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and 357 * debounce registers can only be written by the source. 358 * 359 * Source is ARM by default 360 * only bits 24, 16, 8, and 0 can be set 361 * 362 * we don't currently have a model for the LPC or Coprocessor 363 */ 364 static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value, 365 uint32_t value) 366 { 367 int i; 368 int cmd_source; 369 370 /* assume the source is always ARM for now */ 371 int source = ASPEED_SOURCE_ARM; 372 373 uint32_t new_value = 0; 374 375 /* for each group in set */ 376 for (i = 0; i < ASPEED_GPIOS_PER_SET; i += GPIOS_PER_GROUP) { 377 cmd_source = extract32(regs->cmd_source_0, i, 1) 378 | (extract32(regs->cmd_source_1, i, 1) << 1); 379 380 if (source == cmd_source) { 381 new_value |= (0xff << i) & value; 382 } else { 383 new_value |= (0xff << i) & old_value; 384 } 385 } 386 return new_value; 387 } 388 389 static const AspeedGPIOReg aspeed_3_3v_gpios[GPIO_3_3V_REG_ARRAY_SIZE] = { 390 /* Set ABCD */ 391 [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value }, 392 [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction }, 393 [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable }, 394 [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 }, 395 [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 }, 396 [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 }, 397 [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status }, 398 [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant }, 399 [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 }, 400 [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 }, 401 [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 }, 402 [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 }, 403 [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read }, 404 [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask }, 405 /* Set EFGH */ 406 [GPIO_EFGH_DATA_VALUE] = { 1, gpio_reg_data_value }, 407 [GPIO_EFGH_DIRECTION] = { 1, gpio_reg_direction }, 408 [GPIO_EFGH_INT_ENABLE] = { 1, gpio_reg_int_enable }, 409 [GPIO_EFGH_INT_SENS_0] = { 1, gpio_reg_int_sens_0 }, 410 [GPIO_EFGH_INT_SENS_1] = { 1, gpio_reg_int_sens_1 }, 411 [GPIO_EFGH_INT_SENS_2] = { 1, gpio_reg_int_sens_2 }, 412 [GPIO_EFGH_INT_STATUS] = { 1, gpio_reg_int_status }, 413 [GPIO_EFGH_RESET_TOLERANT] = { 1, gpio_reg_reset_tolerant }, 414 [GPIO_EFGH_DEBOUNCE_1] = { 1, gpio_reg_debounce_1 }, 415 [GPIO_EFGH_DEBOUNCE_2] = { 1, gpio_reg_debounce_2 }, 416 [GPIO_EFGH_COMMAND_SRC_0] = { 1, gpio_reg_cmd_source_0 }, 417 [GPIO_EFGH_COMMAND_SRC_1] = { 1, gpio_reg_cmd_source_1 }, 418 [GPIO_EFGH_DATA_READ] = { 1, gpio_reg_data_read }, 419 [GPIO_EFGH_INPUT_MASK] = { 1, gpio_reg_input_mask }, 420 /* Set IJKL */ 421 [GPIO_IJKL_DATA_VALUE] = { 2, gpio_reg_data_value }, 422 [GPIO_IJKL_DIRECTION] = { 2, gpio_reg_direction }, 423 [GPIO_IJKL_INT_ENABLE] = { 2, gpio_reg_int_enable }, 424 [GPIO_IJKL_INT_SENS_0] = { 2, gpio_reg_int_sens_0 }, 425 [GPIO_IJKL_INT_SENS_1] = { 2, gpio_reg_int_sens_1 }, 426 [GPIO_IJKL_INT_SENS_2] = { 2, gpio_reg_int_sens_2 }, 427 [GPIO_IJKL_INT_STATUS] = { 2, gpio_reg_int_status }, 428 [GPIO_IJKL_RESET_TOLERANT] = { 2, gpio_reg_reset_tolerant }, 429 [GPIO_IJKL_DEBOUNCE_1] = { 2, gpio_reg_debounce_1 }, 430 [GPIO_IJKL_DEBOUNCE_2] = { 2, gpio_reg_debounce_2 }, 431 [GPIO_IJKL_COMMAND_SRC_0] = { 2, gpio_reg_cmd_source_0 }, 432 [GPIO_IJKL_COMMAND_SRC_1] = { 2, gpio_reg_cmd_source_1 }, 433 [GPIO_IJKL_DATA_READ] = { 2, gpio_reg_data_read }, 434 [GPIO_IJKL_INPUT_MASK] = { 2, gpio_reg_input_mask }, 435 /* Set MNOP */ 436 [GPIO_MNOP_DATA_VALUE] = { 3, gpio_reg_data_value }, 437 [GPIO_MNOP_DIRECTION] = { 3, gpio_reg_direction }, 438 [GPIO_MNOP_INT_ENABLE] = { 3, gpio_reg_int_enable }, 439 [GPIO_MNOP_INT_SENS_0] = { 3, gpio_reg_int_sens_0 }, 440 [GPIO_MNOP_INT_SENS_1] = { 3, gpio_reg_int_sens_1 }, 441 [GPIO_MNOP_INT_SENS_2] = { 3, gpio_reg_int_sens_2 }, 442 [GPIO_MNOP_INT_STATUS] = { 3, gpio_reg_int_status }, 443 [GPIO_MNOP_RESET_TOLERANT] = { 3, gpio_reg_reset_tolerant }, 444 [GPIO_MNOP_DEBOUNCE_1] = { 3, gpio_reg_debounce_1 }, 445 [GPIO_MNOP_DEBOUNCE_2] = { 3, gpio_reg_debounce_2 }, 446 [GPIO_MNOP_COMMAND_SRC_0] = { 3, gpio_reg_cmd_source_0 }, 447 [GPIO_MNOP_COMMAND_SRC_1] = { 3, gpio_reg_cmd_source_1 }, 448 [GPIO_MNOP_DATA_READ] = { 3, gpio_reg_data_read }, 449 [GPIO_MNOP_INPUT_MASK] = { 3, gpio_reg_input_mask }, 450 /* Set QRST */ 451 [GPIO_QRST_DATA_VALUE] = { 4, gpio_reg_data_value }, 452 [GPIO_QRST_DIRECTION] = { 4, gpio_reg_direction }, 453 [GPIO_QRST_INT_ENABLE] = { 4, gpio_reg_int_enable }, 454 [GPIO_QRST_INT_SENS_0] = { 4, gpio_reg_int_sens_0 }, 455 [GPIO_QRST_INT_SENS_1] = { 4, gpio_reg_int_sens_1 }, 456 [GPIO_QRST_INT_SENS_2] = { 4, gpio_reg_int_sens_2 }, 457 [GPIO_QRST_INT_STATUS] = { 4, gpio_reg_int_status }, 458 [GPIO_QRST_RESET_TOLERANT] = { 4, gpio_reg_reset_tolerant }, 459 [GPIO_QRST_DEBOUNCE_1] = { 4, gpio_reg_debounce_1 }, 460 [GPIO_QRST_DEBOUNCE_2] = { 4, gpio_reg_debounce_2 }, 461 [GPIO_QRST_COMMAND_SRC_0] = { 4, gpio_reg_cmd_source_0 }, 462 [GPIO_QRST_COMMAND_SRC_1] = { 4, gpio_reg_cmd_source_1 }, 463 [GPIO_QRST_DATA_READ] = { 4, gpio_reg_data_read }, 464 [GPIO_QRST_INPUT_MASK] = { 4, gpio_reg_input_mask }, 465 /* Set UVWX */ 466 [GPIO_UVWX_DATA_VALUE] = { 5, gpio_reg_data_value }, 467 [GPIO_UVWX_DIRECTION] = { 5, gpio_reg_direction }, 468 [GPIO_UVWX_INT_ENABLE] = { 5, gpio_reg_int_enable }, 469 [GPIO_UVWX_INT_SENS_0] = { 5, gpio_reg_int_sens_0 }, 470 [GPIO_UVWX_INT_SENS_1] = { 5, gpio_reg_int_sens_1 }, 471 [GPIO_UVWX_INT_SENS_2] = { 5, gpio_reg_int_sens_2 }, 472 [GPIO_UVWX_INT_STATUS] = { 5, gpio_reg_int_status }, 473 [GPIO_UVWX_RESET_TOLERANT] = { 5, gpio_reg_reset_tolerant }, 474 [GPIO_UVWX_DEBOUNCE_1] = { 5, gpio_reg_debounce_1 }, 475 [GPIO_UVWX_DEBOUNCE_2] = { 5, gpio_reg_debounce_2 }, 476 [GPIO_UVWX_COMMAND_SRC_0] = { 5, gpio_reg_cmd_source_0 }, 477 [GPIO_UVWX_COMMAND_SRC_1] = { 5, gpio_reg_cmd_source_1 }, 478 [GPIO_UVWX_DATA_READ] = { 5, gpio_reg_data_read }, 479 [GPIO_UVWX_INPUT_MASK] = { 5, gpio_reg_input_mask }, 480 /* Set YZAAAB */ 481 [GPIO_YZAAAB_DATA_VALUE] = { 6, gpio_reg_data_value }, 482 [GPIO_YZAAAB_DIRECTION] = { 6, gpio_reg_direction }, 483 [GPIO_YZAAAB_INT_ENABLE] = { 6, gpio_reg_int_enable }, 484 [GPIO_YZAAAB_INT_SENS_0] = { 6, gpio_reg_int_sens_0 }, 485 [GPIO_YZAAAB_INT_SENS_1] = { 6, gpio_reg_int_sens_1 }, 486 [GPIO_YZAAAB_INT_SENS_2] = { 6, gpio_reg_int_sens_2 }, 487 [GPIO_YZAAAB_INT_STATUS] = { 6, gpio_reg_int_status }, 488 [GPIO_YZAAAB_RESET_TOLERANT] = { 6, gpio_reg_reset_tolerant }, 489 [GPIO_YZAAAB_DEBOUNCE_1] = { 6, gpio_reg_debounce_1 }, 490 [GPIO_YZAAAB_DEBOUNCE_2] = { 6, gpio_reg_debounce_2 }, 491 [GPIO_YZAAAB_COMMAND_SRC_0] = { 6, gpio_reg_cmd_source_0 }, 492 [GPIO_YZAAAB_COMMAND_SRC_1] = { 6, gpio_reg_cmd_source_1 }, 493 [GPIO_YZAAAB_DATA_READ] = { 6, gpio_reg_data_read }, 494 [GPIO_YZAAAB_INPUT_MASK] = { 6, gpio_reg_input_mask }, 495 /* Set AC (ast2500 only) */ 496 [GPIO_AC_DATA_VALUE] = { 7, gpio_reg_data_value }, 497 [GPIO_AC_DIRECTION] = { 7, gpio_reg_direction }, 498 [GPIO_AC_INT_ENABLE] = { 7, gpio_reg_int_enable }, 499 [GPIO_AC_INT_SENS_0] = { 7, gpio_reg_int_sens_0 }, 500 [GPIO_AC_INT_SENS_1] = { 7, gpio_reg_int_sens_1 }, 501 [GPIO_AC_INT_SENS_2] = { 7, gpio_reg_int_sens_2 }, 502 [GPIO_AC_INT_STATUS] = { 7, gpio_reg_int_status }, 503 [GPIO_AC_RESET_TOLERANT] = { 7, gpio_reg_reset_tolerant }, 504 [GPIO_AC_DEBOUNCE_1] = { 7, gpio_reg_debounce_1 }, 505 [GPIO_AC_DEBOUNCE_2] = { 7, gpio_reg_debounce_2 }, 506 [GPIO_AC_COMMAND_SRC_0] = { 7, gpio_reg_cmd_source_0 }, 507 [GPIO_AC_COMMAND_SRC_1] = { 7, gpio_reg_cmd_source_1 }, 508 [GPIO_AC_DATA_READ] = { 7, gpio_reg_data_read }, 509 [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask }, 510 }; 511 512 static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = { 513 /* 1.8V Set ABCD */ 514 [GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value}, 515 [GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction}, 516 [GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable}, 517 [GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0}, 518 [GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1}, 519 [GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2}, 520 [GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status}, 521 [GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant}, 522 [GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1}, 523 [GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2}, 524 [GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0}, 525 [GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1}, 526 [GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read}, 527 [GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask}, 528 /* 1.8V Set E */ 529 [GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value}, 530 [GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction}, 531 [GPIO_1_8V_E_INT_ENABLE] = {1, gpio_reg_int_enable}, 532 [GPIO_1_8V_E_INT_SENS_0] = {1, gpio_reg_int_sens_0}, 533 [GPIO_1_8V_E_INT_SENS_1] = {1, gpio_reg_int_sens_1}, 534 [GPIO_1_8V_E_INT_SENS_2] = {1, gpio_reg_int_sens_2}, 535 [GPIO_1_8V_E_INT_STATUS] = {1, gpio_reg_int_status}, 536 [GPIO_1_8V_E_RESET_TOLERANT] = {1, gpio_reg_reset_tolerant}, 537 [GPIO_1_8V_E_DEBOUNCE_1] = {1, gpio_reg_debounce_1}, 538 [GPIO_1_8V_E_DEBOUNCE_2] = {1, gpio_reg_debounce_2}, 539 [GPIO_1_8V_E_COMMAND_SRC_0] = {1, gpio_reg_cmd_source_0}, 540 [GPIO_1_8V_E_COMMAND_SRC_1] = {1, gpio_reg_cmd_source_1}, 541 [GPIO_1_8V_E_DATA_READ] = {1, gpio_reg_data_read}, 542 [GPIO_1_8V_E_INPUT_MASK] = {1, gpio_reg_input_mask}, 543 }; 544 545 static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) 546 { 547 AspeedGPIOState *s = ASPEED_GPIO(opaque); 548 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 549 uint64_t idx = -1; 550 const AspeedGPIOReg *reg; 551 GPIOSets *set; 552 uint32_t value = 0; 553 uint64_t debounce_value; 554 555 idx = offset >> 2; 556 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 557 idx -= GPIO_DEBOUNCE_TIME_1; 558 debounce_value = (uint64_t) s->debounce_regs[idx]; 559 trace_aspeed_gpio_read(offset, debounce_value); 560 return debounce_value; 561 } 562 563 if (idx >= agc->reg_table_count) { 564 qemu_log_mask(LOG_GUEST_ERROR, "%s: idx 0x%" PRIx64 " out of bounds\n", 565 __func__, idx); 566 return 0; 567 } 568 569 reg = &agc->reg_table[idx]; 570 if (reg->set_idx >= agc->nr_gpio_sets) { 571 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 572 PRIx64"\n", __func__, offset); 573 return 0; 574 } 575 576 set = &s->sets[reg->set_idx]; 577 switch (reg->type) { 578 case gpio_reg_data_value: 579 value = set->data_value; 580 break; 581 case gpio_reg_direction: 582 value = set->direction; 583 break; 584 case gpio_reg_int_enable: 585 value = set->int_enable; 586 break; 587 case gpio_reg_int_sens_0: 588 value = set->int_sens_0; 589 break; 590 case gpio_reg_int_sens_1: 591 value = set->int_sens_1; 592 break; 593 case gpio_reg_int_sens_2: 594 value = set->int_sens_2; 595 break; 596 case gpio_reg_int_status: 597 value = set->int_status; 598 break; 599 case gpio_reg_reset_tolerant: 600 value = set->reset_tol; 601 break; 602 case gpio_reg_debounce_1: 603 value = set->debounce_1; 604 break; 605 case gpio_reg_debounce_2: 606 value = set->debounce_2; 607 break; 608 case gpio_reg_cmd_source_0: 609 value = set->cmd_source_0; 610 break; 611 case gpio_reg_cmd_source_1: 612 value = set->cmd_source_1; 613 break; 614 case gpio_reg_data_read: 615 value = set->data_read; 616 break; 617 case gpio_reg_input_mask: 618 value = set->input_mask; 619 break; 620 default: 621 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 622 PRIx64"\n", __func__, offset); 623 return 0; 624 } 625 626 trace_aspeed_gpio_read(offset, value); 627 return value; 628 } 629 630 static void aspeed_gpio_write_index_mode(void *opaque, hwaddr offset, 631 uint64_t data, uint32_t size) 632 { 633 AspeedGPIOState *s = ASPEED_GPIO(opaque); 634 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 635 const GPIOSetProperties *props; 636 GPIOSets *set; 637 uint32_t reg_idx_number = FIELD_EX32(data, GPIO_INDEX_REG, NUMBER); 638 uint32_t reg_idx_type = FIELD_EX32(data, GPIO_INDEX_REG, TYPE); 639 uint32_t reg_idx_command = FIELD_EX32(data, GPIO_INDEX_REG, COMMAND); 640 uint32_t set_idx = reg_idx_number / ASPEED_GPIOS_PER_SET; 641 uint32_t pin_idx = reg_idx_number % ASPEED_GPIOS_PER_SET; 642 uint32_t group_idx = pin_idx / GPIOS_PER_GROUP; 643 uint32_t reg_value = 0; 644 uint32_t pending = 0; 645 646 set = &s->sets[set_idx]; 647 props = &agc->props[set_idx]; 648 649 if (reg_idx_command) 650 qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" 651 PRIx64 "index mode wrong command 0x%x\n", 652 __func__, offset, data, reg_idx_command); 653 654 switch (reg_idx_type) { 655 case gpio_reg_idx_data: 656 reg_value = set->data_read; 657 reg_value = deposit32(reg_value, pin_idx, 1, 658 FIELD_EX32(data, GPIO_INDEX_REG, DATA_VALUE)); 659 reg_value &= props->output; 660 reg_value = update_value_control_source(set, set->data_value, 661 reg_value); 662 set->data_read = reg_value; 663 aspeed_gpio_update(s, set, reg_value, set->direction); 664 return; 665 case gpio_reg_idx_direction: 666 reg_value = set->direction; 667 reg_value = deposit32(reg_value, pin_idx, 1, 668 FIELD_EX32(data, GPIO_INDEX_REG, DIRECTION)); 669 /* 670 * where data is the value attempted to be written to the pin: 671 * pin type | input mask | output mask | expected value 672 * ------------------------------------------------------------ 673 * bidirectional | 1 | 1 | data 674 * input only | 1 | 0 | 0 675 * output only | 0 | 1 | 1 676 * no pin | 0 | 0 | 0 677 * 678 * which is captured by: 679 * data = ( data | ~input) & output; 680 */ 681 reg_value = (reg_value | ~props->input) & props->output; 682 set->direction = update_value_control_source(set, set->direction, 683 reg_value); 684 break; 685 case gpio_reg_idx_interrupt: 686 reg_value = set->int_enable; 687 reg_value = deposit32(reg_value, pin_idx, 1, 688 FIELD_EX32(data, GPIO_INDEX_REG, INT_ENABLE)); 689 set->int_enable = update_value_control_source(set, set->int_enable, 690 reg_value); 691 reg_value = set->int_sens_0; 692 reg_value = deposit32(reg_value, pin_idx, 1, 693 FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_0)); 694 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, 695 reg_value); 696 reg_value = set->int_sens_1; 697 reg_value = deposit32(reg_value, pin_idx, 1, 698 FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_1)); 699 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, 700 reg_value); 701 reg_value = set->int_sens_2; 702 reg_value = deposit32(reg_value, pin_idx, 1, 703 FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_2)); 704 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, 705 reg_value); 706 /* interrupt status */ 707 if (FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)) { 708 /* pending is either 1 or 0 for a 1-bit field */ 709 pending = extract32(set->int_status, pin_idx, 1); 710 711 assert(s->pending >= pending); 712 713 /* No change to s->pending if pending is 0 */ 714 s->pending -= pending; 715 716 /* 717 * The write acknowledged the interrupt regardless of whether it 718 * was pending or not. The post-condition is that it mustn't be 719 * pending. Unconditionally clear the status bit. 720 */ 721 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); 722 } 723 break; 724 case gpio_reg_idx_debounce: 725 reg_value = set->debounce_1; 726 reg_value = deposit32(reg_value, pin_idx, 1, 727 FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_1)); 728 set->debounce_1 = update_value_control_source(set, set->debounce_1, 729 reg_value); 730 reg_value = set->debounce_2; 731 reg_value = deposit32(reg_value, pin_idx, 1, 732 FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_2)); 733 set->debounce_2 = update_value_control_source(set, set->debounce_2, 734 reg_value); 735 return; 736 case gpio_reg_idx_tolerance: 737 reg_value = set->reset_tol; 738 reg_value = deposit32(reg_value, pin_idx, 1, 739 FIELD_EX32(data, GPIO_INDEX_REG, RESET_TOLERANT)); 740 set->reset_tol = update_value_control_source(set, set->reset_tol, 741 reg_value); 742 return; 743 case gpio_reg_idx_cmd_src: 744 reg_value = set->cmd_source_0; 745 reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1, 746 FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC_0)); 747 set->cmd_source_0 = reg_value & ASPEED_CMD_SRC_MASK; 748 reg_value = set->cmd_source_1; 749 reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1, 750 FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC_1)); 751 set->cmd_source_1 = reg_value & ASPEED_CMD_SRC_MASK; 752 return; 753 case gpio_reg_idx_input_mask: 754 reg_value = set->input_mask; 755 reg_value = deposit32(reg_value, pin_idx, 1, 756 FIELD_EX32(data, GPIO_INDEX_REG, INPUT_MASK)); 757 /* 758 * feeds into interrupt generation 759 * 0: read from data value reg will be updated 760 * 1: read from data value reg will not be updated 761 */ 762 set->input_mask = reg_value & props->input; 763 break; 764 default: 765 qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" 766 PRIx64 "index mode wrong type 0x%x\n", 767 __func__, offset, data, reg_idx_type); 768 return; 769 } 770 aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); 771 return; 772 } 773 774 static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, 775 uint32_t size) 776 { 777 AspeedGPIOState *s = ASPEED_GPIO(opaque); 778 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 779 const GPIOSetProperties *props; 780 uint64_t idx = -1; 781 const AspeedGPIOReg *reg; 782 GPIOSets *set; 783 uint32_t cleared; 784 785 trace_aspeed_gpio_write(offset, data); 786 787 idx = offset >> 2; 788 789 /* check gpio index mode */ 790 if (idx == R_GPIO_INDEX_REG) { 791 aspeed_gpio_write_index_mode(opaque, offset, data, size); 792 return; 793 } 794 795 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 796 idx -= GPIO_DEBOUNCE_TIME_1; 797 s->debounce_regs[idx] = (uint32_t) data; 798 return; 799 } 800 801 if (idx >= agc->reg_table_count) { 802 qemu_log_mask(LOG_GUEST_ERROR, "%s: idx 0x%" PRIx64 " out of bounds\n", 803 __func__, idx); 804 return; 805 } 806 807 reg = &agc->reg_table[idx]; 808 if (reg->set_idx >= agc->nr_gpio_sets) { 809 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 810 PRIx64"\n", __func__, offset); 811 return; 812 } 813 814 set = &s->sets[reg->set_idx]; 815 props = &agc->props[reg->set_idx]; 816 817 switch (reg->type) { 818 case gpio_reg_data_value: 819 data &= props->output; 820 data = update_value_control_source(set, set->data_value, data); 821 set->data_read = data; 822 aspeed_gpio_update(s, set, data, set->direction); 823 return; 824 case gpio_reg_direction: 825 /* 826 * where data is the value attempted to be written to the pin: 827 * pin type | input mask | output mask | expected value 828 * ------------------------------------------------------------ 829 * bidirectional | 1 | 1 | data 830 * input only | 1 | 0 | 0 831 * output only | 0 | 1 | 1 832 * no pin | 0 | 0 | 0 833 * 834 * which is captured by: 835 * data = ( data | ~input) & output; 836 */ 837 data = (data | ~props->input) & props->output; 838 set->direction = update_value_control_source(set, set->direction, data); 839 break; 840 case gpio_reg_int_enable: 841 set->int_enable = update_value_control_source(set, set->int_enable, 842 data); 843 break; 844 case gpio_reg_int_sens_0: 845 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, 846 data); 847 break; 848 case gpio_reg_int_sens_1: 849 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, 850 data); 851 break; 852 case gpio_reg_int_sens_2: 853 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, 854 data); 855 break; 856 case gpio_reg_int_status: 857 cleared = ctpop32(data & set->int_status); 858 if (s->pending && cleared) { 859 assert(s->pending >= cleared); 860 s->pending -= cleared; 861 } 862 set->int_status &= ~data; 863 break; 864 case gpio_reg_reset_tolerant: 865 set->reset_tol = update_value_control_source(set, set->reset_tol, 866 data); 867 return; 868 case gpio_reg_debounce_1: 869 set->debounce_1 = update_value_control_source(set, set->debounce_1, 870 data); 871 return; 872 case gpio_reg_debounce_2: 873 set->debounce_2 = update_value_control_source(set, set->debounce_2, 874 data); 875 return; 876 case gpio_reg_cmd_source_0: 877 set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK; 878 return; 879 case gpio_reg_cmd_source_1: 880 set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK; 881 return; 882 case gpio_reg_data_read: 883 /* Read only register */ 884 return; 885 case gpio_reg_input_mask: 886 /* 887 * feeds into interrupt generation 888 * 0: read from data value reg will be updated 889 * 1: read from data value reg will not be updated 890 */ 891 set->input_mask = data & props->input; 892 break; 893 default: 894 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 895 PRIx64"\n", __func__, offset); 896 return; 897 } 898 aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); 899 return; 900 } 901 902 static int get_set_idx(AspeedGPIOState *s, const char *group, int *group_idx) 903 { 904 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 905 int set_idx, g_idx; 906 907 for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) { 908 const GPIOSetProperties *set_props = &agc->props[set_idx]; 909 for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) { 910 if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) { 911 *group_idx = g_idx; 912 return set_idx; 913 } 914 } 915 } 916 return -1; 917 } 918 919 static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name, 920 void *opaque, Error **errp) 921 { 922 int pin = 0xfff; 923 bool level = true; 924 char group[4]; 925 AspeedGPIOState *s = ASPEED_GPIO(obj); 926 int set_idx, group_idx = 0; 927 928 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 929 /* 1.8V gpio */ 930 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 931 error_setg(errp, "%s: error reading %s", __func__, name); 932 return; 933 } 934 } 935 set_idx = get_set_idx(s, group, &group_idx); 936 if (set_idx == -1) { 937 error_setg(errp, "%s: invalid group %s", __func__, group); 938 return; 939 } 940 pin = pin + group_idx * GPIOS_PER_GROUP; 941 level = aspeed_gpio_get_pin_level(s, set_idx, pin); 942 visit_type_bool(v, name, &level, errp); 943 } 944 945 static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, 946 void *opaque, Error **errp) 947 { 948 bool level; 949 int pin = 0xfff; 950 char group[4]; 951 AspeedGPIOState *s = ASPEED_GPIO(obj); 952 int set_idx, group_idx = 0; 953 954 if (!visit_type_bool(v, name, &level, errp)) { 955 return; 956 } 957 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 958 /* 1.8V gpio */ 959 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 960 error_setg(errp, "%s: error reading %s", __func__, name); 961 return; 962 } 963 } 964 set_idx = get_set_idx(s, group, &group_idx); 965 if (set_idx == -1) { 966 error_setg(errp, "%s: invalid group %s", __func__, group); 967 return; 968 } 969 pin = pin + group_idx * GPIOS_PER_GROUP; 970 aspeed_gpio_set_pin_level(s, set_idx, pin, level); 971 } 972 973 /* Setup functions */ 974 static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 975 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 976 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 977 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 978 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 979 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 980 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 981 [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, 982 }; 983 984 static const GPIOSetProperties ast2500_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 985 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 986 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 987 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 988 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 989 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 990 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 991 [6] = {0x0fffffff, 0x0fffffff, {"Y", "Z", "AA", "AB"} }, 992 [7] = {0x000000ff, 0x000000ff, {"AC"} }, 993 }; 994 995 static GPIOSetProperties ast2600_3_3v_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 996 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 997 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 998 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 999 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 1000 [4] = {0xffffffff, 0x00ffffff, {"Q", "R", "S", "T"} }, 1001 [5] = {0xffffffff, 0xffffff00, {"U", "V", "W", "X"} }, 1002 [6] = {0x0000ffff, 0x0000ffff, {"Y", "Z"} }, 1003 }; 1004 1005 static GPIOSetProperties ast2600_1_8v_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 1006 [0] = {0xffffffff, 0xffffffff, {"18A", "18B", "18C", "18D"} }, 1007 [1] = {0x0000000f, 0x0000000f, {"18E"} }, 1008 }; 1009 1010 static GPIOSetProperties ast1030_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 1011 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 1012 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 1013 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 1014 [3] = {0xffffff3f, 0xffffff3f, {"M", "N", "O", "P"} }, 1015 [4] = {0xff060c1f, 0x00060c1f, {"Q", "R", "S", "T"} }, 1016 [5] = {0x000000ff, 0x00000000, {"U"} }, 1017 }; 1018 1019 static const MemoryRegionOps aspeed_gpio_ops = { 1020 .read = aspeed_gpio_read, 1021 .write = aspeed_gpio_write, 1022 .endianness = DEVICE_LITTLE_ENDIAN, 1023 .valid.min_access_size = 4, 1024 .valid.max_access_size = 4, 1025 }; 1026 1027 static void aspeed_gpio_reset(DeviceState *dev) 1028 { 1029 AspeedGPIOState *s = ASPEED_GPIO(dev); 1030 1031 /* TODO: respect the reset tolerance registers */ 1032 memset(s->sets, 0, sizeof(s->sets)); 1033 } 1034 1035 static void aspeed_gpio_realize(DeviceState *dev, Error **errp) 1036 { 1037 AspeedGPIOState *s = ASPEED_GPIO(dev); 1038 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1039 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 1040 1041 /* Interrupt parent line */ 1042 sysbus_init_irq(sbd, &s->irq); 1043 1044 /* Individual GPIOs */ 1045 for (int i = 0; i < ASPEED_GPIO_MAX_NR_SETS; i++) { 1046 const GPIOSetProperties *props = &agc->props[i]; 1047 uint32_t skip = ~(props->input | props->output); 1048 for (int j = 0; j < ASPEED_GPIOS_PER_SET; j++) { 1049 if (skip >> j & 1) { 1050 continue; 1051 } 1052 sysbus_init_irq(sbd, &s->gpios[i][j]); 1053 } 1054 } 1055 1056 memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s, 1057 TYPE_ASPEED_GPIO, agc->mem_size); 1058 1059 sysbus_init_mmio(sbd, &s->iomem); 1060 } 1061 1062 static void aspeed_gpio_init(Object *obj) 1063 { 1064 AspeedGPIOState *s = ASPEED_GPIO(obj); 1065 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 1066 1067 for (int i = 0; i < ASPEED_GPIO_MAX_NR_SETS; i++) { 1068 const GPIOSetProperties *props = &agc->props[i]; 1069 uint32_t skip = ~(props->input | props->output); 1070 for (int j = 0; j < ASPEED_GPIOS_PER_SET; j++) { 1071 if (skip >> j & 1) { 1072 continue; 1073 } 1074 int group_idx = j / GPIOS_PER_GROUP; 1075 int pin_idx = j % GPIOS_PER_GROUP; 1076 const char *group = &props->group_label[group_idx][0]; 1077 char *name = g_strdup_printf("gpio%s%d", group, pin_idx); 1078 object_property_add(obj, name, "bool", aspeed_gpio_get_pin, 1079 aspeed_gpio_set_pin, NULL, NULL); 1080 g_free(name); 1081 } 1082 } 1083 } 1084 1085 static const VMStateDescription vmstate_gpio_regs = { 1086 .name = TYPE_ASPEED_GPIO"/regs", 1087 .version_id = 1, 1088 .minimum_version_id = 1, 1089 .fields = (const VMStateField[]) { 1090 VMSTATE_UINT32(data_value, GPIOSets), 1091 VMSTATE_UINT32(data_read, GPIOSets), 1092 VMSTATE_UINT32(direction, GPIOSets), 1093 VMSTATE_UINT32(int_enable, GPIOSets), 1094 VMSTATE_UINT32(int_sens_0, GPIOSets), 1095 VMSTATE_UINT32(int_sens_1, GPIOSets), 1096 VMSTATE_UINT32(int_sens_2, GPIOSets), 1097 VMSTATE_UINT32(int_status, GPIOSets), 1098 VMSTATE_UINT32(reset_tol, GPIOSets), 1099 VMSTATE_UINT32(cmd_source_0, GPIOSets), 1100 VMSTATE_UINT32(cmd_source_1, GPIOSets), 1101 VMSTATE_UINT32(debounce_1, GPIOSets), 1102 VMSTATE_UINT32(debounce_2, GPIOSets), 1103 VMSTATE_UINT32(input_mask, GPIOSets), 1104 VMSTATE_END_OF_LIST(), 1105 } 1106 }; 1107 1108 static const VMStateDescription vmstate_aspeed_gpio = { 1109 .name = TYPE_ASPEED_GPIO, 1110 .version_id = 1, 1111 .minimum_version_id = 1, 1112 .fields = (const VMStateField[]) { 1113 VMSTATE_STRUCT_ARRAY(sets, AspeedGPIOState, ASPEED_GPIO_MAX_NR_SETS, 1114 1, vmstate_gpio_regs, GPIOSets), 1115 VMSTATE_UINT32_ARRAY(debounce_regs, AspeedGPIOState, 1116 ASPEED_GPIO_NR_DEBOUNCE_REGS), 1117 VMSTATE_END_OF_LIST(), 1118 } 1119 }; 1120 1121 static void aspeed_gpio_class_init(ObjectClass *klass, void *data) 1122 { 1123 DeviceClass *dc = DEVICE_CLASS(klass); 1124 1125 dc->realize = aspeed_gpio_realize; 1126 device_class_set_legacy_reset(dc, aspeed_gpio_reset); 1127 dc->desc = "Aspeed GPIO Controller"; 1128 dc->vmsd = &vmstate_aspeed_gpio; 1129 } 1130 1131 static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) 1132 { 1133 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1134 1135 agc->props = ast2400_set_props; 1136 agc->nr_gpio_pins = 216; 1137 agc->nr_gpio_sets = 7; 1138 agc->reg_table = aspeed_3_3v_gpios; 1139 agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; 1140 agc->mem_size = 0x1000; 1141 agc->reg_ops = &aspeed_gpio_ops; 1142 } 1143 1144 static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) 1145 { 1146 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1147 1148 agc->props = ast2500_set_props; 1149 agc->nr_gpio_pins = 228; 1150 agc->nr_gpio_sets = 8; 1151 agc->reg_table = aspeed_3_3v_gpios; 1152 agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; 1153 agc->mem_size = 0x1000; 1154 agc->reg_ops = &aspeed_gpio_ops; 1155 } 1156 1157 static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) 1158 { 1159 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1160 1161 agc->props = ast2600_3_3v_set_props; 1162 agc->nr_gpio_pins = 208; 1163 agc->nr_gpio_sets = 7; 1164 agc->reg_table = aspeed_3_3v_gpios; 1165 agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; 1166 agc->mem_size = 0x800; 1167 agc->reg_ops = &aspeed_gpio_ops; 1168 } 1169 1170 static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) 1171 { 1172 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1173 1174 agc->props = ast2600_1_8v_set_props; 1175 agc->nr_gpio_pins = 36; 1176 agc->nr_gpio_sets = 2; 1177 agc->reg_table = aspeed_1_8v_gpios; 1178 agc->reg_table_count = GPIO_1_8V_REG_ARRAY_SIZE; 1179 agc->mem_size = 0x800; 1180 agc->reg_ops = &aspeed_gpio_ops; 1181 } 1182 1183 static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) 1184 { 1185 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 1186 1187 agc->props = ast1030_set_props; 1188 agc->nr_gpio_pins = 151; 1189 agc->nr_gpio_sets = 6; 1190 agc->reg_table = aspeed_3_3v_gpios; 1191 agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; 1192 agc->mem_size = 0x1000; 1193 agc->reg_ops = &aspeed_gpio_ops; 1194 } 1195 1196 static const TypeInfo aspeed_gpio_info = { 1197 .name = TYPE_ASPEED_GPIO, 1198 .parent = TYPE_SYS_BUS_DEVICE, 1199 .instance_size = sizeof(AspeedGPIOState), 1200 .class_size = sizeof(AspeedGPIOClass), 1201 .class_init = aspeed_gpio_class_init, 1202 .abstract = true, 1203 }; 1204 1205 static const TypeInfo aspeed_gpio_ast2400_info = { 1206 .name = TYPE_ASPEED_GPIO "-ast2400", 1207 .parent = TYPE_ASPEED_GPIO, 1208 .class_init = aspeed_gpio_ast2400_class_init, 1209 .instance_init = aspeed_gpio_init, 1210 }; 1211 1212 static const TypeInfo aspeed_gpio_ast2500_info = { 1213 .name = TYPE_ASPEED_GPIO "-ast2500", 1214 .parent = TYPE_ASPEED_GPIO, 1215 .class_init = aspeed_gpio_2500_class_init, 1216 .instance_init = aspeed_gpio_init, 1217 }; 1218 1219 static const TypeInfo aspeed_gpio_ast2600_3_3v_info = { 1220 .name = TYPE_ASPEED_GPIO "-ast2600", 1221 .parent = TYPE_ASPEED_GPIO, 1222 .class_init = aspeed_gpio_ast2600_3_3v_class_init, 1223 .instance_init = aspeed_gpio_init, 1224 }; 1225 1226 static const TypeInfo aspeed_gpio_ast2600_1_8v_info = { 1227 .name = TYPE_ASPEED_GPIO "-ast2600-1_8v", 1228 .parent = TYPE_ASPEED_GPIO, 1229 .class_init = aspeed_gpio_ast2600_1_8v_class_init, 1230 .instance_init = aspeed_gpio_init, 1231 }; 1232 1233 static const TypeInfo aspeed_gpio_ast1030_info = { 1234 .name = TYPE_ASPEED_GPIO "-ast1030", 1235 .parent = TYPE_ASPEED_GPIO, 1236 .class_init = aspeed_gpio_1030_class_init, 1237 .instance_init = aspeed_gpio_init, 1238 }; 1239 1240 static void aspeed_gpio_register_types(void) 1241 { 1242 type_register_static(&aspeed_gpio_info); 1243 type_register_static(&aspeed_gpio_ast2400_info); 1244 type_register_static(&aspeed_gpio_ast2500_info); 1245 type_register_static(&aspeed_gpio_ast2600_3_3v_info); 1246 type_register_static(&aspeed_gpio_ast2600_1_8v_info); 1247 type_register_static(&aspeed_gpio_ast1030_info); 1248 } 1249 1250 type_init(aspeed_gpio_register_types); 1251