1 /* 2 * ASPEED GPIO Controller 3 * 4 * Copyright (C) 2017-2019 IBM Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/host-utils.h" 11 #include "qemu/log.h" 12 #include "hw/gpio/aspeed_gpio.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "qapi/error.h" 15 #include "qapi/visitor.h" 16 #include "hw/irq.h" 17 #include "migration/vmstate.h" 18 #include "trace.h" 19 20 #define GPIOS_PER_GROUP 8 21 22 /* GPIO Source Types */ 23 #define ASPEED_CMD_SRC_MASK 0x01010101 24 #define ASPEED_SOURCE_ARM 0 25 #define ASPEED_SOURCE_LPC 1 26 #define ASPEED_SOURCE_COPROCESSOR 2 27 #define ASPEED_SOURCE_RESERVED 3 28 29 /* GPIO Interrupt Triggers */ 30 /* 31 * For each set of gpios there are three sensitivity registers that control 32 * the interrupt trigger mode. 33 * 34 * | 2 | 1 | 0 | trigger mode 35 * ----------------------------- 36 * | 0 | 0 | 0 | falling-edge 37 * | 0 | 0 | 1 | rising-edge 38 * | 0 | 1 | 0 | level-low 39 * | 0 | 1 | 1 | level-high 40 * | 1 | X | X | dual-edge 41 */ 42 #define ASPEED_FALLING_EDGE 0 43 #define ASPEED_RISING_EDGE 1 44 #define ASPEED_LEVEL_LOW 2 45 #define ASPEED_LEVEL_HIGH 3 46 #define ASPEED_DUAL_EDGE 4 47 48 /* GPIO Register Address Offsets */ 49 #define GPIO_ABCD_DATA_VALUE (0x000 >> 2) 50 #define GPIO_ABCD_DIRECTION (0x004 >> 2) 51 #define GPIO_ABCD_INT_ENABLE (0x008 >> 2) 52 #define GPIO_ABCD_INT_SENS_0 (0x00C >> 2) 53 #define GPIO_ABCD_INT_SENS_1 (0x010 >> 2) 54 #define GPIO_ABCD_INT_SENS_2 (0x014 >> 2) 55 #define GPIO_ABCD_INT_STATUS (0x018 >> 2) 56 #define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2) 57 #define GPIO_EFGH_DATA_VALUE (0x020 >> 2) 58 #define GPIO_EFGH_DIRECTION (0x024 >> 2) 59 #define GPIO_EFGH_INT_ENABLE (0x028 >> 2) 60 #define GPIO_EFGH_INT_SENS_0 (0x02C >> 2) 61 #define GPIO_EFGH_INT_SENS_1 (0x030 >> 2) 62 #define GPIO_EFGH_INT_SENS_2 (0x034 >> 2) 63 #define GPIO_EFGH_INT_STATUS (0x038 >> 2) 64 #define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2) 65 #define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2) 66 #define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2) 67 #define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2) 68 #define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2) 69 #define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2) 70 #define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2) 71 #define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2) 72 #define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2) 73 #define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2) 74 #define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2) 75 #define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2) 76 #define GPIO_IJKL_DATA_VALUE (0x070 >> 2) 77 #define GPIO_IJKL_DIRECTION (0x074 >> 2) 78 #define GPIO_MNOP_DATA_VALUE (0x078 >> 2) 79 #define GPIO_MNOP_DIRECTION (0x07C >> 2) 80 #define GPIO_QRST_DATA_VALUE (0x080 >> 2) 81 #define GPIO_QRST_DIRECTION (0x084 >> 2) 82 #define GPIO_UVWX_DATA_VALUE (0x088 >> 2) 83 #define GPIO_UVWX_DIRECTION (0x08C >> 2) 84 #define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2) 85 #define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2) 86 #define GPIO_IJKL_INT_ENABLE (0x098 >> 2) 87 #define GPIO_IJKL_INT_SENS_0 (0x09C >> 2) 88 #define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2) 89 #define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2) 90 #define GPIO_IJKL_INT_STATUS (0x0A8 >> 2) 91 #define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2) 92 #define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2) 93 #define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2) 94 #define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2) 95 #define GPIO_ABCD_DATA_READ (0x0C0 >> 2) 96 #define GPIO_EFGH_DATA_READ (0x0C4 >> 2) 97 #define GPIO_IJKL_DATA_READ (0x0C8 >> 2) 98 #define GPIO_MNOP_DATA_READ (0x0CC >> 2) 99 #define GPIO_QRST_DATA_READ (0x0D0 >> 2) 100 #define GPIO_UVWX_DATA_READ (0x0D4 >> 2) 101 #define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2) 102 #define GPIO_AC_DATA_READ (0x0DC >> 2) 103 #define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2) 104 #define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2) 105 #define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2) 106 #define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2) 107 #define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2) 108 #define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2) 109 #define GPIO_MNOP_INT_STATUS (0x0F8 >> 2) 110 #define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2) 111 #define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2) 112 #define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2) 113 #define GPIO_MNOP_INPUT_MASK (0x108 >> 2) 114 #define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2) 115 #define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2) 116 #define GPIO_QRST_INT_ENABLE (0x118 >> 2) 117 #define GPIO_QRST_INT_SENS_0 (0x11C >> 2) 118 #define GPIO_QRST_INT_SENS_1 (0x120 >> 2) 119 #define GPIO_QRST_INT_SENS_2 (0x124 >> 2) 120 #define GPIO_QRST_INT_STATUS (0x128 >> 2) 121 #define GPIO_QRST_RESET_TOLERANT (0x12C >> 2) 122 #define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2) 123 #define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2) 124 #define GPIO_QRST_INPUT_MASK (0x138 >> 2) 125 #define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2) 126 #define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2) 127 #define GPIO_UVWX_INT_ENABLE (0x148 >> 2) 128 #define GPIO_UVWX_INT_SENS_0 (0x14C >> 2) 129 #define GPIO_UVWX_INT_SENS_1 (0x150 >> 2) 130 #define GPIO_UVWX_INT_SENS_2 (0x154 >> 2) 131 #define GPIO_UVWX_INT_STATUS (0x158 >> 2) 132 #define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2) 133 #define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2) 134 #define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2) 135 #define GPIO_UVWX_INPUT_MASK (0x168 >> 2) 136 #define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2) 137 #define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2) 138 #define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2) 139 #define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2) 140 #define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2) 141 #define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2) 142 #define GPIO_YZAAAB_INT_STATUS (0x188 >> 2) 143 #define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2) 144 #define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2) 145 #define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2) 146 #define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2) 147 #define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2) 148 #define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2) 149 #define GPIO_AC_INT_ENABLE (0x1A8 >> 2) 150 #define GPIO_AC_INT_SENS_0 (0x1AC >> 2) 151 #define GPIO_AC_INT_SENS_1 (0x1B0 >> 2) 152 #define GPIO_AC_INT_SENS_2 (0x1B4 >> 2) 153 #define GPIO_AC_INT_STATUS (0x1B8 >> 2) 154 #define GPIO_AC_RESET_TOLERANT (0x1BC >> 2) 155 #define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2) 156 #define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2) 157 #define GPIO_AC_INPUT_MASK (0x1C8 >> 2) 158 #define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2) 159 #define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2) 160 #define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2) 161 #define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2) 162 #define GPIO_AC_DATA_VALUE (0x1E8 >> 2) 163 #define GPIO_AC_DIRECTION (0x1EC >> 2) 164 #define GPIO_3_3V_MEM_SIZE 0x1F0 165 #define GPIO_3_3V_REG_ARRAY_SIZE (GPIO_3_3V_MEM_SIZE >> 2) 166 167 /* AST2600 only - 1.8V gpios */ 168 /* 169 * The AST2600 two copies of the GPIO controller: the same 3.3V gpios as the 170 * AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios 171 * (memory offsets 0x800-0x9D4). 172 */ 173 #define GPIO_1_8V_ABCD_DATA_VALUE (0x000 >> 2) 174 #define GPIO_1_8V_ABCD_DIRECTION (0x004 >> 2) 175 #define GPIO_1_8V_ABCD_INT_ENABLE (0x008 >> 2) 176 #define GPIO_1_8V_ABCD_INT_SENS_0 (0x00C >> 2) 177 #define GPIO_1_8V_ABCD_INT_SENS_1 (0x010 >> 2) 178 #define GPIO_1_8V_ABCD_INT_SENS_2 (0x014 >> 2) 179 #define GPIO_1_8V_ABCD_INT_STATUS (0x018 >> 2) 180 #define GPIO_1_8V_ABCD_RESET_TOLERANT (0x01C >> 2) 181 #define GPIO_1_8V_E_DATA_VALUE (0x020 >> 2) 182 #define GPIO_1_8V_E_DIRECTION (0x024 >> 2) 183 #define GPIO_1_8V_E_INT_ENABLE (0x028 >> 2) 184 #define GPIO_1_8V_E_INT_SENS_0 (0x02C >> 2) 185 #define GPIO_1_8V_E_INT_SENS_1 (0x030 >> 2) 186 #define GPIO_1_8V_E_INT_SENS_2 (0x034 >> 2) 187 #define GPIO_1_8V_E_INT_STATUS (0x038 >> 2) 188 #define GPIO_1_8V_E_RESET_TOLERANT (0x03C >> 2) 189 #define GPIO_1_8V_ABCD_DEBOUNCE_1 (0x040 >> 2) 190 #define GPIO_1_8V_ABCD_DEBOUNCE_2 (0x044 >> 2) 191 #define GPIO_1_8V_E_DEBOUNCE_1 (0x048 >> 2) 192 #define GPIO_1_8V_E_DEBOUNCE_2 (0x04C >> 2) 193 #define GPIO_1_8V_DEBOUNCE_TIME_1 (0x050 >> 2) 194 #define GPIO_1_8V_DEBOUNCE_TIME_2 (0x054 >> 2) 195 #define GPIO_1_8V_DEBOUNCE_TIME_3 (0x058 >> 2) 196 #define GPIO_1_8V_ABCD_COMMAND_SRC_0 (0x060 >> 2) 197 #define GPIO_1_8V_ABCD_COMMAND_SRC_1 (0x064 >> 2) 198 #define GPIO_1_8V_E_COMMAND_SRC_0 (0x068 >> 2) 199 #define GPIO_1_8V_E_COMMAND_SRC_1 (0x06C >> 2) 200 #define GPIO_1_8V_ABCD_DATA_READ (0x0C0 >> 2) 201 #define GPIO_1_8V_E_DATA_READ (0x0C4 >> 2) 202 #define GPIO_1_8V_ABCD_INPUT_MASK (0x1D0 >> 2) 203 #define GPIO_1_8V_E_INPUT_MASK (0x1D4 >> 2) 204 #define GPIO_1_8V_MEM_SIZE 0x1D8 205 #define GPIO_1_8V_REG_ARRAY_SIZE (GPIO_1_8V_MEM_SIZE >> 2) 206 207 static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) 208 { 209 uint32_t falling_edge = 0, rising_edge = 0; 210 uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1) 211 | extract32(regs->int_sens_1, gpio, 1) << 1 212 | extract32(regs->int_sens_2, gpio, 1) << 2; 213 uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1); 214 uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1); 215 216 if (!gpio_int_enabled) { 217 return 0; 218 } 219 220 /* Detect edges */ 221 if (gpio_curr_high && !gpio_prev_high) { 222 rising_edge = 1; 223 } else if (!gpio_curr_high && gpio_prev_high) { 224 falling_edge = 1; 225 } 226 227 if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) || 228 ((int_trigger == ASPEED_RISING_EDGE) && rising_edge) || 229 ((int_trigger == ASPEED_LEVEL_LOW) && !gpio_curr_high) || 230 ((int_trigger == ASPEED_LEVEL_HIGH) && gpio_curr_high) || 231 ((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge))) 232 { 233 regs->int_status = deposit32(regs->int_status, gpio, 1, 1); 234 return 1; 235 } 236 return 0; 237 } 238 239 #define nested_struct_index(ta, pa, m, tb, pb) \ 240 (pb - ((tb *)(((char *)pa) + offsetof(ta, m)))) 241 242 static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s, GPIOSets *regs) 243 { 244 return nested_struct_index(AspeedGPIOState, s, sets, GPIOSets, regs); 245 } 246 247 static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs, 248 uint32_t value) 249 { 250 uint32_t input_mask = regs->input_mask; 251 uint32_t direction = regs->direction; 252 uint32_t old = regs->data_value; 253 uint32_t new = value; 254 uint32_t diff; 255 int gpio; 256 257 diff = old ^ new; 258 if (diff) { 259 for (gpio = 0; gpio < ASPEED_GPIOS_PER_SET; gpio++) { 260 uint32_t mask = 1 << gpio; 261 262 /* If the gpio needs to be updated... */ 263 if (!(diff & mask)) { 264 continue; 265 } 266 267 /* ...and we're output or not input-masked... */ 268 if (!(direction & mask) && (input_mask & mask)) { 269 continue; 270 } 271 272 /* ...then update the state. */ 273 if (mask & new) { 274 regs->data_value |= mask; 275 } else { 276 regs->data_value &= ~mask; 277 } 278 279 /* If the gpio is set to output... */ 280 if (direction & mask) { 281 /* ...trigger the line-state IRQ */ 282 ptrdiff_t set = aspeed_gpio_set_idx(s, regs); 283 qemu_set_irq(s->gpios[set][gpio], !!(new & mask)); 284 } else { 285 /* ...otherwise if we meet the line's current IRQ policy... */ 286 if (aspeed_evaluate_irq(regs, old & mask, gpio)) { 287 /* ...trigger the VIC IRQ */ 288 s->pending++; 289 } 290 } 291 } 292 } 293 qemu_set_irq(s->irq, !!(s->pending)); 294 } 295 296 static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx, 297 uint32_t pin) 298 { 299 uint32_t reg_val; 300 uint32_t pin_mask = 1 << pin; 301 302 reg_val = s->sets[set_idx].data_value; 303 304 return !!(reg_val & pin_mask); 305 } 306 307 static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx, 308 uint32_t pin, bool level) 309 { 310 uint32_t value = s->sets[set_idx].data_value; 311 uint32_t pin_mask = 1 << pin; 312 313 if (level) { 314 value |= pin_mask; 315 } else { 316 value &= ~pin_mask; 317 } 318 319 aspeed_gpio_update(s, &s->sets[set_idx], value); 320 } 321 322 /* 323 * | src_1 | src_2 | source | 324 * |-----------------------------| 325 * | 0 | 0 | ARM | 326 * | 0 | 1 | LPC | 327 * | 1 | 0 | Coprocessor| 328 * | 1 | 1 | Reserved | 329 * 330 * Once the source of a set is programmed, corresponding bits in the 331 * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and 332 * debounce registers can only be written by the source. 333 * 334 * Source is ARM by default 335 * only bits 24, 16, 8, and 0 can be set 336 * 337 * we don't currently have a model for the LPC or Coprocessor 338 */ 339 static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value, 340 uint32_t value) 341 { 342 int i; 343 int cmd_source; 344 345 /* assume the source is always ARM for now */ 346 int source = ASPEED_SOURCE_ARM; 347 348 uint32_t new_value = 0; 349 350 /* for each group in set */ 351 for (i = 0; i < ASPEED_GPIOS_PER_SET; i += GPIOS_PER_GROUP) { 352 cmd_source = extract32(regs->cmd_source_0, i, 1) 353 | (extract32(regs->cmd_source_1, i, 1) << 1); 354 355 if (source == cmd_source) { 356 new_value |= (0xff << i) & value; 357 } else { 358 new_value |= (0xff << i) & old_value; 359 } 360 } 361 return new_value; 362 } 363 364 static const AspeedGPIOReg aspeed_3_3v_gpios[GPIO_3_3V_REG_ARRAY_SIZE] = { 365 /* Set ABCD */ 366 [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value }, 367 [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction }, 368 [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable }, 369 [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 }, 370 [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 }, 371 [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 }, 372 [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status }, 373 [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant }, 374 [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 }, 375 [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 }, 376 [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 }, 377 [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 }, 378 [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read }, 379 [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask }, 380 /* Set EFGH */ 381 [GPIO_EFGH_DATA_VALUE] = { 1, gpio_reg_data_value }, 382 [GPIO_EFGH_DIRECTION] = { 1, gpio_reg_direction }, 383 [GPIO_EFGH_INT_ENABLE] = { 1, gpio_reg_int_enable }, 384 [GPIO_EFGH_INT_SENS_0] = { 1, gpio_reg_int_sens_0 }, 385 [GPIO_EFGH_INT_SENS_1] = { 1, gpio_reg_int_sens_1 }, 386 [GPIO_EFGH_INT_SENS_2] = { 1, gpio_reg_int_sens_2 }, 387 [GPIO_EFGH_INT_STATUS] = { 1, gpio_reg_int_status }, 388 [GPIO_EFGH_RESET_TOLERANT] = { 1, gpio_reg_reset_tolerant }, 389 [GPIO_EFGH_DEBOUNCE_1] = { 1, gpio_reg_debounce_1 }, 390 [GPIO_EFGH_DEBOUNCE_2] = { 1, gpio_reg_debounce_2 }, 391 [GPIO_EFGH_COMMAND_SRC_0] = { 1, gpio_reg_cmd_source_0 }, 392 [GPIO_EFGH_COMMAND_SRC_1] = { 1, gpio_reg_cmd_source_1 }, 393 [GPIO_EFGH_DATA_READ] = { 1, gpio_reg_data_read }, 394 [GPIO_EFGH_INPUT_MASK] = { 1, gpio_reg_input_mask }, 395 /* Set IJKL */ 396 [GPIO_IJKL_DATA_VALUE] = { 2, gpio_reg_data_value }, 397 [GPIO_IJKL_DIRECTION] = { 2, gpio_reg_direction }, 398 [GPIO_IJKL_INT_ENABLE] = { 2, gpio_reg_int_enable }, 399 [GPIO_IJKL_INT_SENS_0] = { 2, gpio_reg_int_sens_0 }, 400 [GPIO_IJKL_INT_SENS_1] = { 2, gpio_reg_int_sens_1 }, 401 [GPIO_IJKL_INT_SENS_2] = { 2, gpio_reg_int_sens_2 }, 402 [GPIO_IJKL_INT_STATUS] = { 2, gpio_reg_int_status }, 403 [GPIO_IJKL_RESET_TOLERANT] = { 2, gpio_reg_reset_tolerant }, 404 [GPIO_IJKL_DEBOUNCE_1] = { 2, gpio_reg_debounce_1 }, 405 [GPIO_IJKL_DEBOUNCE_2] = { 2, gpio_reg_debounce_2 }, 406 [GPIO_IJKL_COMMAND_SRC_0] = { 2, gpio_reg_cmd_source_0 }, 407 [GPIO_IJKL_COMMAND_SRC_1] = { 2, gpio_reg_cmd_source_1 }, 408 [GPIO_IJKL_DATA_READ] = { 2, gpio_reg_data_read }, 409 [GPIO_IJKL_INPUT_MASK] = { 2, gpio_reg_input_mask }, 410 /* Set MNOP */ 411 [GPIO_MNOP_DATA_VALUE] = { 3, gpio_reg_data_value }, 412 [GPIO_MNOP_DIRECTION] = { 3, gpio_reg_direction }, 413 [GPIO_MNOP_INT_ENABLE] = { 3, gpio_reg_int_enable }, 414 [GPIO_MNOP_INT_SENS_0] = { 3, gpio_reg_int_sens_0 }, 415 [GPIO_MNOP_INT_SENS_1] = { 3, gpio_reg_int_sens_1 }, 416 [GPIO_MNOP_INT_SENS_2] = { 3, gpio_reg_int_sens_2 }, 417 [GPIO_MNOP_INT_STATUS] = { 3, gpio_reg_int_status }, 418 [GPIO_MNOP_RESET_TOLERANT] = { 3, gpio_reg_reset_tolerant }, 419 [GPIO_MNOP_DEBOUNCE_1] = { 3, gpio_reg_debounce_1 }, 420 [GPIO_MNOP_DEBOUNCE_2] = { 3, gpio_reg_debounce_2 }, 421 [GPIO_MNOP_COMMAND_SRC_0] = { 3, gpio_reg_cmd_source_0 }, 422 [GPIO_MNOP_COMMAND_SRC_1] = { 3, gpio_reg_cmd_source_1 }, 423 [GPIO_MNOP_DATA_READ] = { 3, gpio_reg_data_read }, 424 [GPIO_MNOP_INPUT_MASK] = { 3, gpio_reg_input_mask }, 425 /* Set QRST */ 426 [GPIO_QRST_DATA_VALUE] = { 4, gpio_reg_data_value }, 427 [GPIO_QRST_DIRECTION] = { 4, gpio_reg_direction }, 428 [GPIO_QRST_INT_ENABLE] = { 4, gpio_reg_int_enable }, 429 [GPIO_QRST_INT_SENS_0] = { 4, gpio_reg_int_sens_0 }, 430 [GPIO_QRST_INT_SENS_1] = { 4, gpio_reg_int_sens_1 }, 431 [GPIO_QRST_INT_SENS_2] = { 4, gpio_reg_int_sens_2 }, 432 [GPIO_QRST_INT_STATUS] = { 4, gpio_reg_int_status }, 433 [GPIO_QRST_RESET_TOLERANT] = { 4, gpio_reg_reset_tolerant }, 434 [GPIO_QRST_DEBOUNCE_1] = { 4, gpio_reg_debounce_1 }, 435 [GPIO_QRST_DEBOUNCE_2] = { 4, gpio_reg_debounce_2 }, 436 [GPIO_QRST_COMMAND_SRC_0] = { 4, gpio_reg_cmd_source_0 }, 437 [GPIO_QRST_COMMAND_SRC_1] = { 4, gpio_reg_cmd_source_1 }, 438 [GPIO_QRST_DATA_READ] = { 4, gpio_reg_data_read }, 439 [GPIO_QRST_INPUT_MASK] = { 4, gpio_reg_input_mask }, 440 /* Set UVWX */ 441 [GPIO_UVWX_DATA_VALUE] = { 5, gpio_reg_data_value }, 442 [GPIO_UVWX_DIRECTION] = { 5, gpio_reg_direction }, 443 [GPIO_UVWX_INT_ENABLE] = { 5, gpio_reg_int_enable }, 444 [GPIO_UVWX_INT_SENS_0] = { 5, gpio_reg_int_sens_0 }, 445 [GPIO_UVWX_INT_SENS_1] = { 5, gpio_reg_int_sens_1 }, 446 [GPIO_UVWX_INT_SENS_2] = { 5, gpio_reg_int_sens_2 }, 447 [GPIO_UVWX_INT_STATUS] = { 5, gpio_reg_int_status }, 448 [GPIO_UVWX_RESET_TOLERANT] = { 5, gpio_reg_reset_tolerant }, 449 [GPIO_UVWX_DEBOUNCE_1] = { 5, gpio_reg_debounce_1 }, 450 [GPIO_UVWX_DEBOUNCE_2] = { 5, gpio_reg_debounce_2 }, 451 [GPIO_UVWX_COMMAND_SRC_0] = { 5, gpio_reg_cmd_source_0 }, 452 [GPIO_UVWX_COMMAND_SRC_1] = { 5, gpio_reg_cmd_source_1 }, 453 [GPIO_UVWX_DATA_READ] = { 5, gpio_reg_data_read }, 454 [GPIO_UVWX_INPUT_MASK] = { 5, gpio_reg_input_mask }, 455 /* Set YZAAAB */ 456 [GPIO_YZAAAB_DATA_VALUE] = { 6, gpio_reg_data_value }, 457 [GPIO_YZAAAB_DIRECTION] = { 6, gpio_reg_direction }, 458 [GPIO_YZAAAB_INT_ENABLE] = { 6, gpio_reg_int_enable }, 459 [GPIO_YZAAAB_INT_SENS_0] = { 6, gpio_reg_int_sens_0 }, 460 [GPIO_YZAAAB_INT_SENS_1] = { 6, gpio_reg_int_sens_1 }, 461 [GPIO_YZAAAB_INT_SENS_2] = { 6, gpio_reg_int_sens_2 }, 462 [GPIO_YZAAAB_INT_STATUS] = { 6, gpio_reg_int_status }, 463 [GPIO_YZAAAB_RESET_TOLERANT] = { 6, gpio_reg_reset_tolerant }, 464 [GPIO_YZAAAB_DEBOUNCE_1] = { 6, gpio_reg_debounce_1 }, 465 [GPIO_YZAAAB_DEBOUNCE_2] = { 6, gpio_reg_debounce_2 }, 466 [GPIO_YZAAAB_COMMAND_SRC_0] = { 6, gpio_reg_cmd_source_0 }, 467 [GPIO_YZAAAB_COMMAND_SRC_1] = { 6, gpio_reg_cmd_source_1 }, 468 [GPIO_YZAAAB_DATA_READ] = { 6, gpio_reg_data_read }, 469 [GPIO_YZAAAB_INPUT_MASK] = { 6, gpio_reg_input_mask }, 470 /* Set AC (ast2500 only) */ 471 [GPIO_AC_DATA_VALUE] = { 7, gpio_reg_data_value }, 472 [GPIO_AC_DIRECTION] = { 7, gpio_reg_direction }, 473 [GPIO_AC_INT_ENABLE] = { 7, gpio_reg_int_enable }, 474 [GPIO_AC_INT_SENS_0] = { 7, gpio_reg_int_sens_0 }, 475 [GPIO_AC_INT_SENS_1] = { 7, gpio_reg_int_sens_1 }, 476 [GPIO_AC_INT_SENS_2] = { 7, gpio_reg_int_sens_2 }, 477 [GPIO_AC_INT_STATUS] = { 7, gpio_reg_int_status }, 478 [GPIO_AC_RESET_TOLERANT] = { 7, gpio_reg_reset_tolerant }, 479 [GPIO_AC_DEBOUNCE_1] = { 7, gpio_reg_debounce_1 }, 480 [GPIO_AC_DEBOUNCE_2] = { 7, gpio_reg_debounce_2 }, 481 [GPIO_AC_COMMAND_SRC_0] = { 7, gpio_reg_cmd_source_0 }, 482 [GPIO_AC_COMMAND_SRC_1] = { 7, gpio_reg_cmd_source_1 }, 483 [GPIO_AC_DATA_READ] = { 7, gpio_reg_data_read }, 484 [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask }, 485 }; 486 487 static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = { 488 /* 1.8V Set ABCD */ 489 [GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value}, 490 [GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction}, 491 [GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable}, 492 [GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0}, 493 [GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1}, 494 [GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2}, 495 [GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status}, 496 [GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant}, 497 [GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1}, 498 [GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2}, 499 [GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0}, 500 [GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1}, 501 [GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read}, 502 [GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask}, 503 /* 1.8V Set E */ 504 [GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value}, 505 [GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction}, 506 [GPIO_1_8V_E_INT_ENABLE] = {1, gpio_reg_int_enable}, 507 [GPIO_1_8V_E_INT_SENS_0] = {1, gpio_reg_int_sens_0}, 508 [GPIO_1_8V_E_INT_SENS_1] = {1, gpio_reg_int_sens_1}, 509 [GPIO_1_8V_E_INT_SENS_2] = {1, gpio_reg_int_sens_2}, 510 [GPIO_1_8V_E_INT_STATUS] = {1, gpio_reg_int_status}, 511 [GPIO_1_8V_E_RESET_TOLERANT] = {1, gpio_reg_reset_tolerant}, 512 [GPIO_1_8V_E_DEBOUNCE_1] = {1, gpio_reg_debounce_1}, 513 [GPIO_1_8V_E_DEBOUNCE_2] = {1, gpio_reg_debounce_2}, 514 [GPIO_1_8V_E_COMMAND_SRC_0] = {1, gpio_reg_cmd_source_0}, 515 [GPIO_1_8V_E_COMMAND_SRC_1] = {1, gpio_reg_cmd_source_1}, 516 [GPIO_1_8V_E_DATA_READ] = {1, gpio_reg_data_read}, 517 [GPIO_1_8V_E_INPUT_MASK] = {1, gpio_reg_input_mask}, 518 }; 519 520 static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) 521 { 522 AspeedGPIOState *s = ASPEED_GPIO(opaque); 523 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 524 uint64_t idx = -1; 525 const AspeedGPIOReg *reg; 526 GPIOSets *set; 527 uint32_t value = 0; 528 uint64_t debounce_value; 529 530 idx = offset >> 2; 531 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 532 idx -= GPIO_DEBOUNCE_TIME_1; 533 debounce_value = (uint64_t) s->debounce_regs[idx]; 534 trace_aspeed_gpio_read(offset, debounce_value); 535 return debounce_value; 536 } 537 538 reg = &agc->reg_table[idx]; 539 if (reg->set_idx >= agc->nr_gpio_sets) { 540 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 541 HWADDR_PRIx"\n", __func__, offset); 542 return 0; 543 } 544 545 set = &s->sets[reg->set_idx]; 546 switch (reg->type) { 547 case gpio_reg_data_value: 548 value = set->data_value; 549 break; 550 case gpio_reg_direction: 551 value = set->direction; 552 break; 553 case gpio_reg_int_enable: 554 value = set->int_enable; 555 break; 556 case gpio_reg_int_sens_0: 557 value = set->int_sens_0; 558 break; 559 case gpio_reg_int_sens_1: 560 value = set->int_sens_1; 561 break; 562 case gpio_reg_int_sens_2: 563 value = set->int_sens_2; 564 break; 565 case gpio_reg_int_status: 566 value = set->int_status; 567 break; 568 case gpio_reg_reset_tolerant: 569 value = set->reset_tol; 570 break; 571 case gpio_reg_debounce_1: 572 value = set->debounce_1; 573 break; 574 case gpio_reg_debounce_2: 575 value = set->debounce_2; 576 break; 577 case gpio_reg_cmd_source_0: 578 value = set->cmd_source_0; 579 break; 580 case gpio_reg_cmd_source_1: 581 value = set->cmd_source_1; 582 break; 583 case gpio_reg_data_read: 584 value = set->data_read; 585 break; 586 case gpio_reg_input_mask: 587 value = set->input_mask; 588 break; 589 default: 590 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 591 HWADDR_PRIx"\n", __func__, offset); 592 return 0; 593 } 594 595 trace_aspeed_gpio_read(offset, value); 596 return value; 597 } 598 599 static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, 600 uint32_t size) 601 { 602 AspeedGPIOState *s = ASPEED_GPIO(opaque); 603 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 604 const GPIOSetProperties *props; 605 uint64_t idx = -1; 606 const AspeedGPIOReg *reg; 607 GPIOSets *set; 608 uint32_t cleared; 609 610 trace_aspeed_gpio_write(offset, data); 611 612 idx = offset >> 2; 613 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 614 idx -= GPIO_DEBOUNCE_TIME_1; 615 s->debounce_regs[idx] = (uint32_t) data; 616 return; 617 } 618 619 reg = &agc->reg_table[idx]; 620 if (reg->set_idx >= agc->nr_gpio_sets) { 621 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 622 HWADDR_PRIx"\n", __func__, offset); 623 return; 624 } 625 626 set = &s->sets[reg->set_idx]; 627 props = &agc->props[reg->set_idx]; 628 629 switch (reg->type) { 630 case gpio_reg_data_value: 631 data &= props->output; 632 data = update_value_control_source(set, set->data_value, data); 633 set->data_read = data; 634 aspeed_gpio_update(s, set, data); 635 return; 636 case gpio_reg_direction: 637 /* 638 * where data is the value attempted to be written to the pin: 639 * pin type | input mask | output mask | expected value 640 * ------------------------------------------------------------ 641 * bidirectional | 1 | 1 | data 642 * input only | 1 | 0 | 0 643 * output only | 0 | 1 | 1 644 * no pin | 0 | 0 | 0 645 * 646 * which is captured by: 647 * data = ( data | ~input) & output; 648 */ 649 data = (data | ~props->input) & props->output; 650 set->direction = update_value_control_source(set, set->direction, data); 651 break; 652 case gpio_reg_int_enable: 653 set->int_enable = update_value_control_source(set, set->int_enable, 654 data); 655 break; 656 case gpio_reg_int_sens_0: 657 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, 658 data); 659 break; 660 case gpio_reg_int_sens_1: 661 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, 662 data); 663 break; 664 case gpio_reg_int_sens_2: 665 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, 666 data); 667 break; 668 case gpio_reg_int_status: 669 cleared = ctpop32(data & set->int_status); 670 if (s->pending && cleared) { 671 assert(s->pending >= cleared); 672 s->pending -= cleared; 673 } 674 set->int_status &= ~data; 675 break; 676 case gpio_reg_reset_tolerant: 677 set->reset_tol = update_value_control_source(set, set->reset_tol, 678 data); 679 return; 680 case gpio_reg_debounce_1: 681 set->debounce_1 = update_value_control_source(set, set->debounce_1, 682 data); 683 return; 684 case gpio_reg_debounce_2: 685 set->debounce_2 = update_value_control_source(set, set->debounce_2, 686 data); 687 return; 688 case gpio_reg_cmd_source_0: 689 set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK; 690 return; 691 case gpio_reg_cmd_source_1: 692 set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK; 693 return; 694 case gpio_reg_data_read: 695 /* Read only register */ 696 return; 697 case gpio_reg_input_mask: 698 /* 699 * feeds into interrupt generation 700 * 0: read from data value reg will be updated 701 * 1: read from data value reg will not be updated 702 */ 703 set->input_mask = data & props->input; 704 break; 705 default: 706 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 707 HWADDR_PRIx"\n", __func__, offset); 708 return; 709 } 710 aspeed_gpio_update(s, set, set->data_value); 711 return; 712 } 713 714 static int get_set_idx(AspeedGPIOState *s, const char *group, int *group_idx) 715 { 716 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 717 int set_idx, g_idx; 718 719 for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) { 720 const GPIOSetProperties *set_props = &agc->props[set_idx]; 721 for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) { 722 if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) { 723 *group_idx = g_idx; 724 return set_idx; 725 } 726 } 727 } 728 return -1; 729 } 730 731 static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name, 732 void *opaque, Error **errp) 733 { 734 int pin = 0xfff; 735 bool level = true; 736 char group[4]; 737 AspeedGPIOState *s = ASPEED_GPIO(obj); 738 int set_idx, group_idx = 0; 739 740 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 741 /* 1.8V gpio */ 742 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 743 error_setg(errp, "%s: error reading %s", __func__, name); 744 return; 745 } 746 } 747 set_idx = get_set_idx(s, group, &group_idx); 748 if (set_idx == -1) { 749 error_setg(errp, "%s: invalid group %s", __func__, group); 750 return; 751 } 752 pin = pin + group_idx * GPIOS_PER_GROUP; 753 level = aspeed_gpio_get_pin_level(s, set_idx, pin); 754 visit_type_bool(v, name, &level, errp); 755 } 756 757 static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, 758 void *opaque, Error **errp) 759 { 760 bool level; 761 int pin = 0xfff; 762 char group[4]; 763 AspeedGPIOState *s = ASPEED_GPIO(obj); 764 int set_idx, group_idx = 0; 765 766 if (!visit_type_bool(v, name, &level, errp)) { 767 return; 768 } 769 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 770 /* 1.8V gpio */ 771 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 772 error_setg(errp, "%s: error reading %s", __func__, name); 773 return; 774 } 775 } 776 set_idx = get_set_idx(s, group, &group_idx); 777 if (set_idx == -1) { 778 error_setg(errp, "%s: invalid group %s", __func__, group); 779 return; 780 } 781 pin = pin + group_idx * GPIOS_PER_GROUP; 782 aspeed_gpio_set_pin_level(s, set_idx, pin, level); 783 } 784 785 /****************** Setup functions ******************/ 786 static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 787 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 788 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 789 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 790 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 791 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 792 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 793 [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, 794 }; 795 796 static const GPIOSetProperties ast2500_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 797 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 798 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 799 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 800 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 801 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 802 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 803 [6] = {0x0fffffff, 0x0fffffff, {"Y", "Z", "AA", "AB"} }, 804 [7] = {0x000000ff, 0x000000ff, {"AC"} }, 805 }; 806 807 static GPIOSetProperties ast2600_3_3v_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 808 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 809 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 810 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 811 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 812 [4] = {0xffffffff, 0x00ffffff, {"Q", "R", "S", "T"} }, 813 [5] = {0xffffffff, 0xffffff00, {"U", "V", "W", "X"} }, 814 [6] = {0x0000ffff, 0x0000ffff, {"Y", "Z"} }, 815 }; 816 817 static GPIOSetProperties ast2600_1_8v_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 818 [0] = {0xffffffff, 0xffffffff, {"18A", "18B", "18C", "18D"} }, 819 [1] = {0x0000000f, 0x0000000f, {"18E"} }, 820 }; 821 822 static GPIOSetProperties ast1030_set_props[ASPEED_GPIO_MAX_NR_SETS] = { 823 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 824 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 825 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 826 [3] = {0xffffff3f, 0xffffff3f, {"M", "N", "O", "P"} }, 827 [4] = {0xff060c1f, 0x00060c1f, {"Q", "R", "S", "T"} }, 828 [5] = {0x000000ff, 0x00000000, {"U"} }, 829 }; 830 831 static const MemoryRegionOps aspeed_gpio_ops = { 832 .read = aspeed_gpio_read, 833 .write = aspeed_gpio_write, 834 .endianness = DEVICE_LITTLE_ENDIAN, 835 .valid.min_access_size = 4, 836 .valid.max_access_size = 4, 837 }; 838 839 static void aspeed_gpio_reset(DeviceState *dev) 840 { 841 AspeedGPIOState *s = ASPEED_GPIO(dev); 842 843 /* TODO: respect the reset tolerance registers */ 844 memset(s->sets, 0, sizeof(s->sets)); 845 } 846 847 static void aspeed_gpio_realize(DeviceState *dev, Error **errp) 848 { 849 AspeedGPIOState *s = ASPEED_GPIO(dev); 850 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 851 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 852 853 /* Interrupt parent line */ 854 sysbus_init_irq(sbd, &s->irq); 855 856 /* Individual GPIOs */ 857 for (int i = 0; i < ASPEED_GPIO_MAX_NR_SETS; i++) { 858 const GPIOSetProperties *props = &agc->props[i]; 859 uint32_t skip = ~(props->input | props->output); 860 for (int j = 0; j < ASPEED_GPIOS_PER_SET; j++) { 861 if (skip >> j & 1) { 862 continue; 863 } 864 sysbus_init_irq(sbd, &s->gpios[i][j]); 865 } 866 } 867 868 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, 869 TYPE_ASPEED_GPIO, 0x800); 870 871 sysbus_init_mmio(sbd, &s->iomem); 872 } 873 874 static void aspeed_gpio_init(Object *obj) 875 { 876 AspeedGPIOState *s = ASPEED_GPIO(obj); 877 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 878 879 for (int i = 0; i < ASPEED_GPIO_MAX_NR_SETS; i++) { 880 const GPIOSetProperties *props = &agc->props[i]; 881 uint32_t skip = ~(props->input | props->output); 882 for (int j = 0; j < ASPEED_GPIOS_PER_SET; j++) { 883 if (skip >> j & 1) { 884 continue; 885 } 886 int group_idx = j / GPIOS_PER_GROUP; 887 int pin_idx = j % GPIOS_PER_GROUP; 888 const char *group = &props->group_label[group_idx][0]; 889 char *name = g_strdup_printf("gpio%s%d", group, pin_idx); 890 object_property_add(obj, name, "bool", aspeed_gpio_get_pin, 891 aspeed_gpio_set_pin, NULL, NULL); 892 g_free(name); 893 } 894 } 895 } 896 897 static const VMStateDescription vmstate_gpio_regs = { 898 .name = TYPE_ASPEED_GPIO"/regs", 899 .version_id = 1, 900 .minimum_version_id = 1, 901 .fields = (VMStateField[]) { 902 VMSTATE_UINT32(data_value, GPIOSets), 903 VMSTATE_UINT32(data_read, GPIOSets), 904 VMSTATE_UINT32(direction, GPIOSets), 905 VMSTATE_UINT32(int_enable, GPIOSets), 906 VMSTATE_UINT32(int_sens_0, GPIOSets), 907 VMSTATE_UINT32(int_sens_1, GPIOSets), 908 VMSTATE_UINT32(int_sens_2, GPIOSets), 909 VMSTATE_UINT32(int_status, GPIOSets), 910 VMSTATE_UINT32(reset_tol, GPIOSets), 911 VMSTATE_UINT32(cmd_source_0, GPIOSets), 912 VMSTATE_UINT32(cmd_source_1, GPIOSets), 913 VMSTATE_UINT32(debounce_1, GPIOSets), 914 VMSTATE_UINT32(debounce_2, GPIOSets), 915 VMSTATE_UINT32(input_mask, GPIOSets), 916 VMSTATE_END_OF_LIST(), 917 } 918 }; 919 920 static const VMStateDescription vmstate_aspeed_gpio = { 921 .name = TYPE_ASPEED_GPIO, 922 .version_id = 1, 923 .minimum_version_id = 1, 924 .fields = (VMStateField[]) { 925 VMSTATE_STRUCT_ARRAY(sets, AspeedGPIOState, ASPEED_GPIO_MAX_NR_SETS, 926 1, vmstate_gpio_regs, GPIOSets), 927 VMSTATE_UINT32_ARRAY(debounce_regs, AspeedGPIOState, 928 ASPEED_GPIO_NR_DEBOUNCE_REGS), 929 VMSTATE_END_OF_LIST(), 930 } 931 }; 932 933 static void aspeed_gpio_class_init(ObjectClass *klass, void *data) 934 { 935 DeviceClass *dc = DEVICE_CLASS(klass); 936 937 dc->realize = aspeed_gpio_realize; 938 dc->reset = aspeed_gpio_reset; 939 dc->desc = "Aspeed GPIO Controller"; 940 dc->vmsd = &vmstate_aspeed_gpio; 941 } 942 943 static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) 944 { 945 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 946 947 agc->props = ast2400_set_props; 948 agc->nr_gpio_pins = 216; 949 agc->nr_gpio_sets = 7; 950 agc->reg_table = aspeed_3_3v_gpios; 951 } 952 953 static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) 954 { 955 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 956 957 agc->props = ast2500_set_props; 958 agc->nr_gpio_pins = 228; 959 agc->nr_gpio_sets = 8; 960 agc->reg_table = aspeed_3_3v_gpios; 961 } 962 963 static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) 964 { 965 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 966 967 agc->props = ast2600_3_3v_set_props; 968 agc->nr_gpio_pins = 208; 969 agc->nr_gpio_sets = 7; 970 agc->reg_table = aspeed_3_3v_gpios; 971 } 972 973 static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) 974 { 975 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 976 977 agc->props = ast2600_1_8v_set_props; 978 agc->nr_gpio_pins = 36; 979 agc->nr_gpio_sets = 2; 980 agc->reg_table = aspeed_1_8v_gpios; 981 } 982 983 static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) 984 { 985 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 986 987 agc->props = ast1030_set_props; 988 agc->nr_gpio_pins = 151; 989 agc->nr_gpio_sets = 6; 990 agc->reg_table = aspeed_3_3v_gpios; 991 } 992 993 static const TypeInfo aspeed_gpio_info = { 994 .name = TYPE_ASPEED_GPIO, 995 .parent = TYPE_SYS_BUS_DEVICE, 996 .instance_size = sizeof(AspeedGPIOState), 997 .class_size = sizeof(AspeedGPIOClass), 998 .class_init = aspeed_gpio_class_init, 999 .abstract = true, 1000 }; 1001 1002 static const TypeInfo aspeed_gpio_ast2400_info = { 1003 .name = TYPE_ASPEED_GPIO "-ast2400", 1004 .parent = TYPE_ASPEED_GPIO, 1005 .class_init = aspeed_gpio_ast2400_class_init, 1006 .instance_init = aspeed_gpio_init, 1007 }; 1008 1009 static const TypeInfo aspeed_gpio_ast2500_info = { 1010 .name = TYPE_ASPEED_GPIO "-ast2500", 1011 .parent = TYPE_ASPEED_GPIO, 1012 .class_init = aspeed_gpio_2500_class_init, 1013 .instance_init = aspeed_gpio_init, 1014 }; 1015 1016 static const TypeInfo aspeed_gpio_ast2600_3_3v_info = { 1017 .name = TYPE_ASPEED_GPIO "-ast2600", 1018 .parent = TYPE_ASPEED_GPIO, 1019 .class_init = aspeed_gpio_ast2600_3_3v_class_init, 1020 .instance_init = aspeed_gpio_init, 1021 }; 1022 1023 static const TypeInfo aspeed_gpio_ast2600_1_8v_info = { 1024 .name = TYPE_ASPEED_GPIO "-ast2600-1_8v", 1025 .parent = TYPE_ASPEED_GPIO, 1026 .class_init = aspeed_gpio_ast2600_1_8v_class_init, 1027 .instance_init = aspeed_gpio_init, 1028 }; 1029 1030 static const TypeInfo aspeed_gpio_ast1030_info = { 1031 .name = TYPE_ASPEED_GPIO "-ast1030", 1032 .parent = TYPE_ASPEED_GPIO, 1033 .class_init = aspeed_gpio_1030_class_init, 1034 .instance_init = aspeed_gpio_init, 1035 }; 1036 1037 static void aspeed_gpio_register_types(void) 1038 { 1039 type_register_static(&aspeed_gpio_info); 1040 type_register_static(&aspeed_gpio_ast2400_info); 1041 type_register_static(&aspeed_gpio_ast2500_info); 1042 type_register_static(&aspeed_gpio_ast2600_3_3v_info); 1043 type_register_static(&aspeed_gpio_ast2600_1_8v_info); 1044 type_register_static(&aspeed_gpio_ast1030_info); 1045 } 1046 1047 type_init(aspeed_gpio_register_types); 1048