1 /* 2 * QEMU VMware-SVGA "chipset". 3 * 4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/loader.h" 26 #include "trace.h" 27 #include "ui/console.h" 28 #include "ui/vnc.h" 29 #include "hw/pci/pci.h" 30 31 #undef VERBOSE 32 #if 0 33 #define HW_RECT_ACCEL 34 #define HW_FILL_ACCEL 35 #endif 36 #define HW_MOUSE_ACCEL 37 38 #include "vga_int.h" 39 40 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ 41 42 struct vmsvga_state_s { 43 VGACommonState vga; 44 45 int invalidated; 46 int enable; 47 int config; 48 struct { 49 int id; 50 int x; 51 int y; 52 int on; 53 } cursor; 54 55 int index; 56 int scratch_size; 57 uint32_t *scratch; 58 int new_width; 59 int new_height; 60 int new_depth; 61 uint32_t guest; 62 uint32_t svgaid; 63 int syncing; 64 65 MemoryRegion fifo_ram; 66 uint8_t *fifo_ptr; 67 unsigned int fifo_size; 68 69 union { 70 uint32_t *fifo; 71 struct QEMU_PACKED { 72 uint32_t min; 73 uint32_t max; 74 uint32_t next_cmd; 75 uint32_t stop; 76 /* Add registers here when adding capabilities. */ 77 uint32_t fifo[0]; 78 } *cmd; 79 }; 80 81 #define REDRAW_FIFO_LEN 512 82 struct vmsvga_rect_s { 83 int x, y, w, h; 84 } redraw_fifo[REDRAW_FIFO_LEN]; 85 int redraw_fifo_first, redraw_fifo_last; 86 }; 87 88 #define TYPE_VMWARE_SVGA "vmware-svga" 89 90 #define VMWARE_SVGA(obj) \ 91 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA) 92 93 struct pci_vmsvga_state_s { 94 /*< private >*/ 95 PCIDevice parent_obj; 96 /*< public >*/ 97 98 struct vmsvga_state_s chip; 99 MemoryRegion io_bar; 100 }; 101 102 #define SVGA_MAGIC 0x900000UL 103 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 104 #define SVGA_ID_0 SVGA_MAKE_ID(0) 105 #define SVGA_ID_1 SVGA_MAKE_ID(1) 106 #define SVGA_ID_2 SVGA_MAKE_ID(2) 107 108 #define SVGA_LEGACY_BASE_PORT 0x4560 109 #define SVGA_INDEX_PORT 0x0 110 #define SVGA_VALUE_PORT 0x1 111 #define SVGA_BIOS_PORT 0x2 112 113 #define SVGA_VERSION_2 114 115 #ifdef SVGA_VERSION_2 116 # define SVGA_ID SVGA_ID_2 117 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 118 # define SVGA_IO_MUL 1 119 # define SVGA_FIFO_SIZE 0x10000 120 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 121 #else 122 # define SVGA_ID SVGA_ID_1 123 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 124 # define SVGA_IO_MUL 4 125 # define SVGA_FIFO_SIZE 0x10000 126 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA 127 #endif 128 129 enum { 130 /* ID 0, 1 and 2 registers */ 131 SVGA_REG_ID = 0, 132 SVGA_REG_ENABLE = 1, 133 SVGA_REG_WIDTH = 2, 134 SVGA_REG_HEIGHT = 3, 135 SVGA_REG_MAX_WIDTH = 4, 136 SVGA_REG_MAX_HEIGHT = 5, 137 SVGA_REG_DEPTH = 6, 138 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 139 SVGA_REG_PSEUDOCOLOR = 8, 140 SVGA_REG_RED_MASK = 9, 141 SVGA_REG_GREEN_MASK = 10, 142 SVGA_REG_BLUE_MASK = 11, 143 SVGA_REG_BYTES_PER_LINE = 12, 144 SVGA_REG_FB_START = 13, 145 SVGA_REG_FB_OFFSET = 14, 146 SVGA_REG_VRAM_SIZE = 15, 147 SVGA_REG_FB_SIZE = 16, 148 149 /* ID 1 and 2 registers */ 150 SVGA_REG_CAPABILITIES = 17, 151 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ 152 SVGA_REG_MEM_SIZE = 19, 153 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 154 SVGA_REG_SYNC = 21, /* Write to force synchronization */ 155 SVGA_REG_BUSY = 22, /* Read to check if sync is done */ 156 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 157 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ 158 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ 159 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ 160 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ 161 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ 162 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 163 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 164 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ 165 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 166 167 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 168 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, 169 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, 170 }; 171 172 #define SVGA_CAP_NONE 0 173 #define SVGA_CAP_RECT_FILL (1 << 0) 174 #define SVGA_CAP_RECT_COPY (1 << 1) 175 #define SVGA_CAP_RECT_PAT_FILL (1 << 2) 176 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) 177 #define SVGA_CAP_RASTER_OP (1 << 4) 178 #define SVGA_CAP_CURSOR (1 << 5) 179 #define SVGA_CAP_CURSOR_BYPASS (1 << 6) 180 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) 181 #define SVGA_CAP_8BIT_EMULATION (1 << 8) 182 #define SVGA_CAP_ALPHA_CURSOR (1 << 9) 183 #define SVGA_CAP_GLYPH (1 << 10) 184 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) 185 #define SVGA_CAP_OFFSCREEN_1 (1 << 12) 186 #define SVGA_CAP_ALPHA_BLEND (1 << 13) 187 #define SVGA_CAP_3D (1 << 14) 188 #define SVGA_CAP_EXTENDED_FIFO (1 << 15) 189 #define SVGA_CAP_MULTIMON (1 << 16) 190 #define SVGA_CAP_PITCHLOCK (1 << 17) 191 192 /* 193 * FIFO offsets (seen as an array of 32-bit words) 194 */ 195 enum { 196 /* 197 * The original defined FIFO offsets 198 */ 199 SVGA_FIFO_MIN = 0, 200 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 201 SVGA_FIFO_NEXT_CMD, 202 SVGA_FIFO_STOP, 203 204 /* 205 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO 206 */ 207 SVGA_FIFO_CAPABILITIES = 4, 208 SVGA_FIFO_FLAGS, 209 SVGA_FIFO_FENCE, 210 SVGA_FIFO_3D_HWVERSION, 211 SVGA_FIFO_PITCHLOCK, 212 }; 213 214 #define SVGA_FIFO_CAP_NONE 0 215 #define SVGA_FIFO_CAP_FENCE (1 << 0) 216 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 217 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 218 219 #define SVGA_FIFO_FLAG_NONE 0 220 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 221 222 /* These values can probably be changed arbitrarily. */ 223 #define SVGA_SCRATCH_SIZE 0x8000 224 #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT) 225 #define SVGA_MAX_HEIGHT 1770 226 227 #ifdef VERBOSE 228 # define GUEST_OS_BASE 0x5001 229 static const char *vmsvga_guest_id[] = { 230 [0x00] = "Dos", 231 [0x01] = "Windows 3.1", 232 [0x02] = "Windows 95", 233 [0x03] = "Windows 98", 234 [0x04] = "Windows ME", 235 [0x05] = "Windows NT", 236 [0x06] = "Windows 2000", 237 [0x07] = "Linux", 238 [0x08] = "OS/2", 239 [0x09] = "an unknown OS", 240 [0x0a] = "BSD", 241 [0x0b] = "Whistler", 242 [0x0c] = "an unknown OS", 243 [0x0d] = "an unknown OS", 244 [0x0e] = "an unknown OS", 245 [0x0f] = "an unknown OS", 246 [0x10] = "an unknown OS", 247 [0x11] = "an unknown OS", 248 [0x12] = "an unknown OS", 249 [0x13] = "an unknown OS", 250 [0x14] = "an unknown OS", 251 [0x15] = "Windows 2003", 252 }; 253 #endif 254 255 enum { 256 SVGA_CMD_INVALID_CMD = 0, 257 SVGA_CMD_UPDATE = 1, 258 SVGA_CMD_RECT_FILL = 2, 259 SVGA_CMD_RECT_COPY = 3, 260 SVGA_CMD_DEFINE_BITMAP = 4, 261 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, 262 SVGA_CMD_DEFINE_PIXMAP = 6, 263 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, 264 SVGA_CMD_RECT_BITMAP_FILL = 8, 265 SVGA_CMD_RECT_PIXMAP_FILL = 9, 266 SVGA_CMD_RECT_BITMAP_COPY = 10, 267 SVGA_CMD_RECT_PIXMAP_COPY = 11, 268 SVGA_CMD_FREE_OBJECT = 12, 269 SVGA_CMD_RECT_ROP_FILL = 13, 270 SVGA_CMD_RECT_ROP_COPY = 14, 271 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, 272 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, 273 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, 274 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, 275 SVGA_CMD_DEFINE_CURSOR = 19, 276 SVGA_CMD_DISPLAY_CURSOR = 20, 277 SVGA_CMD_MOVE_CURSOR = 21, 278 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 279 SVGA_CMD_DRAW_GLYPH = 23, 280 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, 281 SVGA_CMD_UPDATE_VERBOSE = 25, 282 SVGA_CMD_SURFACE_FILL = 26, 283 SVGA_CMD_SURFACE_COPY = 27, 284 SVGA_CMD_SURFACE_ALPHA_BLEND = 28, 285 SVGA_CMD_FRONT_ROP_FILL = 29, 286 SVGA_CMD_FENCE = 30, 287 }; 288 289 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ 290 enum { 291 SVGA_CURSOR_ON_HIDE = 0, 292 SVGA_CURSOR_ON_SHOW = 1, 293 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, 294 SVGA_CURSOR_ON_RESTORE_TO_FB = 3, 295 }; 296 297 static inline void vmsvga_update_rect(struct vmsvga_state_s *s, 298 int x, int y, int w, int h) 299 { 300 DisplaySurface *surface = qemu_console_surface(s->vga.con); 301 int line; 302 int bypl; 303 int width; 304 int start; 305 uint8_t *src; 306 uint8_t *dst; 307 308 if (x < 0) { 309 fprintf(stderr, "%s: update x was < 0 (%d)\n", __func__, x); 310 w += x; 311 x = 0; 312 } 313 if (w < 0) { 314 fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w); 315 w = 0; 316 } 317 if (x + w > surface_width(surface)) { 318 fprintf(stderr, "%s: update width too large x: %d, w: %d\n", 319 __func__, x, w); 320 x = MIN(x, surface_width(surface)); 321 w = surface_width(surface) - x; 322 } 323 324 if (y < 0) { 325 fprintf(stderr, "%s: update y was < 0 (%d)\n", __func__, y); 326 h += y; 327 y = 0; 328 } 329 if (h < 0) { 330 fprintf(stderr, "%s: update h was < 0 (%d)\n", __func__, h); 331 h = 0; 332 } 333 if (y + h > surface_height(surface)) { 334 fprintf(stderr, "%s: update height too large y: %d, h: %d\n", 335 __func__, y, h); 336 y = MIN(y, surface_height(surface)); 337 h = surface_height(surface) - y; 338 } 339 340 bypl = surface_stride(surface); 341 width = surface_bytes_per_pixel(surface) * w; 342 start = surface_bytes_per_pixel(surface) * x + bypl * y; 343 src = s->vga.vram_ptr + start; 344 dst = surface_data(surface) + start; 345 346 for (line = h; line > 0; line--, src += bypl, dst += bypl) { 347 memcpy(dst, src, width); 348 } 349 dpy_gfx_update(s->vga.con, x, y, w, h); 350 } 351 352 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, 353 int x, int y, int w, int h) 354 { 355 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; 356 357 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; 358 rect->x = x; 359 rect->y = y; 360 rect->w = w; 361 rect->h = h; 362 } 363 364 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) 365 { 366 struct vmsvga_rect_s *rect; 367 368 if (s->invalidated) { 369 s->redraw_fifo_first = s->redraw_fifo_last; 370 return; 371 } 372 /* Overlapping region updates can be optimised out here - if someone 373 * knows a smart algorithm to do that, please share. */ 374 while (s->redraw_fifo_first != s->redraw_fifo_last) { 375 rect = &s->redraw_fifo[s->redraw_fifo_first++]; 376 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; 377 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); 378 } 379 } 380 381 #ifdef HW_RECT_ACCEL 382 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, 383 int x0, int y0, int x1, int y1, int w, int h) 384 { 385 DisplaySurface *surface = qemu_console_surface(s->vga.con); 386 uint8_t *vram = s->vga.vram_ptr; 387 int bypl = surface_stride(surface); 388 int bypp = surface_bytes_per_pixel(surface); 389 int width = bypp * w; 390 int line = h; 391 uint8_t *ptr[2]; 392 393 if (y1 > y0) { 394 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); 395 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); 396 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { 397 memmove(ptr[1], ptr[0], width); 398 } 399 } else { 400 ptr[0] = vram + bypp * x0 + bypl * y0; 401 ptr[1] = vram + bypp * x1 + bypl * y1; 402 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { 403 memmove(ptr[1], ptr[0], width); 404 } 405 } 406 407 vmsvga_update_rect_delayed(s, x1, y1, w, h); 408 } 409 #endif 410 411 #ifdef HW_FILL_ACCEL 412 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, 413 uint32_t c, int x, int y, int w, int h) 414 { 415 DisplaySurface *surface = qemu_console_surface(s->vga.con); 416 int bypl = surface_stride(surface); 417 int width = surface_bytes_per_pixel(surface) * w; 418 int line = h; 419 int column; 420 uint8_t *fst; 421 uint8_t *dst; 422 uint8_t *src; 423 uint8_t col[4]; 424 425 col[0] = c; 426 col[1] = c >> 8; 427 col[2] = c >> 16; 428 col[3] = c >> 24; 429 430 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; 431 432 if (line--) { 433 dst = fst; 434 src = col; 435 for (column = width; column > 0; column--) { 436 *(dst++) = *(src++); 437 if (src - col == surface_bytes_per_pixel(surface)) { 438 src = col; 439 } 440 } 441 dst = fst; 442 for (; line > 0; line--) { 443 dst += bypl; 444 memcpy(dst, fst, width); 445 } 446 } 447 448 vmsvga_update_rect_delayed(s, x, y, w, h); 449 } 450 #endif 451 452 struct vmsvga_cursor_definition_s { 453 int width; 454 int height; 455 int id; 456 int bpp; 457 int hot_x; 458 int hot_y; 459 uint32_t mask[1024]; 460 uint32_t image[4096]; 461 }; 462 463 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) 464 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) 465 466 #ifdef HW_MOUSE_ACCEL 467 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, 468 struct vmsvga_cursor_definition_s *c) 469 { 470 QEMUCursor *qc; 471 int i, pixels; 472 473 qc = cursor_alloc(c->width, c->height); 474 qc->hot_x = c->hot_x; 475 qc->hot_y = c->hot_y; 476 switch (c->bpp) { 477 case 1: 478 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, 479 1, (void *)c->mask); 480 #ifdef DEBUG 481 cursor_print_ascii_art(qc, "vmware/mono"); 482 #endif 483 break; 484 case 32: 485 /* fill alpha channel from mask, set color to zero */ 486 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, 487 1, (void *)c->mask); 488 /* add in rgb values */ 489 pixels = c->width * c->height; 490 for (i = 0; i < pixels; i++) { 491 qc->data[i] |= c->image[i] & 0xffffff; 492 } 493 #ifdef DEBUG 494 cursor_print_ascii_art(qc, "vmware/32bit"); 495 #endif 496 break; 497 default: 498 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", 499 __func__, c->bpp); 500 cursor_put(qc); 501 qc = cursor_builtin_left_ptr(); 502 } 503 504 dpy_cursor_define(s->vga.con, qc); 505 cursor_put(qc); 506 } 507 #endif 508 509 #define CMD(f) le32_to_cpu(s->cmd->f) 510 511 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) 512 { 513 int num; 514 515 if (!s->config || !s->enable) { 516 return 0; 517 } 518 num = CMD(next_cmd) - CMD(stop); 519 if (num < 0) { 520 num += CMD(max) - CMD(min); 521 } 522 return num >> 2; 523 } 524 525 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) 526 { 527 uint32_t cmd = s->fifo[CMD(stop) >> 2]; 528 529 s->cmd->stop = cpu_to_le32(CMD(stop) + 4); 530 if (CMD(stop) >= CMD(max)) { 531 s->cmd->stop = s->cmd->min; 532 } 533 return cmd; 534 } 535 536 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) 537 { 538 return le32_to_cpu(vmsvga_fifo_read_raw(s)); 539 } 540 541 static void vmsvga_fifo_run(struct vmsvga_state_s *s) 542 { 543 uint32_t cmd, colour; 544 int args, len; 545 int x, y, dx, dy, width, height; 546 struct vmsvga_cursor_definition_s cursor; 547 uint32_t cmd_start; 548 549 len = vmsvga_fifo_length(s); 550 while (len > 0) { 551 /* May need to go back to the start of the command if incomplete */ 552 cmd_start = s->cmd->stop; 553 554 switch (cmd = vmsvga_fifo_read(s)) { 555 case SVGA_CMD_UPDATE: 556 case SVGA_CMD_UPDATE_VERBOSE: 557 len -= 5; 558 if (len < 0) { 559 goto rewind; 560 } 561 562 x = vmsvga_fifo_read(s); 563 y = vmsvga_fifo_read(s); 564 width = vmsvga_fifo_read(s); 565 height = vmsvga_fifo_read(s); 566 vmsvga_update_rect_delayed(s, x, y, width, height); 567 break; 568 569 case SVGA_CMD_RECT_FILL: 570 len -= 6; 571 if (len < 0) { 572 goto rewind; 573 } 574 575 colour = vmsvga_fifo_read(s); 576 x = vmsvga_fifo_read(s); 577 y = vmsvga_fifo_read(s); 578 width = vmsvga_fifo_read(s); 579 height = vmsvga_fifo_read(s); 580 #ifdef HW_FILL_ACCEL 581 vmsvga_fill_rect(s, colour, x, y, width, height); 582 break; 583 #else 584 args = 0; 585 goto badcmd; 586 #endif 587 588 case SVGA_CMD_RECT_COPY: 589 len -= 7; 590 if (len < 0) { 591 goto rewind; 592 } 593 594 x = vmsvga_fifo_read(s); 595 y = vmsvga_fifo_read(s); 596 dx = vmsvga_fifo_read(s); 597 dy = vmsvga_fifo_read(s); 598 width = vmsvga_fifo_read(s); 599 height = vmsvga_fifo_read(s); 600 #ifdef HW_RECT_ACCEL 601 vmsvga_copy_rect(s, x, y, dx, dy, width, height); 602 break; 603 #else 604 args = 0; 605 goto badcmd; 606 #endif 607 608 case SVGA_CMD_DEFINE_CURSOR: 609 len -= 8; 610 if (len < 0) { 611 goto rewind; 612 } 613 614 cursor.id = vmsvga_fifo_read(s); 615 cursor.hot_x = vmsvga_fifo_read(s); 616 cursor.hot_y = vmsvga_fifo_read(s); 617 cursor.width = x = vmsvga_fifo_read(s); 618 cursor.height = y = vmsvga_fifo_read(s); 619 vmsvga_fifo_read(s); 620 cursor.bpp = vmsvga_fifo_read(s); 621 622 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); 623 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || 624 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { 625 goto badcmd; 626 } 627 628 len -= args; 629 if (len < 0) { 630 goto rewind; 631 } 632 633 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { 634 cursor.mask[args] = vmsvga_fifo_read_raw(s); 635 } 636 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { 637 cursor.image[args] = vmsvga_fifo_read_raw(s); 638 } 639 #ifdef HW_MOUSE_ACCEL 640 vmsvga_cursor_define(s, &cursor); 641 break; 642 #else 643 args = 0; 644 goto badcmd; 645 #endif 646 647 /* 648 * Other commands that we at least know the number of arguments 649 * for so we can avoid FIFO desync if driver uses them illegally. 650 */ 651 case SVGA_CMD_DEFINE_ALPHA_CURSOR: 652 len -= 6; 653 if (len < 0) { 654 goto rewind; 655 } 656 vmsvga_fifo_read(s); 657 vmsvga_fifo_read(s); 658 vmsvga_fifo_read(s); 659 x = vmsvga_fifo_read(s); 660 y = vmsvga_fifo_read(s); 661 args = x * y; 662 goto badcmd; 663 case SVGA_CMD_RECT_ROP_FILL: 664 args = 6; 665 goto badcmd; 666 case SVGA_CMD_RECT_ROP_COPY: 667 args = 7; 668 goto badcmd; 669 case SVGA_CMD_DRAW_GLYPH_CLIPPED: 670 len -= 4; 671 if (len < 0) { 672 goto rewind; 673 } 674 vmsvga_fifo_read(s); 675 vmsvga_fifo_read(s); 676 args = 7 + (vmsvga_fifo_read(s) >> 2); 677 goto badcmd; 678 case SVGA_CMD_SURFACE_ALPHA_BLEND: 679 args = 12; 680 goto badcmd; 681 682 /* 683 * Other commands that are not listed as depending on any 684 * CAPABILITIES bits, but are not described in the README either. 685 */ 686 case SVGA_CMD_SURFACE_FILL: 687 case SVGA_CMD_SURFACE_COPY: 688 case SVGA_CMD_FRONT_ROP_FILL: 689 case SVGA_CMD_FENCE: 690 case SVGA_CMD_INVALID_CMD: 691 break; /* Nop */ 692 693 default: 694 args = 0; 695 badcmd: 696 len -= args; 697 if (len < 0) { 698 goto rewind; 699 } 700 while (args--) { 701 vmsvga_fifo_read(s); 702 } 703 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", 704 __func__, cmd); 705 break; 706 707 rewind: 708 s->cmd->stop = cmd_start; 709 break; 710 } 711 } 712 713 s->syncing = 0; 714 } 715 716 static uint32_t vmsvga_index_read(void *opaque, uint32_t address) 717 { 718 struct vmsvga_state_s *s = opaque; 719 720 return s->index; 721 } 722 723 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) 724 { 725 struct vmsvga_state_s *s = opaque; 726 727 s->index = index; 728 } 729 730 static uint32_t vmsvga_value_read(void *opaque, uint32_t address) 731 { 732 uint32_t caps; 733 struct vmsvga_state_s *s = opaque; 734 DisplaySurface *surface = qemu_console_surface(s->vga.con); 735 PixelFormat pf; 736 uint32_t ret; 737 738 switch (s->index) { 739 case SVGA_REG_ID: 740 ret = s->svgaid; 741 break; 742 743 case SVGA_REG_ENABLE: 744 ret = s->enable; 745 break; 746 747 case SVGA_REG_WIDTH: 748 ret = s->new_width ? s->new_width : surface_width(surface); 749 break; 750 751 case SVGA_REG_HEIGHT: 752 ret = s->new_height ? s->new_height : surface_height(surface); 753 break; 754 755 case SVGA_REG_MAX_WIDTH: 756 ret = SVGA_MAX_WIDTH; 757 break; 758 759 case SVGA_REG_MAX_HEIGHT: 760 ret = SVGA_MAX_HEIGHT; 761 break; 762 763 case SVGA_REG_DEPTH: 764 ret = (s->new_depth == 32) ? 24 : s->new_depth; 765 break; 766 767 case SVGA_REG_BITS_PER_PIXEL: 768 case SVGA_REG_HOST_BITS_PER_PIXEL: 769 ret = s->new_depth; 770 break; 771 772 case SVGA_REG_PSEUDOCOLOR: 773 ret = 0x0; 774 break; 775 776 case SVGA_REG_RED_MASK: 777 pf = qemu_default_pixelformat(s->new_depth); 778 ret = pf.rmask; 779 break; 780 781 case SVGA_REG_GREEN_MASK: 782 pf = qemu_default_pixelformat(s->new_depth); 783 ret = pf.gmask; 784 break; 785 786 case SVGA_REG_BLUE_MASK: 787 pf = qemu_default_pixelformat(s->new_depth); 788 ret = pf.bmask; 789 break; 790 791 case SVGA_REG_BYTES_PER_LINE: 792 if (s->new_width) { 793 ret = (s->new_depth * s->new_width) / 8; 794 } else { 795 ret = surface_stride(surface); 796 } 797 break; 798 799 case SVGA_REG_FB_START: { 800 struct pci_vmsvga_state_s *pci_vmsvga 801 = container_of(s, struct pci_vmsvga_state_s, chip); 802 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1); 803 break; 804 } 805 806 case SVGA_REG_FB_OFFSET: 807 ret = 0x0; 808 break; 809 810 case SVGA_REG_VRAM_SIZE: 811 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ 812 break; 813 814 case SVGA_REG_FB_SIZE: 815 ret = s->vga.vram_size; 816 break; 817 818 case SVGA_REG_CAPABILITIES: 819 caps = SVGA_CAP_NONE; 820 #ifdef HW_RECT_ACCEL 821 caps |= SVGA_CAP_RECT_COPY; 822 #endif 823 #ifdef HW_FILL_ACCEL 824 caps |= SVGA_CAP_RECT_FILL; 825 #endif 826 #ifdef HW_MOUSE_ACCEL 827 if (dpy_cursor_define_supported(s->vga.con)) { 828 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 829 SVGA_CAP_CURSOR_BYPASS; 830 } 831 #endif 832 ret = caps; 833 break; 834 835 case SVGA_REG_MEM_START: { 836 struct pci_vmsvga_state_s *pci_vmsvga 837 = container_of(s, struct pci_vmsvga_state_s, chip); 838 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2); 839 break; 840 } 841 842 case SVGA_REG_MEM_SIZE: 843 ret = s->fifo_size; 844 break; 845 846 case SVGA_REG_CONFIG_DONE: 847 ret = s->config; 848 break; 849 850 case SVGA_REG_SYNC: 851 case SVGA_REG_BUSY: 852 ret = s->syncing; 853 break; 854 855 case SVGA_REG_GUEST_ID: 856 ret = s->guest; 857 break; 858 859 case SVGA_REG_CURSOR_ID: 860 ret = s->cursor.id; 861 break; 862 863 case SVGA_REG_CURSOR_X: 864 ret = s->cursor.x; 865 break; 866 867 case SVGA_REG_CURSOR_Y: 868 ret = s->cursor.y; 869 break; 870 871 case SVGA_REG_CURSOR_ON: 872 ret = s->cursor.on; 873 break; 874 875 case SVGA_REG_SCRATCH_SIZE: 876 ret = s->scratch_size; 877 break; 878 879 case SVGA_REG_MEM_REGS: 880 case SVGA_REG_NUM_DISPLAYS: 881 case SVGA_REG_PITCHLOCK: 882 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 883 ret = 0; 884 break; 885 886 default: 887 if (s->index >= SVGA_SCRATCH_BASE && 888 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 889 ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; 890 break; 891 } 892 printf("%s: Bad register %02x\n", __func__, s->index); 893 ret = 0; 894 break; 895 } 896 897 if (s->index >= SVGA_SCRATCH_BASE) { 898 trace_vmware_scratch_read(s->index, ret); 899 } else if (s->index >= SVGA_PALETTE_BASE) { 900 trace_vmware_palette_read(s->index, ret); 901 } else { 902 trace_vmware_value_read(s->index, ret); 903 } 904 return ret; 905 } 906 907 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) 908 { 909 struct vmsvga_state_s *s = opaque; 910 911 if (s->index >= SVGA_SCRATCH_BASE) { 912 trace_vmware_scratch_write(s->index, value); 913 } else if (s->index >= SVGA_PALETTE_BASE) { 914 trace_vmware_palette_write(s->index, value); 915 } else { 916 trace_vmware_value_write(s->index, value); 917 } 918 switch (s->index) { 919 case SVGA_REG_ID: 920 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { 921 s->svgaid = value; 922 } 923 break; 924 925 case SVGA_REG_ENABLE: 926 s->enable = !!value; 927 s->invalidated = 1; 928 s->vga.hw_ops->invalidate(&s->vga); 929 if (s->enable && s->config) { 930 vga_dirty_log_stop(&s->vga); 931 } else { 932 vga_dirty_log_start(&s->vga); 933 } 934 break; 935 936 case SVGA_REG_WIDTH: 937 if (value <= SVGA_MAX_WIDTH) { 938 s->new_width = value; 939 s->invalidated = 1; 940 } else { 941 printf("%s: Bad width: %i\n", __func__, value); 942 } 943 break; 944 945 case SVGA_REG_HEIGHT: 946 if (value <= SVGA_MAX_HEIGHT) { 947 s->new_height = value; 948 s->invalidated = 1; 949 } else { 950 printf("%s: Bad height: %i\n", __func__, value); 951 } 952 break; 953 954 case SVGA_REG_BITS_PER_PIXEL: 955 if (value != 32) { 956 printf("%s: Bad bits per pixel: %i bits\n", __func__, value); 957 s->config = 0; 958 s->invalidated = 1; 959 } 960 break; 961 962 case SVGA_REG_CONFIG_DONE: 963 if (value) { 964 s->fifo = (uint32_t *) s->fifo_ptr; 965 /* Check range and alignment. */ 966 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { 967 break; 968 } 969 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { 970 break; 971 } 972 if (CMD(max) > SVGA_FIFO_SIZE) { 973 break; 974 } 975 if (CMD(max) < CMD(min) + 10 * 1024) { 976 break; 977 } 978 vga_dirty_log_stop(&s->vga); 979 } 980 s->config = !!value; 981 break; 982 983 case SVGA_REG_SYNC: 984 s->syncing = 1; 985 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ 986 break; 987 988 case SVGA_REG_GUEST_ID: 989 s->guest = value; 990 #ifdef VERBOSE 991 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + 992 ARRAY_SIZE(vmsvga_guest_id)) { 993 printf("%s: guest runs %s.\n", __func__, 994 vmsvga_guest_id[value - GUEST_OS_BASE]); 995 } 996 #endif 997 break; 998 999 case SVGA_REG_CURSOR_ID: 1000 s->cursor.id = value; 1001 break; 1002 1003 case SVGA_REG_CURSOR_X: 1004 s->cursor.x = value; 1005 break; 1006 1007 case SVGA_REG_CURSOR_Y: 1008 s->cursor.y = value; 1009 break; 1010 1011 case SVGA_REG_CURSOR_ON: 1012 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 1013 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 1014 #ifdef HW_MOUSE_ACCEL 1015 if (value <= SVGA_CURSOR_ON_SHOW) { 1016 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); 1017 } 1018 #endif 1019 break; 1020 1021 case SVGA_REG_DEPTH: 1022 case SVGA_REG_MEM_REGS: 1023 case SVGA_REG_NUM_DISPLAYS: 1024 case SVGA_REG_PITCHLOCK: 1025 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 1026 break; 1027 1028 default: 1029 if (s->index >= SVGA_SCRATCH_BASE && 1030 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 1031 s->scratch[s->index - SVGA_SCRATCH_BASE] = value; 1032 break; 1033 } 1034 printf("%s: Bad register %02x\n", __func__, s->index); 1035 } 1036 } 1037 1038 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) 1039 { 1040 printf("%s: what are we supposed to return?\n", __func__); 1041 return 0xcafe; 1042 } 1043 1044 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) 1045 { 1046 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); 1047 } 1048 1049 static inline void vmsvga_check_size(struct vmsvga_state_s *s) 1050 { 1051 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1052 1053 if (s->new_width != surface_width(surface) || 1054 s->new_height != surface_height(surface) || 1055 s->new_depth != surface_bits_per_pixel(surface)) { 1056 int stride = (s->new_depth * s->new_width) / 8; 1057 pixman_format_code_t format = 1058 qemu_default_pixman_format(s->new_depth, true); 1059 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); 1060 surface = qemu_create_displaysurface_from(s->new_width, s->new_height, 1061 format, stride, 1062 s->vga.vram_ptr); 1063 dpy_gfx_replace_surface(s->vga.con, surface); 1064 s->invalidated = 1; 1065 } 1066 } 1067 1068 static void vmsvga_update_display(void *opaque) 1069 { 1070 struct vmsvga_state_s *s = opaque; 1071 DisplaySurface *surface; 1072 bool dirty = false; 1073 1074 if (!s->enable) { 1075 s->vga.hw_ops->gfx_update(&s->vga); 1076 return; 1077 } 1078 1079 vmsvga_check_size(s); 1080 surface = qemu_console_surface(s->vga.con); 1081 1082 vmsvga_fifo_run(s); 1083 vmsvga_update_rect_flush(s); 1084 1085 /* 1086 * Is it more efficient to look at vram VGA-dirty bits or wait 1087 * for the driver to issue SVGA_CMD_UPDATE? 1088 */ 1089 if (memory_region_is_logging(&s->vga.vram)) { 1090 vga_sync_dirty_bitmap(&s->vga); 1091 dirty = memory_region_get_dirty(&s->vga.vram, 0, 1092 surface_stride(surface) * surface_height(surface), 1093 DIRTY_MEMORY_VGA); 1094 } 1095 if (s->invalidated || dirty) { 1096 s->invalidated = 0; 1097 dpy_gfx_update(s->vga.con, 0, 0, 1098 surface_width(surface), surface_height(surface)); 1099 } 1100 if (dirty) { 1101 memory_region_reset_dirty(&s->vga.vram, 0, 1102 surface_stride(surface) * surface_height(surface), 1103 DIRTY_MEMORY_VGA); 1104 } 1105 } 1106 1107 static void vmsvga_reset(DeviceState *dev) 1108 { 1109 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev); 1110 struct vmsvga_state_s *s = &pci->chip; 1111 1112 s->index = 0; 1113 s->enable = 0; 1114 s->config = 0; 1115 s->svgaid = SVGA_ID; 1116 s->cursor.on = 0; 1117 s->redraw_fifo_first = 0; 1118 s->redraw_fifo_last = 0; 1119 s->syncing = 0; 1120 1121 vga_dirty_log_start(&s->vga); 1122 } 1123 1124 static void vmsvga_invalidate_display(void *opaque) 1125 { 1126 struct vmsvga_state_s *s = opaque; 1127 if (!s->enable) { 1128 s->vga.hw_ops->invalidate(&s->vga); 1129 return; 1130 } 1131 1132 s->invalidated = 1; 1133 } 1134 1135 static void vmsvga_text_update(void *opaque, console_ch_t *chardata) 1136 { 1137 struct vmsvga_state_s *s = opaque; 1138 1139 if (s->vga.hw_ops->text_update) { 1140 s->vga.hw_ops->text_update(&s->vga, chardata); 1141 } 1142 } 1143 1144 static int vmsvga_post_load(void *opaque, int version_id) 1145 { 1146 struct vmsvga_state_s *s = opaque; 1147 1148 s->invalidated = 1; 1149 if (s->config) { 1150 s->fifo = (uint32_t *) s->fifo_ptr; 1151 } 1152 return 0; 1153 } 1154 1155 static const VMStateDescription vmstate_vmware_vga_internal = { 1156 .name = "vmware_vga_internal", 1157 .version_id = 0, 1158 .minimum_version_id = 0, 1159 .post_load = vmsvga_post_load, 1160 .fields = (VMStateField[]) { 1161 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), 1162 VMSTATE_INT32(enable, struct vmsvga_state_s), 1163 VMSTATE_INT32(config, struct vmsvga_state_s), 1164 VMSTATE_INT32(cursor.id, struct vmsvga_state_s), 1165 VMSTATE_INT32(cursor.x, struct vmsvga_state_s), 1166 VMSTATE_INT32(cursor.y, struct vmsvga_state_s), 1167 VMSTATE_INT32(cursor.on, struct vmsvga_state_s), 1168 VMSTATE_INT32(index, struct vmsvga_state_s), 1169 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, 1170 scratch_size, 0, vmstate_info_uint32, uint32_t), 1171 VMSTATE_INT32(new_width, struct vmsvga_state_s), 1172 VMSTATE_INT32(new_height, struct vmsvga_state_s), 1173 VMSTATE_UINT32(guest, struct vmsvga_state_s), 1174 VMSTATE_UINT32(svgaid, struct vmsvga_state_s), 1175 VMSTATE_INT32(syncing, struct vmsvga_state_s), 1176 VMSTATE_UNUSED(4), /* was fb_size */ 1177 VMSTATE_END_OF_LIST() 1178 } 1179 }; 1180 1181 static const VMStateDescription vmstate_vmware_vga = { 1182 .name = "vmware_vga", 1183 .version_id = 0, 1184 .minimum_version_id = 0, 1185 .fields = (VMStateField[]) { 1186 VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s), 1187 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, 1188 vmstate_vmware_vga_internal, struct vmsvga_state_s), 1189 VMSTATE_END_OF_LIST() 1190 } 1191 }; 1192 1193 static const GraphicHwOps vmsvga_ops = { 1194 .invalidate = vmsvga_invalidate_display, 1195 .gfx_update = vmsvga_update_display, 1196 .text_update = vmsvga_text_update, 1197 }; 1198 1199 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, 1200 MemoryRegion *address_space, MemoryRegion *io) 1201 { 1202 s->scratch_size = SVGA_SCRATCH_SIZE; 1203 s->scratch = g_malloc(s->scratch_size * 4); 1204 1205 s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s); 1206 1207 s->fifo_size = SVGA_FIFO_SIZE; 1208 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, 1209 &error_abort); 1210 vmstate_register_ram_global(&s->fifo_ram); 1211 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); 1212 1213 vga_common_init(&s->vga, OBJECT(dev), true); 1214 vga_init(&s->vga, OBJECT(dev), address_space, io, true); 1215 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); 1216 s->new_depth = 32; 1217 } 1218 1219 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) 1220 { 1221 struct vmsvga_state_s *s = opaque; 1222 1223 switch (addr) { 1224 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); 1225 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); 1226 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); 1227 default: return -1u; 1228 } 1229 } 1230 1231 static void vmsvga_io_write(void *opaque, hwaddr addr, 1232 uint64_t data, unsigned size) 1233 { 1234 struct vmsvga_state_s *s = opaque; 1235 1236 switch (addr) { 1237 case SVGA_IO_MUL * SVGA_INDEX_PORT: 1238 vmsvga_index_write(s, addr, data); 1239 break; 1240 case SVGA_IO_MUL * SVGA_VALUE_PORT: 1241 vmsvga_value_write(s, addr, data); 1242 break; 1243 case SVGA_IO_MUL * SVGA_BIOS_PORT: 1244 vmsvga_bios_write(s, addr, data); 1245 break; 1246 } 1247 } 1248 1249 static const MemoryRegionOps vmsvga_io_ops = { 1250 .read = vmsvga_io_read, 1251 .write = vmsvga_io_write, 1252 .endianness = DEVICE_LITTLE_ENDIAN, 1253 .valid = { 1254 .min_access_size = 4, 1255 .max_access_size = 4, 1256 .unaligned = true, 1257 }, 1258 .impl = { 1259 .unaligned = true, 1260 }, 1261 }; 1262 1263 static int pci_vmsvga_initfn(PCIDevice *dev) 1264 { 1265 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev); 1266 1267 dev->config[PCI_CACHE_LINE_SIZE] = 0x08; 1268 dev->config[PCI_LATENCY_TIMER] = 0x40; 1269 dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */ 1270 1271 memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, 1272 "vmsvga-io", 0x10); 1273 memory_region_set_flush_coalesced(&s->io_bar); 1274 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1275 1276 vmsvga_init(DEVICE(dev), &s->chip, 1277 pci_address_space(dev), pci_address_space_io(dev)); 1278 1279 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, 1280 &s->chip.vga.vram); 1281 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, 1282 &s->chip.fifo_ram); 1283 1284 if (!dev->rom_bar) { 1285 /* compatibility with pc-0.13 and older */ 1286 vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev)); 1287 } 1288 1289 return 0; 1290 } 1291 1292 static Property vga_vmware_properties[] = { 1293 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, 1294 chip.vga.vram_size_mb, 16), 1295 DEFINE_PROP_END_OF_LIST(), 1296 }; 1297 1298 static void vmsvga_class_init(ObjectClass *klass, void *data) 1299 { 1300 DeviceClass *dc = DEVICE_CLASS(klass); 1301 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1302 1303 k->init = pci_vmsvga_initfn; 1304 k->romfile = "vgabios-vmware.bin"; 1305 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1306 k->device_id = SVGA_PCI_DEVICE_ID; 1307 k->class_id = PCI_CLASS_DISPLAY_VGA; 1308 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 1309 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1310 dc->reset = vmsvga_reset; 1311 dc->vmsd = &vmstate_vmware_vga; 1312 dc->props = vga_vmware_properties; 1313 dc->hotpluggable = false; 1314 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1315 } 1316 1317 static const TypeInfo vmsvga_info = { 1318 .name = TYPE_VMWARE_SVGA, 1319 .parent = TYPE_PCI_DEVICE, 1320 .instance_size = sizeof(struct pci_vmsvga_state_s), 1321 .class_init = vmsvga_class_init, 1322 }; 1323 1324 static void vmsvga_register_types(void) 1325 { 1326 type_register_static(&vmsvga_info); 1327 } 1328 1329 type_init(vmsvga_register_types) 1330