1 /* 2 * QEMU VMware-SVGA "chipset". 3 * 4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/loader.h" 26 #include "ui/console.h" 27 #include "hw/pci/pci.h" 28 29 #undef VERBOSE 30 #define HW_RECT_ACCEL 31 #define HW_FILL_ACCEL 32 #define HW_MOUSE_ACCEL 33 34 #include "vga_int.h" 35 36 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ 37 38 struct vmsvga_state_s { 39 VGACommonState vga; 40 41 int invalidated; 42 int depth; 43 int bypp; 44 int enable; 45 int config; 46 struct { 47 int id; 48 int x; 49 int y; 50 int on; 51 } cursor; 52 53 int index; 54 int scratch_size; 55 uint32_t *scratch; 56 int new_width; 57 int new_height; 58 uint32_t guest; 59 uint32_t svgaid; 60 int syncing; 61 62 MemoryRegion fifo_ram; 63 uint8_t *fifo_ptr; 64 unsigned int fifo_size; 65 66 union { 67 uint32_t *fifo; 68 struct QEMU_PACKED { 69 uint32_t min; 70 uint32_t max; 71 uint32_t next_cmd; 72 uint32_t stop; 73 /* Add registers here when adding capabilities. */ 74 uint32_t fifo[0]; 75 } *cmd; 76 }; 77 78 #define REDRAW_FIFO_LEN 512 79 struct vmsvga_rect_s { 80 int x, y, w, h; 81 } redraw_fifo[REDRAW_FIFO_LEN]; 82 int redraw_fifo_first, redraw_fifo_last; 83 }; 84 85 struct pci_vmsvga_state_s { 86 PCIDevice card; 87 struct vmsvga_state_s chip; 88 MemoryRegion io_bar; 89 }; 90 91 #define SVGA_MAGIC 0x900000UL 92 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 93 #define SVGA_ID_0 SVGA_MAKE_ID(0) 94 #define SVGA_ID_1 SVGA_MAKE_ID(1) 95 #define SVGA_ID_2 SVGA_MAKE_ID(2) 96 97 #define SVGA_LEGACY_BASE_PORT 0x4560 98 #define SVGA_INDEX_PORT 0x0 99 #define SVGA_VALUE_PORT 0x1 100 #define SVGA_BIOS_PORT 0x2 101 102 #define SVGA_VERSION_2 103 104 #ifdef SVGA_VERSION_2 105 # define SVGA_ID SVGA_ID_2 106 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 107 # define SVGA_IO_MUL 1 108 # define SVGA_FIFO_SIZE 0x10000 109 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 110 #else 111 # define SVGA_ID SVGA_ID_1 112 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 113 # define SVGA_IO_MUL 4 114 # define SVGA_FIFO_SIZE 0x10000 115 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA 116 #endif 117 118 enum { 119 /* ID 0, 1 and 2 registers */ 120 SVGA_REG_ID = 0, 121 SVGA_REG_ENABLE = 1, 122 SVGA_REG_WIDTH = 2, 123 SVGA_REG_HEIGHT = 3, 124 SVGA_REG_MAX_WIDTH = 4, 125 SVGA_REG_MAX_HEIGHT = 5, 126 SVGA_REG_DEPTH = 6, 127 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 128 SVGA_REG_PSEUDOCOLOR = 8, 129 SVGA_REG_RED_MASK = 9, 130 SVGA_REG_GREEN_MASK = 10, 131 SVGA_REG_BLUE_MASK = 11, 132 SVGA_REG_BYTES_PER_LINE = 12, 133 SVGA_REG_FB_START = 13, 134 SVGA_REG_FB_OFFSET = 14, 135 SVGA_REG_VRAM_SIZE = 15, 136 SVGA_REG_FB_SIZE = 16, 137 138 /* ID 1 and 2 registers */ 139 SVGA_REG_CAPABILITIES = 17, 140 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ 141 SVGA_REG_MEM_SIZE = 19, 142 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 143 SVGA_REG_SYNC = 21, /* Write to force synchronization */ 144 SVGA_REG_BUSY = 22, /* Read to check if sync is done */ 145 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 146 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ 147 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ 148 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ 149 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ 150 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ 151 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 152 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 153 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ 154 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 155 156 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 157 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, 158 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, 159 }; 160 161 #define SVGA_CAP_NONE 0 162 #define SVGA_CAP_RECT_FILL (1 << 0) 163 #define SVGA_CAP_RECT_COPY (1 << 1) 164 #define SVGA_CAP_RECT_PAT_FILL (1 << 2) 165 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) 166 #define SVGA_CAP_RASTER_OP (1 << 4) 167 #define SVGA_CAP_CURSOR (1 << 5) 168 #define SVGA_CAP_CURSOR_BYPASS (1 << 6) 169 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) 170 #define SVGA_CAP_8BIT_EMULATION (1 << 8) 171 #define SVGA_CAP_ALPHA_CURSOR (1 << 9) 172 #define SVGA_CAP_GLYPH (1 << 10) 173 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) 174 #define SVGA_CAP_OFFSCREEN_1 (1 << 12) 175 #define SVGA_CAP_ALPHA_BLEND (1 << 13) 176 #define SVGA_CAP_3D (1 << 14) 177 #define SVGA_CAP_EXTENDED_FIFO (1 << 15) 178 #define SVGA_CAP_MULTIMON (1 << 16) 179 #define SVGA_CAP_PITCHLOCK (1 << 17) 180 181 /* 182 * FIFO offsets (seen as an array of 32-bit words) 183 */ 184 enum { 185 /* 186 * The original defined FIFO offsets 187 */ 188 SVGA_FIFO_MIN = 0, 189 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 190 SVGA_FIFO_NEXT_CMD, 191 SVGA_FIFO_STOP, 192 193 /* 194 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO 195 */ 196 SVGA_FIFO_CAPABILITIES = 4, 197 SVGA_FIFO_FLAGS, 198 SVGA_FIFO_FENCE, 199 SVGA_FIFO_3D_HWVERSION, 200 SVGA_FIFO_PITCHLOCK, 201 }; 202 203 #define SVGA_FIFO_CAP_NONE 0 204 #define SVGA_FIFO_CAP_FENCE (1 << 0) 205 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 206 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 207 208 #define SVGA_FIFO_FLAG_NONE 0 209 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 210 211 /* These values can probably be changed arbitrarily. */ 212 #define SVGA_SCRATCH_SIZE 0x8000 213 #define SVGA_MAX_WIDTH 2360 214 #define SVGA_MAX_HEIGHT 1770 215 216 #ifdef VERBOSE 217 # define GUEST_OS_BASE 0x5001 218 static const char *vmsvga_guest_id[] = { 219 [0x00] = "Dos", 220 [0x01] = "Windows 3.1", 221 [0x02] = "Windows 95", 222 [0x03] = "Windows 98", 223 [0x04] = "Windows ME", 224 [0x05] = "Windows NT", 225 [0x06] = "Windows 2000", 226 [0x07] = "Linux", 227 [0x08] = "OS/2", 228 [0x09] = "an unknown OS", 229 [0x0a] = "BSD", 230 [0x0b] = "Whistler", 231 [0x0c] = "an unknown OS", 232 [0x0d] = "an unknown OS", 233 [0x0e] = "an unknown OS", 234 [0x0f] = "an unknown OS", 235 [0x10] = "an unknown OS", 236 [0x11] = "an unknown OS", 237 [0x12] = "an unknown OS", 238 [0x13] = "an unknown OS", 239 [0x14] = "an unknown OS", 240 [0x15] = "Windows 2003", 241 }; 242 #endif 243 244 enum { 245 SVGA_CMD_INVALID_CMD = 0, 246 SVGA_CMD_UPDATE = 1, 247 SVGA_CMD_RECT_FILL = 2, 248 SVGA_CMD_RECT_COPY = 3, 249 SVGA_CMD_DEFINE_BITMAP = 4, 250 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, 251 SVGA_CMD_DEFINE_PIXMAP = 6, 252 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, 253 SVGA_CMD_RECT_BITMAP_FILL = 8, 254 SVGA_CMD_RECT_PIXMAP_FILL = 9, 255 SVGA_CMD_RECT_BITMAP_COPY = 10, 256 SVGA_CMD_RECT_PIXMAP_COPY = 11, 257 SVGA_CMD_FREE_OBJECT = 12, 258 SVGA_CMD_RECT_ROP_FILL = 13, 259 SVGA_CMD_RECT_ROP_COPY = 14, 260 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, 261 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, 262 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, 263 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, 264 SVGA_CMD_DEFINE_CURSOR = 19, 265 SVGA_CMD_DISPLAY_CURSOR = 20, 266 SVGA_CMD_MOVE_CURSOR = 21, 267 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 268 SVGA_CMD_DRAW_GLYPH = 23, 269 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, 270 SVGA_CMD_UPDATE_VERBOSE = 25, 271 SVGA_CMD_SURFACE_FILL = 26, 272 SVGA_CMD_SURFACE_COPY = 27, 273 SVGA_CMD_SURFACE_ALPHA_BLEND = 28, 274 SVGA_CMD_FRONT_ROP_FILL = 29, 275 SVGA_CMD_FENCE = 30, 276 }; 277 278 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ 279 enum { 280 SVGA_CURSOR_ON_HIDE = 0, 281 SVGA_CURSOR_ON_SHOW = 1, 282 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, 283 SVGA_CURSOR_ON_RESTORE_TO_FB = 3, 284 }; 285 286 static inline void vmsvga_update_rect(struct vmsvga_state_s *s, 287 int x, int y, int w, int h) 288 { 289 DisplaySurface *surface = qemu_console_surface(s->vga.con); 290 int line; 291 int bypl; 292 int width; 293 int start; 294 uint8_t *src; 295 uint8_t *dst; 296 297 if (x < 0) { 298 fprintf(stderr, "%s: update x was < 0 (%d)\n", __func__, x); 299 w += x; 300 x = 0; 301 } 302 if (w < 0) { 303 fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w); 304 w = 0; 305 } 306 if (x + w > surface_width(surface)) { 307 fprintf(stderr, "%s: update width too large x: %d, w: %d\n", 308 __func__, x, w); 309 x = MIN(x, surface_width(surface)); 310 w = surface_width(surface) - x; 311 } 312 313 if (y < 0) { 314 fprintf(stderr, "%s: update y was < 0 (%d)\n", __func__, y); 315 h += y; 316 y = 0; 317 } 318 if (h < 0) { 319 fprintf(stderr, "%s: update h was < 0 (%d)\n", __func__, h); 320 h = 0; 321 } 322 if (y + h > surface_height(surface)) { 323 fprintf(stderr, "%s: update height too large y: %d, h: %d\n", 324 __func__, y, h); 325 y = MIN(y, surface_height(surface)); 326 h = surface_height(surface) - y; 327 } 328 329 bypl = surface_stride(surface); 330 width = surface_bytes_per_pixel(surface) * w; 331 start = surface_bytes_per_pixel(surface) * x + bypl * y; 332 src = s->vga.vram_ptr + start; 333 dst = surface_data(surface) + start; 334 335 for (line = h; line > 0; line--, src += bypl, dst += bypl) { 336 memcpy(dst, src, width); 337 } 338 dpy_gfx_update(s->vga.con, x, y, w, h); 339 } 340 341 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, 342 int x, int y, int w, int h) 343 { 344 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; 345 346 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; 347 rect->x = x; 348 rect->y = y; 349 rect->w = w; 350 rect->h = h; 351 } 352 353 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) 354 { 355 struct vmsvga_rect_s *rect; 356 357 if (s->invalidated) { 358 s->redraw_fifo_first = s->redraw_fifo_last; 359 return; 360 } 361 /* Overlapping region updates can be optimised out here - if someone 362 * knows a smart algorithm to do that, please share. */ 363 while (s->redraw_fifo_first != s->redraw_fifo_last) { 364 rect = &s->redraw_fifo[s->redraw_fifo_first++]; 365 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; 366 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); 367 } 368 } 369 370 #ifdef HW_RECT_ACCEL 371 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, 372 int x0, int y0, int x1, int y1, int w, int h) 373 { 374 DisplaySurface *surface = qemu_console_surface(s->vga.con); 375 uint8_t *vram = s->vga.vram_ptr; 376 int bypl = surface_stride(surface); 377 int bypp = surface_bytes_per_pixel(surface); 378 int width = bypp * w; 379 int line = h; 380 uint8_t *ptr[2]; 381 382 if (y1 > y0) { 383 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); 384 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); 385 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { 386 memmove(ptr[1], ptr[0], width); 387 } 388 } else { 389 ptr[0] = vram + bypp * x0 + bypl * y0; 390 ptr[1] = vram + bypp * x1 + bypl * y1; 391 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { 392 memmove(ptr[1], ptr[0], width); 393 } 394 } 395 396 vmsvga_update_rect_delayed(s, x1, y1, w, h); 397 } 398 #endif 399 400 #ifdef HW_FILL_ACCEL 401 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, 402 uint32_t c, int x, int y, int w, int h) 403 { 404 DisplaySurface *surface = qemu_console_surface(s->vga.con); 405 int bypl = surface_stride(surface); 406 int width = surface_bytes_per_pixel(surface) * w; 407 int line = h; 408 int column; 409 uint8_t *fst; 410 uint8_t *dst; 411 uint8_t *src; 412 uint8_t col[4]; 413 414 col[0] = c; 415 col[1] = c >> 8; 416 col[2] = c >> 16; 417 col[3] = c >> 24; 418 419 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; 420 421 if (line--) { 422 dst = fst; 423 src = col; 424 for (column = width; column > 0; column--) { 425 *(dst++) = *(src++); 426 if (src - col == surface_bytes_per_pixel(surface)) { 427 src = col; 428 } 429 } 430 dst = fst; 431 for (; line > 0; line--) { 432 dst += bypl; 433 memcpy(dst, fst, width); 434 } 435 } 436 437 vmsvga_update_rect_delayed(s, x, y, w, h); 438 } 439 #endif 440 441 struct vmsvga_cursor_definition_s { 442 int width; 443 int height; 444 int id; 445 int bpp; 446 int hot_x; 447 int hot_y; 448 uint32_t mask[1024]; 449 uint32_t image[4096]; 450 }; 451 452 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) 453 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) 454 455 #ifdef HW_MOUSE_ACCEL 456 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, 457 struct vmsvga_cursor_definition_s *c) 458 { 459 QEMUCursor *qc; 460 int i, pixels; 461 462 qc = cursor_alloc(c->width, c->height); 463 qc->hot_x = c->hot_x; 464 qc->hot_y = c->hot_y; 465 switch (c->bpp) { 466 case 1: 467 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, 468 1, (void *)c->mask); 469 #ifdef DEBUG 470 cursor_print_ascii_art(qc, "vmware/mono"); 471 #endif 472 break; 473 case 32: 474 /* fill alpha channel from mask, set color to zero */ 475 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, 476 1, (void *)c->mask); 477 /* add in rgb values */ 478 pixels = c->width * c->height; 479 for (i = 0; i < pixels; i++) { 480 qc->data[i] |= c->image[i] & 0xffffff; 481 } 482 #ifdef DEBUG 483 cursor_print_ascii_art(qc, "vmware/32bit"); 484 #endif 485 break; 486 default: 487 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", 488 __func__, c->bpp); 489 cursor_put(qc); 490 qc = cursor_builtin_left_ptr(); 491 } 492 493 dpy_cursor_define(s->vga.con, qc); 494 cursor_put(qc); 495 } 496 #endif 497 498 #define CMD(f) le32_to_cpu(s->cmd->f) 499 500 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) 501 { 502 int num; 503 504 if (!s->config || !s->enable) { 505 return 0; 506 } 507 num = CMD(next_cmd) - CMD(stop); 508 if (num < 0) { 509 num += CMD(max) - CMD(min); 510 } 511 return num >> 2; 512 } 513 514 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) 515 { 516 uint32_t cmd = s->fifo[CMD(stop) >> 2]; 517 518 s->cmd->stop = cpu_to_le32(CMD(stop) + 4); 519 if (CMD(stop) >= CMD(max)) { 520 s->cmd->stop = s->cmd->min; 521 } 522 return cmd; 523 } 524 525 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) 526 { 527 return le32_to_cpu(vmsvga_fifo_read_raw(s)); 528 } 529 530 static void vmsvga_fifo_run(struct vmsvga_state_s *s) 531 { 532 uint32_t cmd, colour; 533 int args, len; 534 int x, y, dx, dy, width, height; 535 struct vmsvga_cursor_definition_s cursor; 536 uint32_t cmd_start; 537 538 len = vmsvga_fifo_length(s); 539 while (len > 0) { 540 /* May need to go back to the start of the command if incomplete */ 541 cmd_start = s->cmd->stop; 542 543 switch (cmd = vmsvga_fifo_read(s)) { 544 case SVGA_CMD_UPDATE: 545 case SVGA_CMD_UPDATE_VERBOSE: 546 len -= 5; 547 if (len < 0) { 548 goto rewind; 549 } 550 551 x = vmsvga_fifo_read(s); 552 y = vmsvga_fifo_read(s); 553 width = vmsvga_fifo_read(s); 554 height = vmsvga_fifo_read(s); 555 vmsvga_update_rect_delayed(s, x, y, width, height); 556 break; 557 558 case SVGA_CMD_RECT_FILL: 559 len -= 6; 560 if (len < 0) { 561 goto rewind; 562 } 563 564 colour = vmsvga_fifo_read(s); 565 x = vmsvga_fifo_read(s); 566 y = vmsvga_fifo_read(s); 567 width = vmsvga_fifo_read(s); 568 height = vmsvga_fifo_read(s); 569 #ifdef HW_FILL_ACCEL 570 vmsvga_fill_rect(s, colour, x, y, width, height); 571 break; 572 #else 573 args = 0; 574 goto badcmd; 575 #endif 576 577 case SVGA_CMD_RECT_COPY: 578 len -= 7; 579 if (len < 0) { 580 goto rewind; 581 } 582 583 x = vmsvga_fifo_read(s); 584 y = vmsvga_fifo_read(s); 585 dx = vmsvga_fifo_read(s); 586 dy = vmsvga_fifo_read(s); 587 width = vmsvga_fifo_read(s); 588 height = vmsvga_fifo_read(s); 589 #ifdef HW_RECT_ACCEL 590 vmsvga_copy_rect(s, x, y, dx, dy, width, height); 591 break; 592 #else 593 args = 0; 594 goto badcmd; 595 #endif 596 597 case SVGA_CMD_DEFINE_CURSOR: 598 len -= 8; 599 if (len < 0) { 600 goto rewind; 601 } 602 603 cursor.id = vmsvga_fifo_read(s); 604 cursor.hot_x = vmsvga_fifo_read(s); 605 cursor.hot_y = vmsvga_fifo_read(s); 606 cursor.width = x = vmsvga_fifo_read(s); 607 cursor.height = y = vmsvga_fifo_read(s); 608 vmsvga_fifo_read(s); 609 cursor.bpp = vmsvga_fifo_read(s); 610 611 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); 612 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || 613 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { 614 goto badcmd; 615 } 616 617 len -= args; 618 if (len < 0) { 619 goto rewind; 620 } 621 622 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { 623 cursor.mask[args] = vmsvga_fifo_read_raw(s); 624 } 625 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { 626 cursor.image[args] = vmsvga_fifo_read_raw(s); 627 } 628 #ifdef HW_MOUSE_ACCEL 629 vmsvga_cursor_define(s, &cursor); 630 break; 631 #else 632 args = 0; 633 goto badcmd; 634 #endif 635 636 /* 637 * Other commands that we at least know the number of arguments 638 * for so we can avoid FIFO desync if driver uses them illegally. 639 */ 640 case SVGA_CMD_DEFINE_ALPHA_CURSOR: 641 len -= 6; 642 if (len < 0) { 643 goto rewind; 644 } 645 vmsvga_fifo_read(s); 646 vmsvga_fifo_read(s); 647 vmsvga_fifo_read(s); 648 x = vmsvga_fifo_read(s); 649 y = vmsvga_fifo_read(s); 650 args = x * y; 651 goto badcmd; 652 case SVGA_CMD_RECT_ROP_FILL: 653 args = 6; 654 goto badcmd; 655 case SVGA_CMD_RECT_ROP_COPY: 656 args = 7; 657 goto badcmd; 658 case SVGA_CMD_DRAW_GLYPH_CLIPPED: 659 len -= 4; 660 if (len < 0) { 661 goto rewind; 662 } 663 vmsvga_fifo_read(s); 664 vmsvga_fifo_read(s); 665 args = 7 + (vmsvga_fifo_read(s) >> 2); 666 goto badcmd; 667 case SVGA_CMD_SURFACE_ALPHA_BLEND: 668 args = 12; 669 goto badcmd; 670 671 /* 672 * Other commands that are not listed as depending on any 673 * CAPABILITIES bits, but are not described in the README either. 674 */ 675 case SVGA_CMD_SURFACE_FILL: 676 case SVGA_CMD_SURFACE_COPY: 677 case SVGA_CMD_FRONT_ROP_FILL: 678 case SVGA_CMD_FENCE: 679 case SVGA_CMD_INVALID_CMD: 680 break; /* Nop */ 681 682 default: 683 args = 0; 684 badcmd: 685 len -= args; 686 if (len < 0) { 687 goto rewind; 688 } 689 while (args--) { 690 vmsvga_fifo_read(s); 691 } 692 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", 693 __func__, cmd); 694 break; 695 696 rewind: 697 s->cmd->stop = cmd_start; 698 break; 699 } 700 } 701 702 s->syncing = 0; 703 } 704 705 static uint32_t vmsvga_index_read(void *opaque, uint32_t address) 706 { 707 struct vmsvga_state_s *s = opaque; 708 709 return s->index; 710 } 711 712 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) 713 { 714 struct vmsvga_state_s *s = opaque; 715 716 s->index = index; 717 } 718 719 static uint32_t vmsvga_value_read(void *opaque, uint32_t address) 720 { 721 uint32_t caps; 722 struct vmsvga_state_s *s = opaque; 723 DisplaySurface *surface = qemu_console_surface(s->vga.con); 724 uint32_t ret; 725 726 switch (s->index) { 727 case SVGA_REG_ID: 728 ret = s->svgaid; 729 break; 730 731 case SVGA_REG_ENABLE: 732 ret = s->enable; 733 break; 734 735 case SVGA_REG_WIDTH: 736 ret = surface_width(surface); 737 break; 738 739 case SVGA_REG_HEIGHT: 740 ret = surface_height(surface); 741 break; 742 743 case SVGA_REG_MAX_WIDTH: 744 ret = SVGA_MAX_WIDTH; 745 break; 746 747 case SVGA_REG_MAX_HEIGHT: 748 ret = SVGA_MAX_HEIGHT; 749 break; 750 751 case SVGA_REG_DEPTH: 752 ret = s->depth; 753 break; 754 755 case SVGA_REG_BITS_PER_PIXEL: 756 ret = (s->depth + 7) & ~7; 757 break; 758 759 case SVGA_REG_PSEUDOCOLOR: 760 ret = 0x0; 761 break; 762 763 case SVGA_REG_RED_MASK: 764 ret = surface->pf.rmask; 765 break; 766 767 case SVGA_REG_GREEN_MASK: 768 ret = surface->pf.gmask; 769 break; 770 771 case SVGA_REG_BLUE_MASK: 772 ret = surface->pf.bmask; 773 break; 774 775 case SVGA_REG_BYTES_PER_LINE: 776 ret = s->bypp * s->new_width; 777 break; 778 779 case SVGA_REG_FB_START: { 780 struct pci_vmsvga_state_s *pci_vmsvga 781 = container_of(s, struct pci_vmsvga_state_s, chip); 782 ret = pci_get_bar_addr(&pci_vmsvga->card, 1); 783 break; 784 } 785 786 case SVGA_REG_FB_OFFSET: 787 ret = 0x0; 788 break; 789 790 case SVGA_REG_VRAM_SIZE: 791 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ 792 break; 793 794 case SVGA_REG_FB_SIZE: 795 ret = s->vga.vram_size; 796 break; 797 798 case SVGA_REG_CAPABILITIES: 799 caps = SVGA_CAP_NONE; 800 #ifdef HW_RECT_ACCEL 801 caps |= SVGA_CAP_RECT_COPY; 802 #endif 803 #ifdef HW_FILL_ACCEL 804 caps |= SVGA_CAP_RECT_FILL; 805 #endif 806 #ifdef HW_MOUSE_ACCEL 807 if (dpy_cursor_define_supported(s->vga.con)) { 808 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 809 SVGA_CAP_CURSOR_BYPASS; 810 } 811 #endif 812 ret = caps; 813 break; 814 815 case SVGA_REG_MEM_START: { 816 struct pci_vmsvga_state_s *pci_vmsvga 817 = container_of(s, struct pci_vmsvga_state_s, chip); 818 ret = pci_get_bar_addr(&pci_vmsvga->card, 2); 819 break; 820 } 821 822 case SVGA_REG_MEM_SIZE: 823 ret = s->fifo_size; 824 break; 825 826 case SVGA_REG_CONFIG_DONE: 827 ret = s->config; 828 break; 829 830 case SVGA_REG_SYNC: 831 case SVGA_REG_BUSY: 832 ret = s->syncing; 833 break; 834 835 case SVGA_REG_GUEST_ID: 836 ret = s->guest; 837 break; 838 839 case SVGA_REG_CURSOR_ID: 840 ret = s->cursor.id; 841 break; 842 843 case SVGA_REG_CURSOR_X: 844 ret = s->cursor.x; 845 break; 846 847 case SVGA_REG_CURSOR_Y: 848 ret = s->cursor.x; 849 break; 850 851 case SVGA_REG_CURSOR_ON: 852 ret = s->cursor.on; 853 break; 854 855 case SVGA_REG_HOST_BITS_PER_PIXEL: 856 ret = (s->depth + 7) & ~7; 857 break; 858 859 case SVGA_REG_SCRATCH_SIZE: 860 ret = s->scratch_size; 861 break; 862 863 case SVGA_REG_MEM_REGS: 864 case SVGA_REG_NUM_DISPLAYS: 865 case SVGA_REG_PITCHLOCK: 866 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 867 ret = 0; 868 break; 869 870 default: 871 if (s->index >= SVGA_SCRATCH_BASE && 872 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 873 ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; 874 break; 875 } 876 printf("%s: Bad register %02x\n", __func__, s->index); 877 ret = 0; 878 break; 879 } 880 881 if (s->index >= SVGA_SCRATCH_BASE) { 882 trace_vmware_scratch_read(s->index, ret); 883 } else if (s->index >= SVGA_PALETTE_BASE) { 884 trace_vmware_palette_read(s->index, ret); 885 } else { 886 trace_vmware_value_read(s->index, ret); 887 } 888 return ret; 889 } 890 891 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) 892 { 893 struct vmsvga_state_s *s = opaque; 894 895 if (s->index >= SVGA_SCRATCH_BASE) { 896 trace_vmware_scratch_write(s->index, value); 897 } else if (s->index >= SVGA_PALETTE_BASE) { 898 trace_vmware_palette_write(s->index, value); 899 } else { 900 trace_vmware_value_write(s->index, value); 901 } 902 switch (s->index) { 903 case SVGA_REG_ID: 904 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { 905 s->svgaid = value; 906 } 907 break; 908 909 case SVGA_REG_ENABLE: 910 s->enable = !!value; 911 s->invalidated = 1; 912 s->vga.invalidate(&s->vga); 913 if (s->enable && s->config) { 914 vga_dirty_log_stop(&s->vga); 915 } else { 916 vga_dirty_log_start(&s->vga); 917 } 918 break; 919 920 case SVGA_REG_WIDTH: 921 if (value <= SVGA_MAX_WIDTH) { 922 s->new_width = value; 923 s->invalidated = 1; 924 } else { 925 printf("%s: Bad width: %i\n", __func__, value); 926 } 927 break; 928 929 case SVGA_REG_HEIGHT: 930 if (value <= SVGA_MAX_HEIGHT) { 931 s->new_height = value; 932 s->invalidated = 1; 933 } else { 934 printf("%s: Bad height: %i\n", __func__, value); 935 } 936 break; 937 938 case SVGA_REG_BITS_PER_PIXEL: 939 if (value != s->depth) { 940 printf("%s: Bad bits per pixel: %i bits\n", __func__, value); 941 s->config = 0; 942 } 943 break; 944 945 case SVGA_REG_CONFIG_DONE: 946 if (value) { 947 s->fifo = (uint32_t *) s->fifo_ptr; 948 /* Check range and alignment. */ 949 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { 950 break; 951 } 952 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { 953 break; 954 } 955 if (CMD(max) > SVGA_FIFO_SIZE) { 956 break; 957 } 958 if (CMD(max) < CMD(min) + 10 * 1024) { 959 break; 960 } 961 vga_dirty_log_stop(&s->vga); 962 } 963 s->config = !!value; 964 break; 965 966 case SVGA_REG_SYNC: 967 s->syncing = 1; 968 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ 969 break; 970 971 case SVGA_REG_GUEST_ID: 972 s->guest = value; 973 #ifdef VERBOSE 974 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + 975 ARRAY_SIZE(vmsvga_guest_id)) { 976 printf("%s: guest runs %s.\n", __func__, 977 vmsvga_guest_id[value - GUEST_OS_BASE]); 978 } 979 #endif 980 break; 981 982 case SVGA_REG_CURSOR_ID: 983 s->cursor.id = value; 984 break; 985 986 case SVGA_REG_CURSOR_X: 987 s->cursor.x = value; 988 break; 989 990 case SVGA_REG_CURSOR_Y: 991 s->cursor.y = value; 992 break; 993 994 case SVGA_REG_CURSOR_ON: 995 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 996 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 997 #ifdef HW_MOUSE_ACCEL 998 if (value <= SVGA_CURSOR_ON_SHOW) { 999 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); 1000 } 1001 #endif 1002 break; 1003 1004 case SVGA_REG_DEPTH: 1005 case SVGA_REG_MEM_REGS: 1006 case SVGA_REG_NUM_DISPLAYS: 1007 case SVGA_REG_PITCHLOCK: 1008 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 1009 break; 1010 1011 default: 1012 if (s->index >= SVGA_SCRATCH_BASE && 1013 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 1014 s->scratch[s->index - SVGA_SCRATCH_BASE] = value; 1015 break; 1016 } 1017 printf("%s: Bad register %02x\n", __func__, s->index); 1018 } 1019 } 1020 1021 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) 1022 { 1023 printf("%s: what are we supposed to return?\n", __func__); 1024 return 0xcafe; 1025 } 1026 1027 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) 1028 { 1029 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); 1030 } 1031 1032 static inline void vmsvga_check_size(struct vmsvga_state_s *s) 1033 { 1034 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1035 1036 if (s->new_width != surface_width(surface) || 1037 s->new_height != surface_height(surface)) { 1038 qemu_console_resize(s->vga.con, s->new_width, s->new_height); 1039 s->invalidated = 1; 1040 } 1041 } 1042 1043 static void vmsvga_update_display(void *opaque) 1044 { 1045 struct vmsvga_state_s *s = opaque; 1046 DisplaySurface *surface; 1047 bool dirty = false; 1048 1049 if (!s->enable) { 1050 s->vga.update(&s->vga); 1051 return; 1052 } 1053 1054 vmsvga_check_size(s); 1055 surface = qemu_console_surface(s->vga.con); 1056 1057 vmsvga_fifo_run(s); 1058 vmsvga_update_rect_flush(s); 1059 1060 /* 1061 * Is it more efficient to look at vram VGA-dirty bits or wait 1062 * for the driver to issue SVGA_CMD_UPDATE? 1063 */ 1064 if (memory_region_is_logging(&s->vga.vram)) { 1065 vga_sync_dirty_bitmap(&s->vga); 1066 dirty = memory_region_get_dirty(&s->vga.vram, 0, 1067 surface_stride(surface) * surface_height(surface), 1068 DIRTY_MEMORY_VGA); 1069 } 1070 if (s->invalidated || dirty) { 1071 s->invalidated = 0; 1072 memcpy(surface_data(surface), s->vga.vram_ptr, 1073 surface_stride(surface) * surface_height(surface)); 1074 dpy_gfx_update(s->vga.con, 0, 0, 1075 surface_width(surface), surface_height(surface)); 1076 } 1077 if (dirty) { 1078 memory_region_reset_dirty(&s->vga.vram, 0, 1079 surface_stride(surface) * surface_height(surface), 1080 DIRTY_MEMORY_VGA); 1081 } 1082 } 1083 1084 static void vmsvga_reset(DeviceState *dev) 1085 { 1086 struct pci_vmsvga_state_s *pci = 1087 DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev); 1088 struct vmsvga_state_s *s = &pci->chip; 1089 1090 s->index = 0; 1091 s->enable = 0; 1092 s->config = 0; 1093 s->svgaid = SVGA_ID; 1094 s->cursor.on = 0; 1095 s->redraw_fifo_first = 0; 1096 s->redraw_fifo_last = 0; 1097 s->syncing = 0; 1098 1099 vga_dirty_log_start(&s->vga); 1100 } 1101 1102 static void vmsvga_invalidate_display(void *opaque) 1103 { 1104 struct vmsvga_state_s *s = opaque; 1105 if (!s->enable) { 1106 s->vga.invalidate(&s->vga); 1107 return; 1108 } 1109 1110 s->invalidated = 1; 1111 } 1112 1113 /* save the vga display in a PPM image even if no display is 1114 available */ 1115 static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch, 1116 Error **errp) 1117 { 1118 struct vmsvga_state_s *s = opaque; 1119 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1120 1121 if (!s->enable) { 1122 s->vga.screen_dump(&s->vga, filename, cswitch, errp); 1123 return; 1124 } 1125 1126 if (surface_bits_per_pixel(surface) == 32) { 1127 DisplaySurface *ds = qemu_create_displaysurface_from( 1128 surface_width(surface), 1129 surface_height(surface), 1130 32, 1131 surface_stride(surface), 1132 s->vga.vram_ptr, false); 1133 ppm_save(filename, ds, errp); 1134 g_free(ds); 1135 } 1136 } 1137 1138 static void vmsvga_text_update(void *opaque, console_ch_t *chardata) 1139 { 1140 struct vmsvga_state_s *s = opaque; 1141 1142 if (s->vga.text_update) { 1143 s->vga.text_update(&s->vga, chardata); 1144 } 1145 } 1146 1147 static int vmsvga_post_load(void *opaque, int version_id) 1148 { 1149 struct vmsvga_state_s *s = opaque; 1150 1151 s->invalidated = 1; 1152 if (s->config) { 1153 s->fifo = (uint32_t *) s->fifo_ptr; 1154 } 1155 return 0; 1156 } 1157 1158 static const VMStateDescription vmstate_vmware_vga_internal = { 1159 .name = "vmware_vga_internal", 1160 .version_id = 0, 1161 .minimum_version_id = 0, 1162 .minimum_version_id_old = 0, 1163 .post_load = vmsvga_post_load, 1164 .fields = (VMStateField[]) { 1165 VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s), 1166 VMSTATE_INT32(enable, struct vmsvga_state_s), 1167 VMSTATE_INT32(config, struct vmsvga_state_s), 1168 VMSTATE_INT32(cursor.id, struct vmsvga_state_s), 1169 VMSTATE_INT32(cursor.x, struct vmsvga_state_s), 1170 VMSTATE_INT32(cursor.y, struct vmsvga_state_s), 1171 VMSTATE_INT32(cursor.on, struct vmsvga_state_s), 1172 VMSTATE_INT32(index, struct vmsvga_state_s), 1173 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, 1174 scratch_size, 0, vmstate_info_uint32, uint32_t), 1175 VMSTATE_INT32(new_width, struct vmsvga_state_s), 1176 VMSTATE_INT32(new_height, struct vmsvga_state_s), 1177 VMSTATE_UINT32(guest, struct vmsvga_state_s), 1178 VMSTATE_UINT32(svgaid, struct vmsvga_state_s), 1179 VMSTATE_INT32(syncing, struct vmsvga_state_s), 1180 VMSTATE_UNUSED(4), /* was fb_size */ 1181 VMSTATE_END_OF_LIST() 1182 } 1183 }; 1184 1185 static const VMStateDescription vmstate_vmware_vga = { 1186 .name = "vmware_vga", 1187 .version_id = 0, 1188 .minimum_version_id = 0, 1189 .minimum_version_id_old = 0, 1190 .fields = (VMStateField[]) { 1191 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s), 1192 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, 1193 vmstate_vmware_vga_internal, struct vmsvga_state_s), 1194 VMSTATE_END_OF_LIST() 1195 } 1196 }; 1197 1198 static void vmsvga_init(struct vmsvga_state_s *s, 1199 MemoryRegion *address_space, MemoryRegion *io) 1200 { 1201 DisplaySurface *surface; 1202 1203 s->scratch_size = SVGA_SCRATCH_SIZE; 1204 s->scratch = g_malloc(s->scratch_size * 4); 1205 1206 s->vga.con = graphic_console_init(vmsvga_update_display, 1207 vmsvga_invalidate_display, 1208 vmsvga_screen_dump, 1209 vmsvga_text_update, s); 1210 surface = qemu_console_surface(s->vga.con); 1211 1212 s->fifo_size = SVGA_FIFO_SIZE; 1213 memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size); 1214 vmstate_register_ram_global(&s->fifo_ram); 1215 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); 1216 1217 vga_common_init(&s->vga); 1218 vga_init(&s->vga, address_space, io, true); 1219 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); 1220 /* Save some values here in case they are changed later. 1221 * This is suspicious and needs more though why it is needed. */ 1222 s->depth = surface_bits_per_pixel(surface); 1223 s->bypp = surface_bytes_per_pixel(surface); 1224 } 1225 1226 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) 1227 { 1228 struct vmsvga_state_s *s = opaque; 1229 1230 switch (addr) { 1231 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); 1232 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); 1233 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); 1234 default: return -1u; 1235 } 1236 } 1237 1238 static void vmsvga_io_write(void *opaque, hwaddr addr, 1239 uint64_t data, unsigned size) 1240 { 1241 struct vmsvga_state_s *s = opaque; 1242 1243 switch (addr) { 1244 case SVGA_IO_MUL * SVGA_INDEX_PORT: 1245 vmsvga_index_write(s, addr, data); 1246 break; 1247 case SVGA_IO_MUL * SVGA_VALUE_PORT: 1248 vmsvga_value_write(s, addr, data); 1249 break; 1250 case SVGA_IO_MUL * SVGA_BIOS_PORT: 1251 vmsvga_bios_write(s, addr, data); 1252 break; 1253 } 1254 } 1255 1256 static const MemoryRegionOps vmsvga_io_ops = { 1257 .read = vmsvga_io_read, 1258 .write = vmsvga_io_write, 1259 .endianness = DEVICE_LITTLE_ENDIAN, 1260 .valid = { 1261 .min_access_size = 4, 1262 .max_access_size = 4, 1263 }, 1264 }; 1265 1266 static int pci_vmsvga_initfn(PCIDevice *dev) 1267 { 1268 struct pci_vmsvga_state_s *s = 1269 DO_UPCAST(struct pci_vmsvga_state_s, card, dev); 1270 1271 s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ 1272 s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ 1273 s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ 1274 1275 memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip, 1276 "vmsvga-io", 0x10); 1277 memory_region_set_flush_coalesced(&s->io_bar); 1278 pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1279 1280 vmsvga_init(&s->chip, pci_address_space(dev), pci_address_space_io(dev)); 1281 1282 pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, 1283 &s->chip.vga.vram); 1284 pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, 1285 &s->chip.fifo_ram); 1286 1287 if (!dev->rom_bar) { 1288 /* compatibility with pc-0.13 and older */ 1289 vga_init_vbe(&s->chip.vga, pci_address_space(dev)); 1290 } 1291 1292 return 0; 1293 } 1294 1295 static Property vga_vmware_properties[] = { 1296 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, 1297 chip.vga.vram_size_mb, 16), 1298 DEFINE_PROP_END_OF_LIST(), 1299 }; 1300 1301 static void vmsvga_class_init(ObjectClass *klass, void *data) 1302 { 1303 DeviceClass *dc = DEVICE_CLASS(klass); 1304 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1305 1306 k->no_hotplug = 1; 1307 k->init = pci_vmsvga_initfn; 1308 k->romfile = "vgabios-vmware.bin"; 1309 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1310 k->device_id = SVGA_PCI_DEVICE_ID; 1311 k->class_id = PCI_CLASS_DISPLAY_VGA; 1312 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 1313 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1314 dc->reset = vmsvga_reset; 1315 dc->vmsd = &vmstate_vmware_vga; 1316 dc->props = vga_vmware_properties; 1317 } 1318 1319 static const TypeInfo vmsvga_info = { 1320 .name = "vmware-svga", 1321 .parent = TYPE_PCI_DEVICE, 1322 .instance_size = sizeof(struct pci_vmsvga_state_s), 1323 .class_init = vmsvga_class_init, 1324 }; 1325 1326 static void vmsvga_register_types(void) 1327 { 1328 type_register_static(&vmsvga_info); 1329 } 1330 1331 type_init(vmsvga_register_types) 1332