1 /* 2 * QEMU VMware-SVGA "chipset". 3 * 4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/loader.h" 26 #include "trace.h" 27 #include "ui/console.h" 28 #include "ui/vnc.h" 29 #include "hw/pci/pci.h" 30 31 #undef VERBOSE 32 #define HW_RECT_ACCEL 33 #if 0 34 #define HW_FILL_ACCEL 35 #endif 36 #define HW_MOUSE_ACCEL 37 38 #include "vga_int.h" 39 40 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ 41 42 struct vmsvga_state_s { 43 VGACommonState vga; 44 45 int invalidated; 46 int enable; 47 int config; 48 struct { 49 int id; 50 int x; 51 int y; 52 int on; 53 } cursor; 54 55 int index; 56 int scratch_size; 57 uint32_t *scratch; 58 int new_width; 59 int new_height; 60 int new_depth; 61 uint32_t guest; 62 uint32_t svgaid; 63 int syncing; 64 65 MemoryRegion fifo_ram; 66 uint8_t *fifo_ptr; 67 unsigned int fifo_size; 68 69 union { 70 uint32_t *fifo; 71 struct QEMU_PACKED { 72 uint32_t min; 73 uint32_t max; 74 uint32_t next_cmd; 75 uint32_t stop; 76 /* Add registers here when adding capabilities. */ 77 uint32_t fifo[0]; 78 } *cmd; 79 }; 80 81 #define REDRAW_FIFO_LEN 512 82 struct vmsvga_rect_s { 83 int x, y, w, h; 84 } redraw_fifo[REDRAW_FIFO_LEN]; 85 int redraw_fifo_first, redraw_fifo_last; 86 }; 87 88 #define TYPE_VMWARE_SVGA "vmware-svga" 89 90 #define VMWARE_SVGA(obj) \ 91 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA) 92 93 struct pci_vmsvga_state_s { 94 /*< private >*/ 95 PCIDevice parent_obj; 96 /*< public >*/ 97 98 struct vmsvga_state_s chip; 99 MemoryRegion io_bar; 100 }; 101 102 #define SVGA_MAGIC 0x900000UL 103 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 104 #define SVGA_ID_0 SVGA_MAKE_ID(0) 105 #define SVGA_ID_1 SVGA_MAKE_ID(1) 106 #define SVGA_ID_2 SVGA_MAKE_ID(2) 107 108 #define SVGA_LEGACY_BASE_PORT 0x4560 109 #define SVGA_INDEX_PORT 0x0 110 #define SVGA_VALUE_PORT 0x1 111 #define SVGA_BIOS_PORT 0x2 112 113 #define SVGA_VERSION_2 114 115 #ifdef SVGA_VERSION_2 116 # define SVGA_ID SVGA_ID_2 117 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 118 # define SVGA_IO_MUL 1 119 # define SVGA_FIFO_SIZE 0x10000 120 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 121 #else 122 # define SVGA_ID SVGA_ID_1 123 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 124 # define SVGA_IO_MUL 4 125 # define SVGA_FIFO_SIZE 0x10000 126 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA 127 #endif 128 129 enum { 130 /* ID 0, 1 and 2 registers */ 131 SVGA_REG_ID = 0, 132 SVGA_REG_ENABLE = 1, 133 SVGA_REG_WIDTH = 2, 134 SVGA_REG_HEIGHT = 3, 135 SVGA_REG_MAX_WIDTH = 4, 136 SVGA_REG_MAX_HEIGHT = 5, 137 SVGA_REG_DEPTH = 6, 138 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 139 SVGA_REG_PSEUDOCOLOR = 8, 140 SVGA_REG_RED_MASK = 9, 141 SVGA_REG_GREEN_MASK = 10, 142 SVGA_REG_BLUE_MASK = 11, 143 SVGA_REG_BYTES_PER_LINE = 12, 144 SVGA_REG_FB_START = 13, 145 SVGA_REG_FB_OFFSET = 14, 146 SVGA_REG_VRAM_SIZE = 15, 147 SVGA_REG_FB_SIZE = 16, 148 149 /* ID 1 and 2 registers */ 150 SVGA_REG_CAPABILITIES = 17, 151 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ 152 SVGA_REG_MEM_SIZE = 19, 153 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 154 SVGA_REG_SYNC = 21, /* Write to force synchronization */ 155 SVGA_REG_BUSY = 22, /* Read to check if sync is done */ 156 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 157 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ 158 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ 159 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ 160 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ 161 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ 162 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 163 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 164 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ 165 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 166 167 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 168 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, 169 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, 170 }; 171 172 #define SVGA_CAP_NONE 0 173 #define SVGA_CAP_RECT_FILL (1 << 0) 174 #define SVGA_CAP_RECT_COPY (1 << 1) 175 #define SVGA_CAP_RECT_PAT_FILL (1 << 2) 176 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) 177 #define SVGA_CAP_RASTER_OP (1 << 4) 178 #define SVGA_CAP_CURSOR (1 << 5) 179 #define SVGA_CAP_CURSOR_BYPASS (1 << 6) 180 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) 181 #define SVGA_CAP_8BIT_EMULATION (1 << 8) 182 #define SVGA_CAP_ALPHA_CURSOR (1 << 9) 183 #define SVGA_CAP_GLYPH (1 << 10) 184 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) 185 #define SVGA_CAP_OFFSCREEN_1 (1 << 12) 186 #define SVGA_CAP_ALPHA_BLEND (1 << 13) 187 #define SVGA_CAP_3D (1 << 14) 188 #define SVGA_CAP_EXTENDED_FIFO (1 << 15) 189 #define SVGA_CAP_MULTIMON (1 << 16) 190 #define SVGA_CAP_PITCHLOCK (1 << 17) 191 192 /* 193 * FIFO offsets (seen as an array of 32-bit words) 194 */ 195 enum { 196 /* 197 * The original defined FIFO offsets 198 */ 199 SVGA_FIFO_MIN = 0, 200 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 201 SVGA_FIFO_NEXT_CMD, 202 SVGA_FIFO_STOP, 203 204 /* 205 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO 206 */ 207 SVGA_FIFO_CAPABILITIES = 4, 208 SVGA_FIFO_FLAGS, 209 SVGA_FIFO_FENCE, 210 SVGA_FIFO_3D_HWVERSION, 211 SVGA_FIFO_PITCHLOCK, 212 }; 213 214 #define SVGA_FIFO_CAP_NONE 0 215 #define SVGA_FIFO_CAP_FENCE (1 << 0) 216 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 217 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 218 219 #define SVGA_FIFO_FLAG_NONE 0 220 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 221 222 /* These values can probably be changed arbitrarily. */ 223 #define SVGA_SCRATCH_SIZE 0x8000 224 #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT) 225 #define SVGA_MAX_HEIGHT 1770 226 227 #ifdef VERBOSE 228 # define GUEST_OS_BASE 0x5001 229 static const char *vmsvga_guest_id[] = { 230 [0x00] = "Dos", 231 [0x01] = "Windows 3.1", 232 [0x02] = "Windows 95", 233 [0x03] = "Windows 98", 234 [0x04] = "Windows ME", 235 [0x05] = "Windows NT", 236 [0x06] = "Windows 2000", 237 [0x07] = "Linux", 238 [0x08] = "OS/2", 239 [0x09] = "an unknown OS", 240 [0x0a] = "BSD", 241 [0x0b] = "Whistler", 242 [0x0c] = "an unknown OS", 243 [0x0d] = "an unknown OS", 244 [0x0e] = "an unknown OS", 245 [0x0f] = "an unknown OS", 246 [0x10] = "an unknown OS", 247 [0x11] = "an unknown OS", 248 [0x12] = "an unknown OS", 249 [0x13] = "an unknown OS", 250 [0x14] = "an unknown OS", 251 [0x15] = "Windows 2003", 252 }; 253 #endif 254 255 enum { 256 SVGA_CMD_INVALID_CMD = 0, 257 SVGA_CMD_UPDATE = 1, 258 SVGA_CMD_RECT_FILL = 2, 259 SVGA_CMD_RECT_COPY = 3, 260 SVGA_CMD_DEFINE_BITMAP = 4, 261 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, 262 SVGA_CMD_DEFINE_PIXMAP = 6, 263 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, 264 SVGA_CMD_RECT_BITMAP_FILL = 8, 265 SVGA_CMD_RECT_PIXMAP_FILL = 9, 266 SVGA_CMD_RECT_BITMAP_COPY = 10, 267 SVGA_CMD_RECT_PIXMAP_COPY = 11, 268 SVGA_CMD_FREE_OBJECT = 12, 269 SVGA_CMD_RECT_ROP_FILL = 13, 270 SVGA_CMD_RECT_ROP_COPY = 14, 271 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, 272 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, 273 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, 274 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, 275 SVGA_CMD_DEFINE_CURSOR = 19, 276 SVGA_CMD_DISPLAY_CURSOR = 20, 277 SVGA_CMD_MOVE_CURSOR = 21, 278 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 279 SVGA_CMD_DRAW_GLYPH = 23, 280 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, 281 SVGA_CMD_UPDATE_VERBOSE = 25, 282 SVGA_CMD_SURFACE_FILL = 26, 283 SVGA_CMD_SURFACE_COPY = 27, 284 SVGA_CMD_SURFACE_ALPHA_BLEND = 28, 285 SVGA_CMD_FRONT_ROP_FILL = 29, 286 SVGA_CMD_FENCE = 30, 287 }; 288 289 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ 290 enum { 291 SVGA_CURSOR_ON_HIDE = 0, 292 SVGA_CURSOR_ON_SHOW = 1, 293 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, 294 SVGA_CURSOR_ON_RESTORE_TO_FB = 3, 295 }; 296 297 static inline bool vmsvga_verify_rect(DisplaySurface *surface, 298 const char *name, 299 int x, int y, int w, int h) 300 { 301 if (x < 0) { 302 fprintf(stderr, "%s: x was < 0 (%d)\n", name, x); 303 return false; 304 } 305 if (x > SVGA_MAX_WIDTH) { 306 fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x); 307 return false; 308 } 309 if (w < 0) { 310 fprintf(stderr, "%s: w was < 0 (%d)\n", name, w); 311 return false; 312 } 313 if (w > SVGA_MAX_WIDTH) { 314 fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w); 315 return false; 316 } 317 if (x + w > surface_width(surface)) { 318 fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n", 319 name, surface_width(surface), x, w); 320 return false; 321 } 322 323 if (y < 0) { 324 fprintf(stderr, "%s: y was < 0 (%d)\n", name, y); 325 return false; 326 } 327 if (y > SVGA_MAX_HEIGHT) { 328 fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y); 329 return false; 330 } 331 if (h < 0) { 332 fprintf(stderr, "%s: h was < 0 (%d)\n", name, h); 333 return false; 334 } 335 if (h > SVGA_MAX_HEIGHT) { 336 fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h); 337 return false; 338 } 339 if (y + h > surface_height(surface)) { 340 fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n", 341 name, surface_height(surface), y, h); 342 return false; 343 } 344 345 return true; 346 } 347 348 static inline void vmsvga_update_rect(struct vmsvga_state_s *s, 349 int x, int y, int w, int h) 350 { 351 DisplaySurface *surface = qemu_console_surface(s->vga.con); 352 int line; 353 int bypl; 354 int width; 355 int start; 356 uint8_t *src; 357 uint8_t *dst; 358 359 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { 360 /* go for a fullscreen update as fallback */ 361 x = 0; 362 y = 0; 363 w = surface_width(surface); 364 h = surface_height(surface); 365 } 366 367 bypl = surface_stride(surface); 368 width = surface_bytes_per_pixel(surface) * w; 369 start = surface_bytes_per_pixel(surface) * x + bypl * y; 370 src = s->vga.vram_ptr + start; 371 dst = surface_data(surface) + start; 372 373 for (line = h; line > 0; line--, src += bypl, dst += bypl) { 374 memcpy(dst, src, width); 375 } 376 dpy_gfx_update(s->vga.con, x, y, w, h); 377 } 378 379 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, 380 int x, int y, int w, int h) 381 { 382 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; 383 384 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; 385 rect->x = x; 386 rect->y = y; 387 rect->w = w; 388 rect->h = h; 389 } 390 391 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) 392 { 393 struct vmsvga_rect_s *rect; 394 395 if (s->invalidated) { 396 s->redraw_fifo_first = s->redraw_fifo_last; 397 return; 398 } 399 /* Overlapping region updates can be optimised out here - if someone 400 * knows a smart algorithm to do that, please share. */ 401 while (s->redraw_fifo_first != s->redraw_fifo_last) { 402 rect = &s->redraw_fifo[s->redraw_fifo_first++]; 403 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; 404 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); 405 } 406 } 407 408 #ifdef HW_RECT_ACCEL 409 static inline int vmsvga_copy_rect(struct vmsvga_state_s *s, 410 int x0, int y0, int x1, int y1, int w, int h) 411 { 412 DisplaySurface *surface = qemu_console_surface(s->vga.con); 413 uint8_t *vram = s->vga.vram_ptr; 414 int bypl = surface_stride(surface); 415 int bypp = surface_bytes_per_pixel(surface); 416 int width = bypp * w; 417 int line = h; 418 uint8_t *ptr[2]; 419 420 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) { 421 return -1; 422 } 423 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) { 424 return -1; 425 } 426 427 if (y1 > y0) { 428 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); 429 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); 430 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { 431 memmove(ptr[1], ptr[0], width); 432 } 433 } else { 434 ptr[0] = vram + bypp * x0 + bypl * y0; 435 ptr[1] = vram + bypp * x1 + bypl * y1; 436 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { 437 memmove(ptr[1], ptr[0], width); 438 } 439 } 440 441 vmsvga_update_rect_delayed(s, x1, y1, w, h); 442 return 0; 443 } 444 #endif 445 446 #ifdef HW_FILL_ACCEL 447 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, 448 uint32_t c, int x, int y, int w, int h) 449 { 450 DisplaySurface *surface = qemu_console_surface(s->vga.con); 451 int bypl = surface_stride(surface); 452 int width = surface_bytes_per_pixel(surface) * w; 453 int line = h; 454 int column; 455 uint8_t *fst; 456 uint8_t *dst; 457 uint8_t *src; 458 uint8_t col[4]; 459 460 col[0] = c; 461 col[1] = c >> 8; 462 col[2] = c >> 16; 463 col[3] = c >> 24; 464 465 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; 466 467 if (line--) { 468 dst = fst; 469 src = col; 470 for (column = width; column > 0; column--) { 471 *(dst++) = *(src++); 472 if (src - col == surface_bytes_per_pixel(surface)) { 473 src = col; 474 } 475 } 476 dst = fst; 477 for (; line > 0; line--) { 478 dst += bypl; 479 memcpy(dst, fst, width); 480 } 481 } 482 483 vmsvga_update_rect_delayed(s, x, y, w, h); 484 } 485 #endif 486 487 struct vmsvga_cursor_definition_s { 488 int width; 489 int height; 490 int id; 491 int bpp; 492 int hot_x; 493 int hot_y; 494 uint32_t mask[1024]; 495 uint32_t image[4096]; 496 }; 497 498 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) 499 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) 500 501 #ifdef HW_MOUSE_ACCEL 502 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, 503 struct vmsvga_cursor_definition_s *c) 504 { 505 QEMUCursor *qc; 506 int i, pixels; 507 508 qc = cursor_alloc(c->width, c->height); 509 qc->hot_x = c->hot_x; 510 qc->hot_y = c->hot_y; 511 switch (c->bpp) { 512 case 1: 513 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, 514 1, (void *)c->mask); 515 #ifdef DEBUG 516 cursor_print_ascii_art(qc, "vmware/mono"); 517 #endif 518 break; 519 case 32: 520 /* fill alpha channel from mask, set color to zero */ 521 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, 522 1, (void *)c->mask); 523 /* add in rgb values */ 524 pixels = c->width * c->height; 525 for (i = 0; i < pixels; i++) { 526 qc->data[i] |= c->image[i] & 0xffffff; 527 } 528 #ifdef DEBUG 529 cursor_print_ascii_art(qc, "vmware/32bit"); 530 #endif 531 break; 532 default: 533 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", 534 __func__, c->bpp); 535 cursor_put(qc); 536 qc = cursor_builtin_left_ptr(); 537 } 538 539 dpy_cursor_define(s->vga.con, qc); 540 cursor_put(qc); 541 } 542 #endif 543 544 #define CMD(f) le32_to_cpu(s->cmd->f) 545 546 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) 547 { 548 int num; 549 550 if (!s->config || !s->enable) { 551 return 0; 552 } 553 num = CMD(next_cmd) - CMD(stop); 554 if (num < 0) { 555 num += CMD(max) - CMD(min); 556 } 557 return num >> 2; 558 } 559 560 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) 561 { 562 uint32_t cmd = s->fifo[CMD(stop) >> 2]; 563 564 s->cmd->stop = cpu_to_le32(CMD(stop) + 4); 565 if (CMD(stop) >= CMD(max)) { 566 s->cmd->stop = s->cmd->min; 567 } 568 return cmd; 569 } 570 571 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) 572 { 573 return le32_to_cpu(vmsvga_fifo_read_raw(s)); 574 } 575 576 static void vmsvga_fifo_run(struct vmsvga_state_s *s) 577 { 578 uint32_t cmd, colour; 579 int args, len; 580 int x, y, dx, dy, width, height; 581 struct vmsvga_cursor_definition_s cursor; 582 uint32_t cmd_start; 583 584 len = vmsvga_fifo_length(s); 585 while (len > 0) { 586 /* May need to go back to the start of the command if incomplete */ 587 cmd_start = s->cmd->stop; 588 589 switch (cmd = vmsvga_fifo_read(s)) { 590 case SVGA_CMD_UPDATE: 591 case SVGA_CMD_UPDATE_VERBOSE: 592 len -= 5; 593 if (len < 0) { 594 goto rewind; 595 } 596 597 x = vmsvga_fifo_read(s); 598 y = vmsvga_fifo_read(s); 599 width = vmsvga_fifo_read(s); 600 height = vmsvga_fifo_read(s); 601 vmsvga_update_rect_delayed(s, x, y, width, height); 602 break; 603 604 case SVGA_CMD_RECT_FILL: 605 len -= 6; 606 if (len < 0) { 607 goto rewind; 608 } 609 610 colour = vmsvga_fifo_read(s); 611 x = vmsvga_fifo_read(s); 612 y = vmsvga_fifo_read(s); 613 width = vmsvga_fifo_read(s); 614 height = vmsvga_fifo_read(s); 615 #ifdef HW_FILL_ACCEL 616 vmsvga_fill_rect(s, colour, x, y, width, height); 617 break; 618 #else 619 args = 0; 620 goto badcmd; 621 #endif 622 623 case SVGA_CMD_RECT_COPY: 624 len -= 7; 625 if (len < 0) { 626 goto rewind; 627 } 628 629 x = vmsvga_fifo_read(s); 630 y = vmsvga_fifo_read(s); 631 dx = vmsvga_fifo_read(s); 632 dy = vmsvga_fifo_read(s); 633 width = vmsvga_fifo_read(s); 634 height = vmsvga_fifo_read(s); 635 #ifdef HW_RECT_ACCEL 636 if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) { 637 break; 638 } 639 #endif 640 args = 0; 641 goto badcmd; 642 643 case SVGA_CMD_DEFINE_CURSOR: 644 len -= 8; 645 if (len < 0) { 646 goto rewind; 647 } 648 649 cursor.id = vmsvga_fifo_read(s); 650 cursor.hot_x = vmsvga_fifo_read(s); 651 cursor.hot_y = vmsvga_fifo_read(s); 652 cursor.width = x = vmsvga_fifo_read(s); 653 cursor.height = y = vmsvga_fifo_read(s); 654 vmsvga_fifo_read(s); 655 cursor.bpp = vmsvga_fifo_read(s); 656 657 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); 658 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || 659 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { 660 goto badcmd; 661 } 662 663 len -= args; 664 if (len < 0) { 665 goto rewind; 666 } 667 668 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { 669 cursor.mask[args] = vmsvga_fifo_read_raw(s); 670 } 671 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { 672 cursor.image[args] = vmsvga_fifo_read_raw(s); 673 } 674 #ifdef HW_MOUSE_ACCEL 675 vmsvga_cursor_define(s, &cursor); 676 break; 677 #else 678 args = 0; 679 goto badcmd; 680 #endif 681 682 /* 683 * Other commands that we at least know the number of arguments 684 * for so we can avoid FIFO desync if driver uses them illegally. 685 */ 686 case SVGA_CMD_DEFINE_ALPHA_CURSOR: 687 len -= 6; 688 if (len < 0) { 689 goto rewind; 690 } 691 vmsvga_fifo_read(s); 692 vmsvga_fifo_read(s); 693 vmsvga_fifo_read(s); 694 x = vmsvga_fifo_read(s); 695 y = vmsvga_fifo_read(s); 696 args = x * y; 697 goto badcmd; 698 case SVGA_CMD_RECT_ROP_FILL: 699 args = 6; 700 goto badcmd; 701 case SVGA_CMD_RECT_ROP_COPY: 702 args = 7; 703 goto badcmd; 704 case SVGA_CMD_DRAW_GLYPH_CLIPPED: 705 len -= 4; 706 if (len < 0) { 707 goto rewind; 708 } 709 vmsvga_fifo_read(s); 710 vmsvga_fifo_read(s); 711 args = 7 + (vmsvga_fifo_read(s) >> 2); 712 goto badcmd; 713 case SVGA_CMD_SURFACE_ALPHA_BLEND: 714 args = 12; 715 goto badcmd; 716 717 /* 718 * Other commands that are not listed as depending on any 719 * CAPABILITIES bits, but are not described in the README either. 720 */ 721 case SVGA_CMD_SURFACE_FILL: 722 case SVGA_CMD_SURFACE_COPY: 723 case SVGA_CMD_FRONT_ROP_FILL: 724 case SVGA_CMD_FENCE: 725 case SVGA_CMD_INVALID_CMD: 726 break; /* Nop */ 727 728 default: 729 args = 0; 730 badcmd: 731 len -= args; 732 if (len < 0) { 733 goto rewind; 734 } 735 while (args--) { 736 vmsvga_fifo_read(s); 737 } 738 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", 739 __func__, cmd); 740 break; 741 742 rewind: 743 s->cmd->stop = cmd_start; 744 break; 745 } 746 } 747 748 s->syncing = 0; 749 } 750 751 static uint32_t vmsvga_index_read(void *opaque, uint32_t address) 752 { 753 struct vmsvga_state_s *s = opaque; 754 755 return s->index; 756 } 757 758 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) 759 { 760 struct vmsvga_state_s *s = opaque; 761 762 s->index = index; 763 } 764 765 static uint32_t vmsvga_value_read(void *opaque, uint32_t address) 766 { 767 uint32_t caps; 768 struct vmsvga_state_s *s = opaque; 769 DisplaySurface *surface = qemu_console_surface(s->vga.con); 770 PixelFormat pf; 771 uint32_t ret; 772 773 switch (s->index) { 774 case SVGA_REG_ID: 775 ret = s->svgaid; 776 break; 777 778 case SVGA_REG_ENABLE: 779 ret = s->enable; 780 break; 781 782 case SVGA_REG_WIDTH: 783 ret = s->new_width ? s->new_width : surface_width(surface); 784 break; 785 786 case SVGA_REG_HEIGHT: 787 ret = s->new_height ? s->new_height : surface_height(surface); 788 break; 789 790 case SVGA_REG_MAX_WIDTH: 791 ret = SVGA_MAX_WIDTH; 792 break; 793 794 case SVGA_REG_MAX_HEIGHT: 795 ret = SVGA_MAX_HEIGHT; 796 break; 797 798 case SVGA_REG_DEPTH: 799 ret = (s->new_depth == 32) ? 24 : s->new_depth; 800 break; 801 802 case SVGA_REG_BITS_PER_PIXEL: 803 case SVGA_REG_HOST_BITS_PER_PIXEL: 804 ret = s->new_depth; 805 break; 806 807 case SVGA_REG_PSEUDOCOLOR: 808 ret = 0x0; 809 break; 810 811 case SVGA_REG_RED_MASK: 812 pf = qemu_default_pixelformat(s->new_depth); 813 ret = pf.rmask; 814 break; 815 816 case SVGA_REG_GREEN_MASK: 817 pf = qemu_default_pixelformat(s->new_depth); 818 ret = pf.gmask; 819 break; 820 821 case SVGA_REG_BLUE_MASK: 822 pf = qemu_default_pixelformat(s->new_depth); 823 ret = pf.bmask; 824 break; 825 826 case SVGA_REG_BYTES_PER_LINE: 827 if (s->new_width) { 828 ret = (s->new_depth * s->new_width) / 8; 829 } else { 830 ret = surface_stride(surface); 831 } 832 break; 833 834 case SVGA_REG_FB_START: { 835 struct pci_vmsvga_state_s *pci_vmsvga 836 = container_of(s, struct pci_vmsvga_state_s, chip); 837 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1); 838 break; 839 } 840 841 case SVGA_REG_FB_OFFSET: 842 ret = 0x0; 843 break; 844 845 case SVGA_REG_VRAM_SIZE: 846 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ 847 break; 848 849 case SVGA_REG_FB_SIZE: 850 ret = s->vga.vram_size; 851 break; 852 853 case SVGA_REG_CAPABILITIES: 854 caps = SVGA_CAP_NONE; 855 #ifdef HW_RECT_ACCEL 856 caps |= SVGA_CAP_RECT_COPY; 857 #endif 858 #ifdef HW_FILL_ACCEL 859 caps |= SVGA_CAP_RECT_FILL; 860 #endif 861 #ifdef HW_MOUSE_ACCEL 862 if (dpy_cursor_define_supported(s->vga.con)) { 863 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 864 SVGA_CAP_CURSOR_BYPASS; 865 } 866 #endif 867 ret = caps; 868 break; 869 870 case SVGA_REG_MEM_START: { 871 struct pci_vmsvga_state_s *pci_vmsvga 872 = container_of(s, struct pci_vmsvga_state_s, chip); 873 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2); 874 break; 875 } 876 877 case SVGA_REG_MEM_SIZE: 878 ret = s->fifo_size; 879 break; 880 881 case SVGA_REG_CONFIG_DONE: 882 ret = s->config; 883 break; 884 885 case SVGA_REG_SYNC: 886 case SVGA_REG_BUSY: 887 ret = s->syncing; 888 break; 889 890 case SVGA_REG_GUEST_ID: 891 ret = s->guest; 892 break; 893 894 case SVGA_REG_CURSOR_ID: 895 ret = s->cursor.id; 896 break; 897 898 case SVGA_REG_CURSOR_X: 899 ret = s->cursor.x; 900 break; 901 902 case SVGA_REG_CURSOR_Y: 903 ret = s->cursor.y; 904 break; 905 906 case SVGA_REG_CURSOR_ON: 907 ret = s->cursor.on; 908 break; 909 910 case SVGA_REG_SCRATCH_SIZE: 911 ret = s->scratch_size; 912 break; 913 914 case SVGA_REG_MEM_REGS: 915 case SVGA_REG_NUM_DISPLAYS: 916 case SVGA_REG_PITCHLOCK: 917 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 918 ret = 0; 919 break; 920 921 default: 922 if (s->index >= SVGA_SCRATCH_BASE && 923 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 924 ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; 925 break; 926 } 927 printf("%s: Bad register %02x\n", __func__, s->index); 928 ret = 0; 929 break; 930 } 931 932 if (s->index >= SVGA_SCRATCH_BASE) { 933 trace_vmware_scratch_read(s->index, ret); 934 } else if (s->index >= SVGA_PALETTE_BASE) { 935 trace_vmware_palette_read(s->index, ret); 936 } else { 937 trace_vmware_value_read(s->index, ret); 938 } 939 return ret; 940 } 941 942 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) 943 { 944 struct vmsvga_state_s *s = opaque; 945 946 if (s->index >= SVGA_SCRATCH_BASE) { 947 trace_vmware_scratch_write(s->index, value); 948 } else if (s->index >= SVGA_PALETTE_BASE) { 949 trace_vmware_palette_write(s->index, value); 950 } else { 951 trace_vmware_value_write(s->index, value); 952 } 953 switch (s->index) { 954 case SVGA_REG_ID: 955 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { 956 s->svgaid = value; 957 } 958 break; 959 960 case SVGA_REG_ENABLE: 961 s->enable = !!value; 962 s->invalidated = 1; 963 s->vga.hw_ops->invalidate(&s->vga); 964 if (s->enable && s->config) { 965 vga_dirty_log_stop(&s->vga); 966 } else { 967 vga_dirty_log_start(&s->vga); 968 } 969 break; 970 971 case SVGA_REG_WIDTH: 972 if (value <= SVGA_MAX_WIDTH) { 973 s->new_width = value; 974 s->invalidated = 1; 975 } else { 976 printf("%s: Bad width: %i\n", __func__, value); 977 } 978 break; 979 980 case SVGA_REG_HEIGHT: 981 if (value <= SVGA_MAX_HEIGHT) { 982 s->new_height = value; 983 s->invalidated = 1; 984 } else { 985 printf("%s: Bad height: %i\n", __func__, value); 986 } 987 break; 988 989 case SVGA_REG_BITS_PER_PIXEL: 990 if (value != 32) { 991 printf("%s: Bad bits per pixel: %i bits\n", __func__, value); 992 s->config = 0; 993 s->invalidated = 1; 994 } 995 break; 996 997 case SVGA_REG_CONFIG_DONE: 998 if (value) { 999 s->fifo = (uint32_t *) s->fifo_ptr; 1000 /* Check range and alignment. */ 1001 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { 1002 break; 1003 } 1004 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { 1005 break; 1006 } 1007 if (CMD(max) > SVGA_FIFO_SIZE) { 1008 break; 1009 } 1010 if (CMD(max) < CMD(min) + 10 * 1024) { 1011 break; 1012 } 1013 vga_dirty_log_stop(&s->vga); 1014 } 1015 s->config = !!value; 1016 break; 1017 1018 case SVGA_REG_SYNC: 1019 s->syncing = 1; 1020 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ 1021 break; 1022 1023 case SVGA_REG_GUEST_ID: 1024 s->guest = value; 1025 #ifdef VERBOSE 1026 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + 1027 ARRAY_SIZE(vmsvga_guest_id)) { 1028 printf("%s: guest runs %s.\n", __func__, 1029 vmsvga_guest_id[value - GUEST_OS_BASE]); 1030 } 1031 #endif 1032 break; 1033 1034 case SVGA_REG_CURSOR_ID: 1035 s->cursor.id = value; 1036 break; 1037 1038 case SVGA_REG_CURSOR_X: 1039 s->cursor.x = value; 1040 break; 1041 1042 case SVGA_REG_CURSOR_Y: 1043 s->cursor.y = value; 1044 break; 1045 1046 case SVGA_REG_CURSOR_ON: 1047 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 1048 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 1049 #ifdef HW_MOUSE_ACCEL 1050 if (value <= SVGA_CURSOR_ON_SHOW) { 1051 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); 1052 } 1053 #endif 1054 break; 1055 1056 case SVGA_REG_DEPTH: 1057 case SVGA_REG_MEM_REGS: 1058 case SVGA_REG_NUM_DISPLAYS: 1059 case SVGA_REG_PITCHLOCK: 1060 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 1061 break; 1062 1063 default: 1064 if (s->index >= SVGA_SCRATCH_BASE && 1065 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 1066 s->scratch[s->index - SVGA_SCRATCH_BASE] = value; 1067 break; 1068 } 1069 printf("%s: Bad register %02x\n", __func__, s->index); 1070 } 1071 } 1072 1073 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) 1074 { 1075 printf("%s: what are we supposed to return?\n", __func__); 1076 return 0xcafe; 1077 } 1078 1079 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) 1080 { 1081 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); 1082 } 1083 1084 static inline void vmsvga_check_size(struct vmsvga_state_s *s) 1085 { 1086 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1087 1088 if (s->new_width != surface_width(surface) || 1089 s->new_height != surface_height(surface) || 1090 s->new_depth != surface_bits_per_pixel(surface)) { 1091 int stride = (s->new_depth * s->new_width) / 8; 1092 pixman_format_code_t format = 1093 qemu_default_pixman_format(s->new_depth, true); 1094 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); 1095 surface = qemu_create_displaysurface_from(s->new_width, s->new_height, 1096 format, stride, 1097 s->vga.vram_ptr); 1098 dpy_gfx_replace_surface(s->vga.con, surface); 1099 s->invalidated = 1; 1100 } 1101 } 1102 1103 static void vmsvga_update_display(void *opaque) 1104 { 1105 struct vmsvga_state_s *s = opaque; 1106 DisplaySurface *surface; 1107 bool dirty = false; 1108 1109 if (!s->enable) { 1110 s->vga.hw_ops->gfx_update(&s->vga); 1111 return; 1112 } 1113 1114 vmsvga_check_size(s); 1115 surface = qemu_console_surface(s->vga.con); 1116 1117 vmsvga_fifo_run(s); 1118 vmsvga_update_rect_flush(s); 1119 1120 /* 1121 * Is it more efficient to look at vram VGA-dirty bits or wait 1122 * for the driver to issue SVGA_CMD_UPDATE? 1123 */ 1124 if (memory_region_is_logging(&s->vga.vram)) { 1125 vga_sync_dirty_bitmap(&s->vga); 1126 dirty = memory_region_get_dirty(&s->vga.vram, 0, 1127 surface_stride(surface) * surface_height(surface), 1128 DIRTY_MEMORY_VGA); 1129 } 1130 if (s->invalidated || dirty) { 1131 s->invalidated = 0; 1132 dpy_gfx_update(s->vga.con, 0, 0, 1133 surface_width(surface), surface_height(surface)); 1134 } 1135 if (dirty) { 1136 memory_region_reset_dirty(&s->vga.vram, 0, 1137 surface_stride(surface) * surface_height(surface), 1138 DIRTY_MEMORY_VGA); 1139 } 1140 } 1141 1142 static void vmsvga_reset(DeviceState *dev) 1143 { 1144 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev); 1145 struct vmsvga_state_s *s = &pci->chip; 1146 1147 s->index = 0; 1148 s->enable = 0; 1149 s->config = 0; 1150 s->svgaid = SVGA_ID; 1151 s->cursor.on = 0; 1152 s->redraw_fifo_first = 0; 1153 s->redraw_fifo_last = 0; 1154 s->syncing = 0; 1155 1156 vga_dirty_log_start(&s->vga); 1157 } 1158 1159 static void vmsvga_invalidate_display(void *opaque) 1160 { 1161 struct vmsvga_state_s *s = opaque; 1162 if (!s->enable) { 1163 s->vga.hw_ops->invalidate(&s->vga); 1164 return; 1165 } 1166 1167 s->invalidated = 1; 1168 } 1169 1170 static void vmsvga_text_update(void *opaque, console_ch_t *chardata) 1171 { 1172 struct vmsvga_state_s *s = opaque; 1173 1174 if (s->vga.hw_ops->text_update) { 1175 s->vga.hw_ops->text_update(&s->vga, chardata); 1176 } 1177 } 1178 1179 static int vmsvga_post_load(void *opaque, int version_id) 1180 { 1181 struct vmsvga_state_s *s = opaque; 1182 1183 s->invalidated = 1; 1184 if (s->config) { 1185 s->fifo = (uint32_t *) s->fifo_ptr; 1186 } 1187 return 0; 1188 } 1189 1190 static const VMStateDescription vmstate_vmware_vga_internal = { 1191 .name = "vmware_vga_internal", 1192 .version_id = 0, 1193 .minimum_version_id = 0, 1194 .post_load = vmsvga_post_load, 1195 .fields = (VMStateField[]) { 1196 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), 1197 VMSTATE_INT32(enable, struct vmsvga_state_s), 1198 VMSTATE_INT32(config, struct vmsvga_state_s), 1199 VMSTATE_INT32(cursor.id, struct vmsvga_state_s), 1200 VMSTATE_INT32(cursor.x, struct vmsvga_state_s), 1201 VMSTATE_INT32(cursor.y, struct vmsvga_state_s), 1202 VMSTATE_INT32(cursor.on, struct vmsvga_state_s), 1203 VMSTATE_INT32(index, struct vmsvga_state_s), 1204 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, 1205 scratch_size, 0, vmstate_info_uint32, uint32_t), 1206 VMSTATE_INT32(new_width, struct vmsvga_state_s), 1207 VMSTATE_INT32(new_height, struct vmsvga_state_s), 1208 VMSTATE_UINT32(guest, struct vmsvga_state_s), 1209 VMSTATE_UINT32(svgaid, struct vmsvga_state_s), 1210 VMSTATE_INT32(syncing, struct vmsvga_state_s), 1211 VMSTATE_UNUSED(4), /* was fb_size */ 1212 VMSTATE_END_OF_LIST() 1213 } 1214 }; 1215 1216 static const VMStateDescription vmstate_vmware_vga = { 1217 .name = "vmware_vga", 1218 .version_id = 0, 1219 .minimum_version_id = 0, 1220 .fields = (VMStateField[]) { 1221 VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s), 1222 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, 1223 vmstate_vmware_vga_internal, struct vmsvga_state_s), 1224 VMSTATE_END_OF_LIST() 1225 } 1226 }; 1227 1228 static const GraphicHwOps vmsvga_ops = { 1229 .invalidate = vmsvga_invalidate_display, 1230 .gfx_update = vmsvga_update_display, 1231 .text_update = vmsvga_text_update, 1232 }; 1233 1234 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, 1235 MemoryRegion *address_space, MemoryRegion *io) 1236 { 1237 s->scratch_size = SVGA_SCRATCH_SIZE; 1238 s->scratch = g_malloc(s->scratch_size * 4); 1239 1240 s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s); 1241 1242 s->fifo_size = SVGA_FIFO_SIZE; 1243 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, 1244 &error_abort); 1245 vmstate_register_ram_global(&s->fifo_ram); 1246 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); 1247 1248 vga_common_init(&s->vga, OBJECT(dev), true); 1249 vga_init(&s->vga, OBJECT(dev), address_space, io, true); 1250 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); 1251 s->new_depth = 32; 1252 } 1253 1254 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) 1255 { 1256 struct vmsvga_state_s *s = opaque; 1257 1258 switch (addr) { 1259 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); 1260 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); 1261 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); 1262 default: return -1u; 1263 } 1264 } 1265 1266 static void vmsvga_io_write(void *opaque, hwaddr addr, 1267 uint64_t data, unsigned size) 1268 { 1269 struct vmsvga_state_s *s = opaque; 1270 1271 switch (addr) { 1272 case SVGA_IO_MUL * SVGA_INDEX_PORT: 1273 vmsvga_index_write(s, addr, data); 1274 break; 1275 case SVGA_IO_MUL * SVGA_VALUE_PORT: 1276 vmsvga_value_write(s, addr, data); 1277 break; 1278 case SVGA_IO_MUL * SVGA_BIOS_PORT: 1279 vmsvga_bios_write(s, addr, data); 1280 break; 1281 } 1282 } 1283 1284 static const MemoryRegionOps vmsvga_io_ops = { 1285 .read = vmsvga_io_read, 1286 .write = vmsvga_io_write, 1287 .endianness = DEVICE_LITTLE_ENDIAN, 1288 .valid = { 1289 .min_access_size = 4, 1290 .max_access_size = 4, 1291 .unaligned = true, 1292 }, 1293 .impl = { 1294 .unaligned = true, 1295 }, 1296 }; 1297 1298 static int pci_vmsvga_initfn(PCIDevice *dev) 1299 { 1300 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev); 1301 1302 dev->config[PCI_CACHE_LINE_SIZE] = 0x08; 1303 dev->config[PCI_LATENCY_TIMER] = 0x40; 1304 dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */ 1305 1306 memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, 1307 "vmsvga-io", 0x10); 1308 memory_region_set_flush_coalesced(&s->io_bar); 1309 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1310 1311 vmsvga_init(DEVICE(dev), &s->chip, 1312 pci_address_space(dev), pci_address_space_io(dev)); 1313 1314 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, 1315 &s->chip.vga.vram); 1316 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, 1317 &s->chip.fifo_ram); 1318 1319 if (!dev->rom_bar) { 1320 /* compatibility with pc-0.13 and older */ 1321 vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev)); 1322 } 1323 1324 return 0; 1325 } 1326 1327 static Property vga_vmware_properties[] = { 1328 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, 1329 chip.vga.vram_size_mb, 16), 1330 DEFINE_PROP_END_OF_LIST(), 1331 }; 1332 1333 static void vmsvga_class_init(ObjectClass *klass, void *data) 1334 { 1335 DeviceClass *dc = DEVICE_CLASS(klass); 1336 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1337 1338 k->init = pci_vmsvga_initfn; 1339 k->romfile = "vgabios-vmware.bin"; 1340 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1341 k->device_id = SVGA_PCI_DEVICE_ID; 1342 k->class_id = PCI_CLASS_DISPLAY_VGA; 1343 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 1344 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1345 dc->reset = vmsvga_reset; 1346 dc->vmsd = &vmstate_vmware_vga; 1347 dc->props = vga_vmware_properties; 1348 dc->hotpluggable = false; 1349 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1350 } 1351 1352 static const TypeInfo vmsvga_info = { 1353 .name = TYPE_VMWARE_SVGA, 1354 .parent = TYPE_PCI_DEVICE, 1355 .instance_size = sizeof(struct pci_vmsvga_state_s), 1356 .class_init = vmsvga_class_init, 1357 }; 1358 1359 static void vmsvga_register_types(void) 1360 { 1361 type_register_static(&vmsvga_info); 1362 } 1363 1364 type_init(vmsvga_register_types) 1365