1 /* 2 * QEMU VMware-SVGA "chipset". 3 * 4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/loader.h" 26 #include "ui/console.h" 27 #include "hw/pci/pci.h" 28 29 #undef VERBOSE 30 #define HW_RECT_ACCEL 31 #define HW_FILL_ACCEL 32 #define HW_MOUSE_ACCEL 33 34 #include "vga_int.h" 35 36 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ 37 38 struct vmsvga_state_s { 39 VGACommonState vga; 40 41 int invalidated; 42 int enable; 43 int config; 44 struct { 45 int id; 46 int x; 47 int y; 48 int on; 49 } cursor; 50 51 int index; 52 int scratch_size; 53 uint32_t *scratch; 54 int new_width; 55 int new_height; 56 int new_depth; 57 uint32_t guest; 58 uint32_t svgaid; 59 int syncing; 60 61 MemoryRegion fifo_ram; 62 uint8_t *fifo_ptr; 63 unsigned int fifo_size; 64 65 union { 66 uint32_t *fifo; 67 struct QEMU_PACKED { 68 uint32_t min; 69 uint32_t max; 70 uint32_t next_cmd; 71 uint32_t stop; 72 /* Add registers here when adding capabilities. */ 73 uint32_t fifo[0]; 74 } *cmd; 75 }; 76 77 #define REDRAW_FIFO_LEN 512 78 struct vmsvga_rect_s { 79 int x, y, w, h; 80 } redraw_fifo[REDRAW_FIFO_LEN]; 81 int redraw_fifo_first, redraw_fifo_last; 82 }; 83 84 #define TYPE_VMWARE_SVGA "vmware-svga" 85 86 #define VMWARE_SVGA(obj) \ 87 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA) 88 89 struct pci_vmsvga_state_s { 90 PCIDevice card; 91 struct vmsvga_state_s chip; 92 MemoryRegion io_bar; 93 }; 94 95 #define SVGA_MAGIC 0x900000UL 96 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 97 #define SVGA_ID_0 SVGA_MAKE_ID(0) 98 #define SVGA_ID_1 SVGA_MAKE_ID(1) 99 #define SVGA_ID_2 SVGA_MAKE_ID(2) 100 101 #define SVGA_LEGACY_BASE_PORT 0x4560 102 #define SVGA_INDEX_PORT 0x0 103 #define SVGA_VALUE_PORT 0x1 104 #define SVGA_BIOS_PORT 0x2 105 106 #define SVGA_VERSION_2 107 108 #ifdef SVGA_VERSION_2 109 # define SVGA_ID SVGA_ID_2 110 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 111 # define SVGA_IO_MUL 1 112 # define SVGA_FIFO_SIZE 0x10000 113 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 114 #else 115 # define SVGA_ID SVGA_ID_1 116 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 117 # define SVGA_IO_MUL 4 118 # define SVGA_FIFO_SIZE 0x10000 119 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA 120 #endif 121 122 enum { 123 /* ID 0, 1 and 2 registers */ 124 SVGA_REG_ID = 0, 125 SVGA_REG_ENABLE = 1, 126 SVGA_REG_WIDTH = 2, 127 SVGA_REG_HEIGHT = 3, 128 SVGA_REG_MAX_WIDTH = 4, 129 SVGA_REG_MAX_HEIGHT = 5, 130 SVGA_REG_DEPTH = 6, 131 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 132 SVGA_REG_PSEUDOCOLOR = 8, 133 SVGA_REG_RED_MASK = 9, 134 SVGA_REG_GREEN_MASK = 10, 135 SVGA_REG_BLUE_MASK = 11, 136 SVGA_REG_BYTES_PER_LINE = 12, 137 SVGA_REG_FB_START = 13, 138 SVGA_REG_FB_OFFSET = 14, 139 SVGA_REG_VRAM_SIZE = 15, 140 SVGA_REG_FB_SIZE = 16, 141 142 /* ID 1 and 2 registers */ 143 SVGA_REG_CAPABILITIES = 17, 144 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ 145 SVGA_REG_MEM_SIZE = 19, 146 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 147 SVGA_REG_SYNC = 21, /* Write to force synchronization */ 148 SVGA_REG_BUSY = 22, /* Read to check if sync is done */ 149 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 150 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ 151 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ 152 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ 153 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ 154 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ 155 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 156 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 157 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ 158 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 159 160 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 161 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, 162 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, 163 }; 164 165 #define SVGA_CAP_NONE 0 166 #define SVGA_CAP_RECT_FILL (1 << 0) 167 #define SVGA_CAP_RECT_COPY (1 << 1) 168 #define SVGA_CAP_RECT_PAT_FILL (1 << 2) 169 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) 170 #define SVGA_CAP_RASTER_OP (1 << 4) 171 #define SVGA_CAP_CURSOR (1 << 5) 172 #define SVGA_CAP_CURSOR_BYPASS (1 << 6) 173 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) 174 #define SVGA_CAP_8BIT_EMULATION (1 << 8) 175 #define SVGA_CAP_ALPHA_CURSOR (1 << 9) 176 #define SVGA_CAP_GLYPH (1 << 10) 177 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) 178 #define SVGA_CAP_OFFSCREEN_1 (1 << 12) 179 #define SVGA_CAP_ALPHA_BLEND (1 << 13) 180 #define SVGA_CAP_3D (1 << 14) 181 #define SVGA_CAP_EXTENDED_FIFO (1 << 15) 182 #define SVGA_CAP_MULTIMON (1 << 16) 183 #define SVGA_CAP_PITCHLOCK (1 << 17) 184 185 /* 186 * FIFO offsets (seen as an array of 32-bit words) 187 */ 188 enum { 189 /* 190 * The original defined FIFO offsets 191 */ 192 SVGA_FIFO_MIN = 0, 193 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 194 SVGA_FIFO_NEXT_CMD, 195 SVGA_FIFO_STOP, 196 197 /* 198 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO 199 */ 200 SVGA_FIFO_CAPABILITIES = 4, 201 SVGA_FIFO_FLAGS, 202 SVGA_FIFO_FENCE, 203 SVGA_FIFO_3D_HWVERSION, 204 SVGA_FIFO_PITCHLOCK, 205 }; 206 207 #define SVGA_FIFO_CAP_NONE 0 208 #define SVGA_FIFO_CAP_FENCE (1 << 0) 209 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 210 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 211 212 #define SVGA_FIFO_FLAG_NONE 0 213 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 214 215 /* These values can probably be changed arbitrarily. */ 216 #define SVGA_SCRATCH_SIZE 0x8000 217 #define SVGA_MAX_WIDTH 2360 218 #define SVGA_MAX_HEIGHT 1770 219 220 #ifdef VERBOSE 221 # define GUEST_OS_BASE 0x5001 222 static const char *vmsvga_guest_id[] = { 223 [0x00] = "Dos", 224 [0x01] = "Windows 3.1", 225 [0x02] = "Windows 95", 226 [0x03] = "Windows 98", 227 [0x04] = "Windows ME", 228 [0x05] = "Windows NT", 229 [0x06] = "Windows 2000", 230 [0x07] = "Linux", 231 [0x08] = "OS/2", 232 [0x09] = "an unknown OS", 233 [0x0a] = "BSD", 234 [0x0b] = "Whistler", 235 [0x0c] = "an unknown OS", 236 [0x0d] = "an unknown OS", 237 [0x0e] = "an unknown OS", 238 [0x0f] = "an unknown OS", 239 [0x10] = "an unknown OS", 240 [0x11] = "an unknown OS", 241 [0x12] = "an unknown OS", 242 [0x13] = "an unknown OS", 243 [0x14] = "an unknown OS", 244 [0x15] = "Windows 2003", 245 }; 246 #endif 247 248 enum { 249 SVGA_CMD_INVALID_CMD = 0, 250 SVGA_CMD_UPDATE = 1, 251 SVGA_CMD_RECT_FILL = 2, 252 SVGA_CMD_RECT_COPY = 3, 253 SVGA_CMD_DEFINE_BITMAP = 4, 254 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, 255 SVGA_CMD_DEFINE_PIXMAP = 6, 256 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, 257 SVGA_CMD_RECT_BITMAP_FILL = 8, 258 SVGA_CMD_RECT_PIXMAP_FILL = 9, 259 SVGA_CMD_RECT_BITMAP_COPY = 10, 260 SVGA_CMD_RECT_PIXMAP_COPY = 11, 261 SVGA_CMD_FREE_OBJECT = 12, 262 SVGA_CMD_RECT_ROP_FILL = 13, 263 SVGA_CMD_RECT_ROP_COPY = 14, 264 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, 265 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, 266 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, 267 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, 268 SVGA_CMD_DEFINE_CURSOR = 19, 269 SVGA_CMD_DISPLAY_CURSOR = 20, 270 SVGA_CMD_MOVE_CURSOR = 21, 271 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 272 SVGA_CMD_DRAW_GLYPH = 23, 273 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, 274 SVGA_CMD_UPDATE_VERBOSE = 25, 275 SVGA_CMD_SURFACE_FILL = 26, 276 SVGA_CMD_SURFACE_COPY = 27, 277 SVGA_CMD_SURFACE_ALPHA_BLEND = 28, 278 SVGA_CMD_FRONT_ROP_FILL = 29, 279 SVGA_CMD_FENCE = 30, 280 }; 281 282 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ 283 enum { 284 SVGA_CURSOR_ON_HIDE = 0, 285 SVGA_CURSOR_ON_SHOW = 1, 286 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, 287 SVGA_CURSOR_ON_RESTORE_TO_FB = 3, 288 }; 289 290 static inline void vmsvga_update_rect(struct vmsvga_state_s *s, 291 int x, int y, int w, int h) 292 { 293 DisplaySurface *surface = qemu_console_surface(s->vga.con); 294 int line; 295 int bypl; 296 int width; 297 int start; 298 uint8_t *src; 299 uint8_t *dst; 300 301 if (x < 0) { 302 fprintf(stderr, "%s: update x was < 0 (%d)\n", __func__, x); 303 w += x; 304 x = 0; 305 } 306 if (w < 0) { 307 fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w); 308 w = 0; 309 } 310 if (x + w > surface_width(surface)) { 311 fprintf(stderr, "%s: update width too large x: %d, w: %d\n", 312 __func__, x, w); 313 x = MIN(x, surface_width(surface)); 314 w = surface_width(surface) - x; 315 } 316 317 if (y < 0) { 318 fprintf(stderr, "%s: update y was < 0 (%d)\n", __func__, y); 319 h += y; 320 y = 0; 321 } 322 if (h < 0) { 323 fprintf(stderr, "%s: update h was < 0 (%d)\n", __func__, h); 324 h = 0; 325 } 326 if (y + h > surface_height(surface)) { 327 fprintf(stderr, "%s: update height too large y: %d, h: %d\n", 328 __func__, y, h); 329 y = MIN(y, surface_height(surface)); 330 h = surface_height(surface) - y; 331 } 332 333 bypl = surface_stride(surface); 334 width = surface_bytes_per_pixel(surface) * w; 335 start = surface_bytes_per_pixel(surface) * x + bypl * y; 336 src = s->vga.vram_ptr + start; 337 dst = surface_data(surface) + start; 338 339 for (line = h; line > 0; line--, src += bypl, dst += bypl) { 340 memcpy(dst, src, width); 341 } 342 dpy_gfx_update(s->vga.con, x, y, w, h); 343 } 344 345 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, 346 int x, int y, int w, int h) 347 { 348 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; 349 350 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; 351 rect->x = x; 352 rect->y = y; 353 rect->w = w; 354 rect->h = h; 355 } 356 357 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) 358 { 359 struct vmsvga_rect_s *rect; 360 361 if (s->invalidated) { 362 s->redraw_fifo_first = s->redraw_fifo_last; 363 return; 364 } 365 /* Overlapping region updates can be optimised out here - if someone 366 * knows a smart algorithm to do that, please share. */ 367 while (s->redraw_fifo_first != s->redraw_fifo_last) { 368 rect = &s->redraw_fifo[s->redraw_fifo_first++]; 369 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; 370 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); 371 } 372 } 373 374 #ifdef HW_RECT_ACCEL 375 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, 376 int x0, int y0, int x1, int y1, int w, int h) 377 { 378 DisplaySurface *surface = qemu_console_surface(s->vga.con); 379 uint8_t *vram = s->vga.vram_ptr; 380 int bypl = surface_stride(surface); 381 int bypp = surface_bytes_per_pixel(surface); 382 int width = bypp * w; 383 int line = h; 384 uint8_t *ptr[2]; 385 386 if (y1 > y0) { 387 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); 388 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); 389 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { 390 memmove(ptr[1], ptr[0], width); 391 } 392 } else { 393 ptr[0] = vram + bypp * x0 + bypl * y0; 394 ptr[1] = vram + bypp * x1 + bypl * y1; 395 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { 396 memmove(ptr[1], ptr[0], width); 397 } 398 } 399 400 vmsvga_update_rect_delayed(s, x1, y1, w, h); 401 } 402 #endif 403 404 #ifdef HW_FILL_ACCEL 405 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, 406 uint32_t c, int x, int y, int w, int h) 407 { 408 DisplaySurface *surface = qemu_console_surface(s->vga.con); 409 int bypl = surface_stride(surface); 410 int width = surface_bytes_per_pixel(surface) * w; 411 int line = h; 412 int column; 413 uint8_t *fst; 414 uint8_t *dst; 415 uint8_t *src; 416 uint8_t col[4]; 417 418 col[0] = c; 419 col[1] = c >> 8; 420 col[2] = c >> 16; 421 col[3] = c >> 24; 422 423 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; 424 425 if (line--) { 426 dst = fst; 427 src = col; 428 for (column = width; column > 0; column--) { 429 *(dst++) = *(src++); 430 if (src - col == surface_bytes_per_pixel(surface)) { 431 src = col; 432 } 433 } 434 dst = fst; 435 for (; line > 0; line--) { 436 dst += bypl; 437 memcpy(dst, fst, width); 438 } 439 } 440 441 vmsvga_update_rect_delayed(s, x, y, w, h); 442 } 443 #endif 444 445 struct vmsvga_cursor_definition_s { 446 int width; 447 int height; 448 int id; 449 int bpp; 450 int hot_x; 451 int hot_y; 452 uint32_t mask[1024]; 453 uint32_t image[4096]; 454 }; 455 456 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) 457 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) 458 459 #ifdef HW_MOUSE_ACCEL 460 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, 461 struct vmsvga_cursor_definition_s *c) 462 { 463 QEMUCursor *qc; 464 int i, pixels; 465 466 qc = cursor_alloc(c->width, c->height); 467 qc->hot_x = c->hot_x; 468 qc->hot_y = c->hot_y; 469 switch (c->bpp) { 470 case 1: 471 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, 472 1, (void *)c->mask); 473 #ifdef DEBUG 474 cursor_print_ascii_art(qc, "vmware/mono"); 475 #endif 476 break; 477 case 32: 478 /* fill alpha channel from mask, set color to zero */ 479 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, 480 1, (void *)c->mask); 481 /* add in rgb values */ 482 pixels = c->width * c->height; 483 for (i = 0; i < pixels; i++) { 484 qc->data[i] |= c->image[i] & 0xffffff; 485 } 486 #ifdef DEBUG 487 cursor_print_ascii_art(qc, "vmware/32bit"); 488 #endif 489 break; 490 default: 491 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", 492 __func__, c->bpp); 493 cursor_put(qc); 494 qc = cursor_builtin_left_ptr(); 495 } 496 497 dpy_cursor_define(s->vga.con, qc); 498 cursor_put(qc); 499 } 500 #endif 501 502 #define CMD(f) le32_to_cpu(s->cmd->f) 503 504 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) 505 { 506 int num; 507 508 if (!s->config || !s->enable) { 509 return 0; 510 } 511 num = CMD(next_cmd) - CMD(stop); 512 if (num < 0) { 513 num += CMD(max) - CMD(min); 514 } 515 return num >> 2; 516 } 517 518 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) 519 { 520 uint32_t cmd = s->fifo[CMD(stop) >> 2]; 521 522 s->cmd->stop = cpu_to_le32(CMD(stop) + 4); 523 if (CMD(stop) >= CMD(max)) { 524 s->cmd->stop = s->cmd->min; 525 } 526 return cmd; 527 } 528 529 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) 530 { 531 return le32_to_cpu(vmsvga_fifo_read_raw(s)); 532 } 533 534 static void vmsvga_fifo_run(struct vmsvga_state_s *s) 535 { 536 uint32_t cmd, colour; 537 int args, len; 538 int x, y, dx, dy, width, height; 539 struct vmsvga_cursor_definition_s cursor; 540 uint32_t cmd_start; 541 542 len = vmsvga_fifo_length(s); 543 while (len > 0) { 544 /* May need to go back to the start of the command if incomplete */ 545 cmd_start = s->cmd->stop; 546 547 switch (cmd = vmsvga_fifo_read(s)) { 548 case SVGA_CMD_UPDATE: 549 case SVGA_CMD_UPDATE_VERBOSE: 550 len -= 5; 551 if (len < 0) { 552 goto rewind; 553 } 554 555 x = vmsvga_fifo_read(s); 556 y = vmsvga_fifo_read(s); 557 width = vmsvga_fifo_read(s); 558 height = vmsvga_fifo_read(s); 559 vmsvga_update_rect_delayed(s, x, y, width, height); 560 break; 561 562 case SVGA_CMD_RECT_FILL: 563 len -= 6; 564 if (len < 0) { 565 goto rewind; 566 } 567 568 colour = vmsvga_fifo_read(s); 569 x = vmsvga_fifo_read(s); 570 y = vmsvga_fifo_read(s); 571 width = vmsvga_fifo_read(s); 572 height = vmsvga_fifo_read(s); 573 #ifdef HW_FILL_ACCEL 574 vmsvga_fill_rect(s, colour, x, y, width, height); 575 break; 576 #else 577 args = 0; 578 goto badcmd; 579 #endif 580 581 case SVGA_CMD_RECT_COPY: 582 len -= 7; 583 if (len < 0) { 584 goto rewind; 585 } 586 587 x = vmsvga_fifo_read(s); 588 y = vmsvga_fifo_read(s); 589 dx = vmsvga_fifo_read(s); 590 dy = vmsvga_fifo_read(s); 591 width = vmsvga_fifo_read(s); 592 height = vmsvga_fifo_read(s); 593 #ifdef HW_RECT_ACCEL 594 vmsvga_copy_rect(s, x, y, dx, dy, width, height); 595 break; 596 #else 597 args = 0; 598 goto badcmd; 599 #endif 600 601 case SVGA_CMD_DEFINE_CURSOR: 602 len -= 8; 603 if (len < 0) { 604 goto rewind; 605 } 606 607 cursor.id = vmsvga_fifo_read(s); 608 cursor.hot_x = vmsvga_fifo_read(s); 609 cursor.hot_y = vmsvga_fifo_read(s); 610 cursor.width = x = vmsvga_fifo_read(s); 611 cursor.height = y = vmsvga_fifo_read(s); 612 vmsvga_fifo_read(s); 613 cursor.bpp = vmsvga_fifo_read(s); 614 615 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); 616 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || 617 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { 618 goto badcmd; 619 } 620 621 len -= args; 622 if (len < 0) { 623 goto rewind; 624 } 625 626 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { 627 cursor.mask[args] = vmsvga_fifo_read_raw(s); 628 } 629 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { 630 cursor.image[args] = vmsvga_fifo_read_raw(s); 631 } 632 #ifdef HW_MOUSE_ACCEL 633 vmsvga_cursor_define(s, &cursor); 634 break; 635 #else 636 args = 0; 637 goto badcmd; 638 #endif 639 640 /* 641 * Other commands that we at least know the number of arguments 642 * for so we can avoid FIFO desync if driver uses them illegally. 643 */ 644 case SVGA_CMD_DEFINE_ALPHA_CURSOR: 645 len -= 6; 646 if (len < 0) { 647 goto rewind; 648 } 649 vmsvga_fifo_read(s); 650 vmsvga_fifo_read(s); 651 vmsvga_fifo_read(s); 652 x = vmsvga_fifo_read(s); 653 y = vmsvga_fifo_read(s); 654 args = x * y; 655 goto badcmd; 656 case SVGA_CMD_RECT_ROP_FILL: 657 args = 6; 658 goto badcmd; 659 case SVGA_CMD_RECT_ROP_COPY: 660 args = 7; 661 goto badcmd; 662 case SVGA_CMD_DRAW_GLYPH_CLIPPED: 663 len -= 4; 664 if (len < 0) { 665 goto rewind; 666 } 667 vmsvga_fifo_read(s); 668 vmsvga_fifo_read(s); 669 args = 7 + (vmsvga_fifo_read(s) >> 2); 670 goto badcmd; 671 case SVGA_CMD_SURFACE_ALPHA_BLEND: 672 args = 12; 673 goto badcmd; 674 675 /* 676 * Other commands that are not listed as depending on any 677 * CAPABILITIES bits, but are not described in the README either. 678 */ 679 case SVGA_CMD_SURFACE_FILL: 680 case SVGA_CMD_SURFACE_COPY: 681 case SVGA_CMD_FRONT_ROP_FILL: 682 case SVGA_CMD_FENCE: 683 case SVGA_CMD_INVALID_CMD: 684 break; /* Nop */ 685 686 default: 687 args = 0; 688 badcmd: 689 len -= args; 690 if (len < 0) { 691 goto rewind; 692 } 693 while (args--) { 694 vmsvga_fifo_read(s); 695 } 696 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", 697 __func__, cmd); 698 break; 699 700 rewind: 701 s->cmd->stop = cmd_start; 702 break; 703 } 704 } 705 706 s->syncing = 0; 707 } 708 709 static uint32_t vmsvga_index_read(void *opaque, uint32_t address) 710 { 711 struct vmsvga_state_s *s = opaque; 712 713 return s->index; 714 } 715 716 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) 717 { 718 struct vmsvga_state_s *s = opaque; 719 720 s->index = index; 721 } 722 723 static uint32_t vmsvga_value_read(void *opaque, uint32_t address) 724 { 725 uint32_t caps; 726 struct vmsvga_state_s *s = opaque; 727 DisplaySurface *surface = qemu_console_surface(s->vga.con); 728 PixelFormat pf; 729 uint32_t ret; 730 731 switch (s->index) { 732 case SVGA_REG_ID: 733 ret = s->svgaid; 734 break; 735 736 case SVGA_REG_ENABLE: 737 ret = s->enable; 738 break; 739 740 case SVGA_REG_WIDTH: 741 ret = s->new_width ? s->new_width : surface_width(surface); 742 break; 743 744 case SVGA_REG_HEIGHT: 745 ret = s->new_height ? s->new_height : surface_height(surface); 746 break; 747 748 case SVGA_REG_MAX_WIDTH: 749 ret = SVGA_MAX_WIDTH; 750 break; 751 752 case SVGA_REG_MAX_HEIGHT: 753 ret = SVGA_MAX_HEIGHT; 754 break; 755 756 case SVGA_REG_DEPTH: 757 ret = (s->new_depth == 32) ? 24 : s->new_depth; 758 break; 759 760 case SVGA_REG_BITS_PER_PIXEL: 761 case SVGA_REG_HOST_BITS_PER_PIXEL: 762 ret = s->new_depth; 763 break; 764 765 case SVGA_REG_PSEUDOCOLOR: 766 ret = 0x0; 767 break; 768 769 case SVGA_REG_RED_MASK: 770 pf = qemu_default_pixelformat(s->new_depth); 771 ret = pf.rmask; 772 break; 773 774 case SVGA_REG_GREEN_MASK: 775 pf = qemu_default_pixelformat(s->new_depth); 776 ret = pf.gmask; 777 break; 778 779 case SVGA_REG_BLUE_MASK: 780 pf = qemu_default_pixelformat(s->new_depth); 781 ret = pf.bmask; 782 break; 783 784 case SVGA_REG_BYTES_PER_LINE: 785 if (s->new_width) { 786 ret = (s->new_depth * s->new_width) / 8; 787 } else { 788 ret = surface_stride(surface); 789 } 790 break; 791 792 case SVGA_REG_FB_START: { 793 struct pci_vmsvga_state_s *pci_vmsvga 794 = container_of(s, struct pci_vmsvga_state_s, chip); 795 ret = pci_get_bar_addr(&pci_vmsvga->card, 1); 796 break; 797 } 798 799 case SVGA_REG_FB_OFFSET: 800 ret = 0x0; 801 break; 802 803 case SVGA_REG_VRAM_SIZE: 804 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ 805 break; 806 807 case SVGA_REG_FB_SIZE: 808 ret = s->vga.vram_size; 809 break; 810 811 case SVGA_REG_CAPABILITIES: 812 caps = SVGA_CAP_NONE; 813 #ifdef HW_RECT_ACCEL 814 caps |= SVGA_CAP_RECT_COPY; 815 #endif 816 #ifdef HW_FILL_ACCEL 817 caps |= SVGA_CAP_RECT_FILL; 818 #endif 819 #ifdef HW_MOUSE_ACCEL 820 if (dpy_cursor_define_supported(s->vga.con)) { 821 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 822 SVGA_CAP_CURSOR_BYPASS; 823 } 824 #endif 825 ret = caps; 826 break; 827 828 case SVGA_REG_MEM_START: { 829 struct pci_vmsvga_state_s *pci_vmsvga 830 = container_of(s, struct pci_vmsvga_state_s, chip); 831 ret = pci_get_bar_addr(&pci_vmsvga->card, 2); 832 break; 833 } 834 835 case SVGA_REG_MEM_SIZE: 836 ret = s->fifo_size; 837 break; 838 839 case SVGA_REG_CONFIG_DONE: 840 ret = s->config; 841 break; 842 843 case SVGA_REG_SYNC: 844 case SVGA_REG_BUSY: 845 ret = s->syncing; 846 break; 847 848 case SVGA_REG_GUEST_ID: 849 ret = s->guest; 850 break; 851 852 case SVGA_REG_CURSOR_ID: 853 ret = s->cursor.id; 854 break; 855 856 case SVGA_REG_CURSOR_X: 857 ret = s->cursor.x; 858 break; 859 860 case SVGA_REG_CURSOR_Y: 861 ret = s->cursor.x; 862 break; 863 864 case SVGA_REG_CURSOR_ON: 865 ret = s->cursor.on; 866 break; 867 868 case SVGA_REG_SCRATCH_SIZE: 869 ret = s->scratch_size; 870 break; 871 872 case SVGA_REG_MEM_REGS: 873 case SVGA_REG_NUM_DISPLAYS: 874 case SVGA_REG_PITCHLOCK: 875 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 876 ret = 0; 877 break; 878 879 default: 880 if (s->index >= SVGA_SCRATCH_BASE && 881 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 882 ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; 883 break; 884 } 885 printf("%s: Bad register %02x\n", __func__, s->index); 886 ret = 0; 887 break; 888 } 889 890 if (s->index >= SVGA_SCRATCH_BASE) { 891 trace_vmware_scratch_read(s->index, ret); 892 } else if (s->index >= SVGA_PALETTE_BASE) { 893 trace_vmware_palette_read(s->index, ret); 894 } else { 895 trace_vmware_value_read(s->index, ret); 896 } 897 return ret; 898 } 899 900 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) 901 { 902 struct vmsvga_state_s *s = opaque; 903 904 if (s->index >= SVGA_SCRATCH_BASE) { 905 trace_vmware_scratch_write(s->index, value); 906 } else if (s->index >= SVGA_PALETTE_BASE) { 907 trace_vmware_palette_write(s->index, value); 908 } else { 909 trace_vmware_value_write(s->index, value); 910 } 911 switch (s->index) { 912 case SVGA_REG_ID: 913 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { 914 s->svgaid = value; 915 } 916 break; 917 918 case SVGA_REG_ENABLE: 919 s->enable = !!value; 920 s->invalidated = 1; 921 s->vga.hw_ops->invalidate(&s->vga); 922 if (s->enable && s->config) { 923 vga_dirty_log_stop(&s->vga); 924 } else { 925 vga_dirty_log_start(&s->vga); 926 } 927 break; 928 929 case SVGA_REG_WIDTH: 930 if (value <= SVGA_MAX_WIDTH) { 931 s->new_width = value; 932 s->invalidated = 1; 933 } else { 934 printf("%s: Bad width: %i\n", __func__, value); 935 } 936 break; 937 938 case SVGA_REG_HEIGHT: 939 if (value <= SVGA_MAX_HEIGHT) { 940 s->new_height = value; 941 s->invalidated = 1; 942 } else { 943 printf("%s: Bad height: %i\n", __func__, value); 944 } 945 break; 946 947 case SVGA_REG_BITS_PER_PIXEL: 948 if (value != 32) { 949 printf("%s: Bad bits per pixel: %i bits\n", __func__, value); 950 s->config = 0; 951 s->invalidated = 1; 952 } 953 break; 954 955 case SVGA_REG_CONFIG_DONE: 956 if (value) { 957 s->fifo = (uint32_t *) s->fifo_ptr; 958 /* Check range and alignment. */ 959 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { 960 break; 961 } 962 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { 963 break; 964 } 965 if (CMD(max) > SVGA_FIFO_SIZE) { 966 break; 967 } 968 if (CMD(max) < CMD(min) + 10 * 1024) { 969 break; 970 } 971 vga_dirty_log_stop(&s->vga); 972 } 973 s->config = !!value; 974 break; 975 976 case SVGA_REG_SYNC: 977 s->syncing = 1; 978 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ 979 break; 980 981 case SVGA_REG_GUEST_ID: 982 s->guest = value; 983 #ifdef VERBOSE 984 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + 985 ARRAY_SIZE(vmsvga_guest_id)) { 986 printf("%s: guest runs %s.\n", __func__, 987 vmsvga_guest_id[value - GUEST_OS_BASE]); 988 } 989 #endif 990 break; 991 992 case SVGA_REG_CURSOR_ID: 993 s->cursor.id = value; 994 break; 995 996 case SVGA_REG_CURSOR_X: 997 s->cursor.x = value; 998 break; 999 1000 case SVGA_REG_CURSOR_Y: 1001 s->cursor.y = value; 1002 break; 1003 1004 case SVGA_REG_CURSOR_ON: 1005 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 1006 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 1007 #ifdef HW_MOUSE_ACCEL 1008 if (value <= SVGA_CURSOR_ON_SHOW) { 1009 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); 1010 } 1011 #endif 1012 break; 1013 1014 case SVGA_REG_DEPTH: 1015 case SVGA_REG_MEM_REGS: 1016 case SVGA_REG_NUM_DISPLAYS: 1017 case SVGA_REG_PITCHLOCK: 1018 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 1019 break; 1020 1021 default: 1022 if (s->index >= SVGA_SCRATCH_BASE && 1023 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 1024 s->scratch[s->index - SVGA_SCRATCH_BASE] = value; 1025 break; 1026 } 1027 printf("%s: Bad register %02x\n", __func__, s->index); 1028 } 1029 } 1030 1031 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) 1032 { 1033 printf("%s: what are we supposed to return?\n", __func__); 1034 return 0xcafe; 1035 } 1036 1037 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) 1038 { 1039 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); 1040 } 1041 1042 static inline void vmsvga_check_size(struct vmsvga_state_s *s) 1043 { 1044 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1045 1046 if (s->new_width != surface_width(surface) || 1047 s->new_height != surface_height(surface) || 1048 s->new_depth != surface_bits_per_pixel(surface)) { 1049 int stride = (s->new_depth * s->new_width) / 8; 1050 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); 1051 surface = qemu_create_displaysurface_from(s->new_width, s->new_height, 1052 s->new_depth, stride, 1053 s->vga.vram_ptr, false); 1054 dpy_gfx_replace_surface(s->vga.con, surface); 1055 s->invalidated = 1; 1056 } 1057 } 1058 1059 static void vmsvga_update_display(void *opaque) 1060 { 1061 struct vmsvga_state_s *s = opaque; 1062 DisplaySurface *surface; 1063 bool dirty = false; 1064 1065 if (!s->enable) { 1066 s->vga.hw_ops->gfx_update(&s->vga); 1067 return; 1068 } 1069 1070 vmsvga_check_size(s); 1071 surface = qemu_console_surface(s->vga.con); 1072 1073 vmsvga_fifo_run(s); 1074 vmsvga_update_rect_flush(s); 1075 1076 /* 1077 * Is it more efficient to look at vram VGA-dirty bits or wait 1078 * for the driver to issue SVGA_CMD_UPDATE? 1079 */ 1080 if (memory_region_is_logging(&s->vga.vram)) { 1081 vga_sync_dirty_bitmap(&s->vga); 1082 dirty = memory_region_get_dirty(&s->vga.vram, 0, 1083 surface_stride(surface) * surface_height(surface), 1084 DIRTY_MEMORY_VGA); 1085 } 1086 if (s->invalidated || dirty) { 1087 s->invalidated = 0; 1088 dpy_gfx_update(s->vga.con, 0, 0, 1089 surface_width(surface), surface_height(surface)); 1090 } 1091 if (dirty) { 1092 memory_region_reset_dirty(&s->vga.vram, 0, 1093 surface_stride(surface) * surface_height(surface), 1094 DIRTY_MEMORY_VGA); 1095 } 1096 } 1097 1098 static void vmsvga_reset(DeviceState *dev) 1099 { 1100 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev); 1101 struct vmsvga_state_s *s = &pci->chip; 1102 1103 s->index = 0; 1104 s->enable = 0; 1105 s->config = 0; 1106 s->svgaid = SVGA_ID; 1107 s->cursor.on = 0; 1108 s->redraw_fifo_first = 0; 1109 s->redraw_fifo_last = 0; 1110 s->syncing = 0; 1111 1112 vga_dirty_log_start(&s->vga); 1113 } 1114 1115 static void vmsvga_invalidate_display(void *opaque) 1116 { 1117 struct vmsvga_state_s *s = opaque; 1118 if (!s->enable) { 1119 s->vga.hw_ops->invalidate(&s->vga); 1120 return; 1121 } 1122 1123 s->invalidated = 1; 1124 } 1125 1126 static void vmsvga_text_update(void *opaque, console_ch_t *chardata) 1127 { 1128 struct vmsvga_state_s *s = opaque; 1129 1130 if (s->vga.hw_ops->text_update) { 1131 s->vga.hw_ops->text_update(&s->vga, chardata); 1132 } 1133 } 1134 1135 static int vmsvga_post_load(void *opaque, int version_id) 1136 { 1137 struct vmsvga_state_s *s = opaque; 1138 1139 s->invalidated = 1; 1140 if (s->config) { 1141 s->fifo = (uint32_t *) s->fifo_ptr; 1142 } 1143 return 0; 1144 } 1145 1146 static const VMStateDescription vmstate_vmware_vga_internal = { 1147 .name = "vmware_vga_internal", 1148 .version_id = 0, 1149 .minimum_version_id = 0, 1150 .minimum_version_id_old = 0, 1151 .post_load = vmsvga_post_load, 1152 .fields = (VMStateField[]) { 1153 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), 1154 VMSTATE_INT32(enable, struct vmsvga_state_s), 1155 VMSTATE_INT32(config, struct vmsvga_state_s), 1156 VMSTATE_INT32(cursor.id, struct vmsvga_state_s), 1157 VMSTATE_INT32(cursor.x, struct vmsvga_state_s), 1158 VMSTATE_INT32(cursor.y, struct vmsvga_state_s), 1159 VMSTATE_INT32(cursor.on, struct vmsvga_state_s), 1160 VMSTATE_INT32(index, struct vmsvga_state_s), 1161 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, 1162 scratch_size, 0, vmstate_info_uint32, uint32_t), 1163 VMSTATE_INT32(new_width, struct vmsvga_state_s), 1164 VMSTATE_INT32(new_height, struct vmsvga_state_s), 1165 VMSTATE_UINT32(guest, struct vmsvga_state_s), 1166 VMSTATE_UINT32(svgaid, struct vmsvga_state_s), 1167 VMSTATE_INT32(syncing, struct vmsvga_state_s), 1168 VMSTATE_UNUSED(4), /* was fb_size */ 1169 VMSTATE_END_OF_LIST() 1170 } 1171 }; 1172 1173 static const VMStateDescription vmstate_vmware_vga = { 1174 .name = "vmware_vga", 1175 .version_id = 0, 1176 .minimum_version_id = 0, 1177 .minimum_version_id_old = 0, 1178 .fields = (VMStateField[]) { 1179 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s), 1180 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, 1181 vmstate_vmware_vga_internal, struct vmsvga_state_s), 1182 VMSTATE_END_OF_LIST() 1183 } 1184 }; 1185 1186 static const GraphicHwOps vmsvga_ops = { 1187 .invalidate = vmsvga_invalidate_display, 1188 .gfx_update = vmsvga_update_display, 1189 .text_update = vmsvga_text_update, 1190 }; 1191 1192 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, 1193 MemoryRegion *address_space, MemoryRegion *io) 1194 { 1195 s->scratch_size = SVGA_SCRATCH_SIZE; 1196 s->scratch = g_malloc(s->scratch_size * 4); 1197 1198 s->vga.con = graphic_console_init(dev, &vmsvga_ops, s); 1199 1200 s->fifo_size = SVGA_FIFO_SIZE; 1201 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size); 1202 vmstate_register_ram_global(&s->fifo_ram); 1203 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); 1204 1205 vga_common_init(&s->vga, OBJECT(dev)); 1206 vga_init(&s->vga, OBJECT(dev), address_space, io, true); 1207 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); 1208 s->new_depth = 32; 1209 } 1210 1211 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) 1212 { 1213 struct vmsvga_state_s *s = opaque; 1214 1215 switch (addr) { 1216 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); 1217 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); 1218 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); 1219 default: return -1u; 1220 } 1221 } 1222 1223 static void vmsvga_io_write(void *opaque, hwaddr addr, 1224 uint64_t data, unsigned size) 1225 { 1226 struct vmsvga_state_s *s = opaque; 1227 1228 switch (addr) { 1229 case SVGA_IO_MUL * SVGA_INDEX_PORT: 1230 vmsvga_index_write(s, addr, data); 1231 break; 1232 case SVGA_IO_MUL * SVGA_VALUE_PORT: 1233 vmsvga_value_write(s, addr, data); 1234 break; 1235 case SVGA_IO_MUL * SVGA_BIOS_PORT: 1236 vmsvga_bios_write(s, addr, data); 1237 break; 1238 } 1239 } 1240 1241 static const MemoryRegionOps vmsvga_io_ops = { 1242 .read = vmsvga_io_read, 1243 .write = vmsvga_io_write, 1244 .endianness = DEVICE_LITTLE_ENDIAN, 1245 .valid = { 1246 .min_access_size = 4, 1247 .max_access_size = 4, 1248 .unaligned = true, 1249 }, 1250 .impl = { 1251 .unaligned = true, 1252 }, 1253 }; 1254 1255 static int pci_vmsvga_initfn(PCIDevice *dev) 1256 { 1257 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev); 1258 1259 s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ 1260 s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ 1261 s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ 1262 1263 memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, 1264 "vmsvga-io", 0x10); 1265 memory_region_set_flush_coalesced(&s->io_bar); 1266 pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1267 1268 vmsvga_init(DEVICE(dev), &s->chip, 1269 pci_address_space(dev), pci_address_space_io(dev)); 1270 1271 pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, 1272 &s->chip.vga.vram); 1273 pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, 1274 &s->chip.fifo_ram); 1275 1276 if (!dev->rom_bar) { 1277 /* compatibility with pc-0.13 and older */ 1278 vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev)); 1279 } 1280 1281 return 0; 1282 } 1283 1284 static Property vga_vmware_properties[] = { 1285 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, 1286 chip.vga.vram_size_mb, 16), 1287 DEFINE_PROP_END_OF_LIST(), 1288 }; 1289 1290 static void vmsvga_class_init(ObjectClass *klass, void *data) 1291 { 1292 DeviceClass *dc = DEVICE_CLASS(klass); 1293 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1294 1295 k->no_hotplug = 1; 1296 k->init = pci_vmsvga_initfn; 1297 k->romfile = "vgabios-vmware.bin"; 1298 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1299 k->device_id = SVGA_PCI_DEVICE_ID; 1300 k->class_id = PCI_CLASS_DISPLAY_VGA; 1301 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 1302 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1303 dc->reset = vmsvga_reset; 1304 dc->vmsd = &vmstate_vmware_vga; 1305 dc->props = vga_vmware_properties; 1306 } 1307 1308 static const TypeInfo vmsvga_info = { 1309 .name = TYPE_VMWARE_SVGA, 1310 .parent = TYPE_PCI_DEVICE, 1311 .instance_size = sizeof(struct pci_vmsvga_state_s), 1312 .class_init = vmsvga_class_init, 1313 }; 1314 1315 static void vmsvga_register_types(void) 1316 { 1317 type_register_static(&vmsvga_info); 1318 } 1319 1320 type_init(vmsvga_register_types) 1321