1 /* 2 * QEMU VMware-SVGA "chipset". 3 * 4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/loader.h" 26 #include "trace.h" 27 #include "ui/console.h" 28 #include "ui/vnc.h" 29 #include "hw/pci/pci.h" 30 31 #undef VERBOSE 32 #if 0 33 #define HW_RECT_ACCEL 34 #define HW_FILL_ACCEL 35 #endif 36 #define HW_MOUSE_ACCEL 37 38 #include "vga_int.h" 39 40 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ 41 42 struct vmsvga_state_s { 43 VGACommonState vga; 44 45 int invalidated; 46 int enable; 47 int config; 48 struct { 49 int id; 50 int x; 51 int y; 52 int on; 53 } cursor; 54 55 int index; 56 int scratch_size; 57 uint32_t *scratch; 58 int new_width; 59 int new_height; 60 int new_depth; 61 uint32_t guest; 62 uint32_t svgaid; 63 int syncing; 64 65 MemoryRegion fifo_ram; 66 uint8_t *fifo_ptr; 67 unsigned int fifo_size; 68 69 union { 70 uint32_t *fifo; 71 struct QEMU_PACKED { 72 uint32_t min; 73 uint32_t max; 74 uint32_t next_cmd; 75 uint32_t stop; 76 /* Add registers here when adding capabilities. */ 77 uint32_t fifo[0]; 78 } *cmd; 79 }; 80 81 #define REDRAW_FIFO_LEN 512 82 struct vmsvga_rect_s { 83 int x, y, w, h; 84 } redraw_fifo[REDRAW_FIFO_LEN]; 85 int redraw_fifo_first, redraw_fifo_last; 86 }; 87 88 #define TYPE_VMWARE_SVGA "vmware-svga" 89 90 #define VMWARE_SVGA(obj) \ 91 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA) 92 93 struct pci_vmsvga_state_s { 94 /*< private >*/ 95 PCIDevice parent_obj; 96 /*< public >*/ 97 98 struct vmsvga_state_s chip; 99 MemoryRegion io_bar; 100 }; 101 102 #define SVGA_MAGIC 0x900000UL 103 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 104 #define SVGA_ID_0 SVGA_MAKE_ID(0) 105 #define SVGA_ID_1 SVGA_MAKE_ID(1) 106 #define SVGA_ID_2 SVGA_MAKE_ID(2) 107 108 #define SVGA_LEGACY_BASE_PORT 0x4560 109 #define SVGA_INDEX_PORT 0x0 110 #define SVGA_VALUE_PORT 0x1 111 #define SVGA_BIOS_PORT 0x2 112 113 #define SVGA_VERSION_2 114 115 #ifdef SVGA_VERSION_2 116 # define SVGA_ID SVGA_ID_2 117 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 118 # define SVGA_IO_MUL 1 119 # define SVGA_FIFO_SIZE 0x10000 120 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 121 #else 122 # define SVGA_ID SVGA_ID_1 123 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 124 # define SVGA_IO_MUL 4 125 # define SVGA_FIFO_SIZE 0x10000 126 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA 127 #endif 128 129 enum { 130 /* ID 0, 1 and 2 registers */ 131 SVGA_REG_ID = 0, 132 SVGA_REG_ENABLE = 1, 133 SVGA_REG_WIDTH = 2, 134 SVGA_REG_HEIGHT = 3, 135 SVGA_REG_MAX_WIDTH = 4, 136 SVGA_REG_MAX_HEIGHT = 5, 137 SVGA_REG_DEPTH = 6, 138 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 139 SVGA_REG_PSEUDOCOLOR = 8, 140 SVGA_REG_RED_MASK = 9, 141 SVGA_REG_GREEN_MASK = 10, 142 SVGA_REG_BLUE_MASK = 11, 143 SVGA_REG_BYTES_PER_LINE = 12, 144 SVGA_REG_FB_START = 13, 145 SVGA_REG_FB_OFFSET = 14, 146 SVGA_REG_VRAM_SIZE = 15, 147 SVGA_REG_FB_SIZE = 16, 148 149 /* ID 1 and 2 registers */ 150 SVGA_REG_CAPABILITIES = 17, 151 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ 152 SVGA_REG_MEM_SIZE = 19, 153 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 154 SVGA_REG_SYNC = 21, /* Write to force synchronization */ 155 SVGA_REG_BUSY = 22, /* Read to check if sync is done */ 156 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 157 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ 158 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ 159 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ 160 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ 161 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ 162 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 163 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 164 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ 165 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 166 167 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 168 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, 169 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, 170 }; 171 172 #define SVGA_CAP_NONE 0 173 #define SVGA_CAP_RECT_FILL (1 << 0) 174 #define SVGA_CAP_RECT_COPY (1 << 1) 175 #define SVGA_CAP_RECT_PAT_FILL (1 << 2) 176 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) 177 #define SVGA_CAP_RASTER_OP (1 << 4) 178 #define SVGA_CAP_CURSOR (1 << 5) 179 #define SVGA_CAP_CURSOR_BYPASS (1 << 6) 180 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) 181 #define SVGA_CAP_8BIT_EMULATION (1 << 8) 182 #define SVGA_CAP_ALPHA_CURSOR (1 << 9) 183 #define SVGA_CAP_GLYPH (1 << 10) 184 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) 185 #define SVGA_CAP_OFFSCREEN_1 (1 << 12) 186 #define SVGA_CAP_ALPHA_BLEND (1 << 13) 187 #define SVGA_CAP_3D (1 << 14) 188 #define SVGA_CAP_EXTENDED_FIFO (1 << 15) 189 #define SVGA_CAP_MULTIMON (1 << 16) 190 #define SVGA_CAP_PITCHLOCK (1 << 17) 191 192 /* 193 * FIFO offsets (seen as an array of 32-bit words) 194 */ 195 enum { 196 /* 197 * The original defined FIFO offsets 198 */ 199 SVGA_FIFO_MIN = 0, 200 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 201 SVGA_FIFO_NEXT_CMD, 202 SVGA_FIFO_STOP, 203 204 /* 205 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO 206 */ 207 SVGA_FIFO_CAPABILITIES = 4, 208 SVGA_FIFO_FLAGS, 209 SVGA_FIFO_FENCE, 210 SVGA_FIFO_3D_HWVERSION, 211 SVGA_FIFO_PITCHLOCK, 212 }; 213 214 #define SVGA_FIFO_CAP_NONE 0 215 #define SVGA_FIFO_CAP_FENCE (1 << 0) 216 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 217 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 218 219 #define SVGA_FIFO_FLAG_NONE 0 220 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 221 222 /* These values can probably be changed arbitrarily. */ 223 #define SVGA_SCRATCH_SIZE 0x8000 224 #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT) 225 #define SVGA_MAX_HEIGHT 1770 226 227 #ifdef VERBOSE 228 # define GUEST_OS_BASE 0x5001 229 static const char *vmsvga_guest_id[] = { 230 [0x00] = "Dos", 231 [0x01] = "Windows 3.1", 232 [0x02] = "Windows 95", 233 [0x03] = "Windows 98", 234 [0x04] = "Windows ME", 235 [0x05] = "Windows NT", 236 [0x06] = "Windows 2000", 237 [0x07] = "Linux", 238 [0x08] = "OS/2", 239 [0x09] = "an unknown OS", 240 [0x0a] = "BSD", 241 [0x0b] = "Whistler", 242 [0x0c] = "an unknown OS", 243 [0x0d] = "an unknown OS", 244 [0x0e] = "an unknown OS", 245 [0x0f] = "an unknown OS", 246 [0x10] = "an unknown OS", 247 [0x11] = "an unknown OS", 248 [0x12] = "an unknown OS", 249 [0x13] = "an unknown OS", 250 [0x14] = "an unknown OS", 251 [0x15] = "Windows 2003", 252 }; 253 #endif 254 255 enum { 256 SVGA_CMD_INVALID_CMD = 0, 257 SVGA_CMD_UPDATE = 1, 258 SVGA_CMD_RECT_FILL = 2, 259 SVGA_CMD_RECT_COPY = 3, 260 SVGA_CMD_DEFINE_BITMAP = 4, 261 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, 262 SVGA_CMD_DEFINE_PIXMAP = 6, 263 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, 264 SVGA_CMD_RECT_BITMAP_FILL = 8, 265 SVGA_CMD_RECT_PIXMAP_FILL = 9, 266 SVGA_CMD_RECT_BITMAP_COPY = 10, 267 SVGA_CMD_RECT_PIXMAP_COPY = 11, 268 SVGA_CMD_FREE_OBJECT = 12, 269 SVGA_CMD_RECT_ROP_FILL = 13, 270 SVGA_CMD_RECT_ROP_COPY = 14, 271 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, 272 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, 273 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, 274 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, 275 SVGA_CMD_DEFINE_CURSOR = 19, 276 SVGA_CMD_DISPLAY_CURSOR = 20, 277 SVGA_CMD_MOVE_CURSOR = 21, 278 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 279 SVGA_CMD_DRAW_GLYPH = 23, 280 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, 281 SVGA_CMD_UPDATE_VERBOSE = 25, 282 SVGA_CMD_SURFACE_FILL = 26, 283 SVGA_CMD_SURFACE_COPY = 27, 284 SVGA_CMD_SURFACE_ALPHA_BLEND = 28, 285 SVGA_CMD_FRONT_ROP_FILL = 29, 286 SVGA_CMD_FENCE = 30, 287 }; 288 289 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ 290 enum { 291 SVGA_CURSOR_ON_HIDE = 0, 292 SVGA_CURSOR_ON_SHOW = 1, 293 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, 294 SVGA_CURSOR_ON_RESTORE_TO_FB = 3, 295 }; 296 297 static inline bool vmsvga_verify_rect(DisplaySurface *surface, 298 const char *name, 299 int x, int y, int w, int h) 300 { 301 if (x < 0) { 302 fprintf(stderr, "%s: x was < 0 (%d)\n", name, x); 303 return false; 304 } 305 if (x > SVGA_MAX_WIDTH) { 306 fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x); 307 return false; 308 } 309 if (w < 0) { 310 fprintf(stderr, "%s: w was < 0 (%d)\n", name, w); 311 return false; 312 } 313 if (w > SVGA_MAX_WIDTH) { 314 fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w); 315 return false; 316 } 317 if (x + w > surface_width(surface)) { 318 fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n", 319 name, surface_width(surface), x, w); 320 return false; 321 } 322 323 if (y < 0) { 324 fprintf(stderr, "%s: y was < 0 (%d)\n", name, y); 325 return false; 326 } 327 if (y > SVGA_MAX_HEIGHT) { 328 fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y); 329 return false; 330 } 331 if (h < 0) { 332 fprintf(stderr, "%s: h was < 0 (%d)\n", name, h); 333 return false; 334 } 335 if (h > SVGA_MAX_HEIGHT) { 336 fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h); 337 return false; 338 } 339 if (y + h > surface_height(surface)) { 340 fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n", 341 name, surface_height(surface), y, h); 342 return false; 343 } 344 345 return true; 346 } 347 348 static inline void vmsvga_update_rect(struct vmsvga_state_s *s, 349 int x, int y, int w, int h) 350 { 351 DisplaySurface *surface = qemu_console_surface(s->vga.con); 352 int line; 353 int bypl; 354 int width; 355 int start; 356 uint8_t *src; 357 uint8_t *dst; 358 359 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { 360 /* go for a fullscreen update as fallback */ 361 x = 0; 362 y = 0; 363 w = surface_width(surface); 364 h = surface_height(surface); 365 } 366 367 bypl = surface_stride(surface); 368 width = surface_bytes_per_pixel(surface) * w; 369 start = surface_bytes_per_pixel(surface) * x + bypl * y; 370 src = s->vga.vram_ptr + start; 371 dst = surface_data(surface) + start; 372 373 for (line = h; line > 0; line--, src += bypl, dst += bypl) { 374 memcpy(dst, src, width); 375 } 376 dpy_gfx_update(s->vga.con, x, y, w, h); 377 } 378 379 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, 380 int x, int y, int w, int h) 381 { 382 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; 383 384 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; 385 rect->x = x; 386 rect->y = y; 387 rect->w = w; 388 rect->h = h; 389 } 390 391 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) 392 { 393 struct vmsvga_rect_s *rect; 394 395 if (s->invalidated) { 396 s->redraw_fifo_first = s->redraw_fifo_last; 397 return; 398 } 399 /* Overlapping region updates can be optimised out here - if someone 400 * knows a smart algorithm to do that, please share. */ 401 while (s->redraw_fifo_first != s->redraw_fifo_last) { 402 rect = &s->redraw_fifo[s->redraw_fifo_first++]; 403 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; 404 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); 405 } 406 } 407 408 #ifdef HW_RECT_ACCEL 409 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, 410 int x0, int y0, int x1, int y1, int w, int h) 411 { 412 DisplaySurface *surface = qemu_console_surface(s->vga.con); 413 uint8_t *vram = s->vga.vram_ptr; 414 int bypl = surface_stride(surface); 415 int bypp = surface_bytes_per_pixel(surface); 416 int width = bypp * w; 417 int line = h; 418 uint8_t *ptr[2]; 419 420 if (y1 > y0) { 421 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); 422 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); 423 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { 424 memmove(ptr[1], ptr[0], width); 425 } 426 } else { 427 ptr[0] = vram + bypp * x0 + bypl * y0; 428 ptr[1] = vram + bypp * x1 + bypl * y1; 429 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { 430 memmove(ptr[1], ptr[0], width); 431 } 432 } 433 434 vmsvga_update_rect_delayed(s, x1, y1, w, h); 435 } 436 #endif 437 438 #ifdef HW_FILL_ACCEL 439 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, 440 uint32_t c, int x, int y, int w, int h) 441 { 442 DisplaySurface *surface = qemu_console_surface(s->vga.con); 443 int bypl = surface_stride(surface); 444 int width = surface_bytes_per_pixel(surface) * w; 445 int line = h; 446 int column; 447 uint8_t *fst; 448 uint8_t *dst; 449 uint8_t *src; 450 uint8_t col[4]; 451 452 col[0] = c; 453 col[1] = c >> 8; 454 col[2] = c >> 16; 455 col[3] = c >> 24; 456 457 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; 458 459 if (line--) { 460 dst = fst; 461 src = col; 462 for (column = width; column > 0; column--) { 463 *(dst++) = *(src++); 464 if (src - col == surface_bytes_per_pixel(surface)) { 465 src = col; 466 } 467 } 468 dst = fst; 469 for (; line > 0; line--) { 470 dst += bypl; 471 memcpy(dst, fst, width); 472 } 473 } 474 475 vmsvga_update_rect_delayed(s, x, y, w, h); 476 } 477 #endif 478 479 struct vmsvga_cursor_definition_s { 480 int width; 481 int height; 482 int id; 483 int bpp; 484 int hot_x; 485 int hot_y; 486 uint32_t mask[1024]; 487 uint32_t image[4096]; 488 }; 489 490 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) 491 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) 492 493 #ifdef HW_MOUSE_ACCEL 494 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, 495 struct vmsvga_cursor_definition_s *c) 496 { 497 QEMUCursor *qc; 498 int i, pixels; 499 500 qc = cursor_alloc(c->width, c->height); 501 qc->hot_x = c->hot_x; 502 qc->hot_y = c->hot_y; 503 switch (c->bpp) { 504 case 1: 505 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, 506 1, (void *)c->mask); 507 #ifdef DEBUG 508 cursor_print_ascii_art(qc, "vmware/mono"); 509 #endif 510 break; 511 case 32: 512 /* fill alpha channel from mask, set color to zero */ 513 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, 514 1, (void *)c->mask); 515 /* add in rgb values */ 516 pixels = c->width * c->height; 517 for (i = 0; i < pixels; i++) { 518 qc->data[i] |= c->image[i] & 0xffffff; 519 } 520 #ifdef DEBUG 521 cursor_print_ascii_art(qc, "vmware/32bit"); 522 #endif 523 break; 524 default: 525 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", 526 __func__, c->bpp); 527 cursor_put(qc); 528 qc = cursor_builtin_left_ptr(); 529 } 530 531 dpy_cursor_define(s->vga.con, qc); 532 cursor_put(qc); 533 } 534 #endif 535 536 #define CMD(f) le32_to_cpu(s->cmd->f) 537 538 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) 539 { 540 int num; 541 542 if (!s->config || !s->enable) { 543 return 0; 544 } 545 num = CMD(next_cmd) - CMD(stop); 546 if (num < 0) { 547 num += CMD(max) - CMD(min); 548 } 549 return num >> 2; 550 } 551 552 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) 553 { 554 uint32_t cmd = s->fifo[CMD(stop) >> 2]; 555 556 s->cmd->stop = cpu_to_le32(CMD(stop) + 4); 557 if (CMD(stop) >= CMD(max)) { 558 s->cmd->stop = s->cmd->min; 559 } 560 return cmd; 561 } 562 563 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) 564 { 565 return le32_to_cpu(vmsvga_fifo_read_raw(s)); 566 } 567 568 static void vmsvga_fifo_run(struct vmsvga_state_s *s) 569 { 570 uint32_t cmd, colour; 571 int args, len; 572 int x, y, dx, dy, width, height; 573 struct vmsvga_cursor_definition_s cursor; 574 uint32_t cmd_start; 575 576 len = vmsvga_fifo_length(s); 577 while (len > 0) { 578 /* May need to go back to the start of the command if incomplete */ 579 cmd_start = s->cmd->stop; 580 581 switch (cmd = vmsvga_fifo_read(s)) { 582 case SVGA_CMD_UPDATE: 583 case SVGA_CMD_UPDATE_VERBOSE: 584 len -= 5; 585 if (len < 0) { 586 goto rewind; 587 } 588 589 x = vmsvga_fifo_read(s); 590 y = vmsvga_fifo_read(s); 591 width = vmsvga_fifo_read(s); 592 height = vmsvga_fifo_read(s); 593 vmsvga_update_rect_delayed(s, x, y, width, height); 594 break; 595 596 case SVGA_CMD_RECT_FILL: 597 len -= 6; 598 if (len < 0) { 599 goto rewind; 600 } 601 602 colour = vmsvga_fifo_read(s); 603 x = vmsvga_fifo_read(s); 604 y = vmsvga_fifo_read(s); 605 width = vmsvga_fifo_read(s); 606 height = vmsvga_fifo_read(s); 607 #ifdef HW_FILL_ACCEL 608 vmsvga_fill_rect(s, colour, x, y, width, height); 609 break; 610 #else 611 args = 0; 612 goto badcmd; 613 #endif 614 615 case SVGA_CMD_RECT_COPY: 616 len -= 7; 617 if (len < 0) { 618 goto rewind; 619 } 620 621 x = vmsvga_fifo_read(s); 622 y = vmsvga_fifo_read(s); 623 dx = vmsvga_fifo_read(s); 624 dy = vmsvga_fifo_read(s); 625 width = vmsvga_fifo_read(s); 626 height = vmsvga_fifo_read(s); 627 #ifdef HW_RECT_ACCEL 628 vmsvga_copy_rect(s, x, y, dx, dy, width, height); 629 break; 630 #else 631 args = 0; 632 goto badcmd; 633 #endif 634 635 case SVGA_CMD_DEFINE_CURSOR: 636 len -= 8; 637 if (len < 0) { 638 goto rewind; 639 } 640 641 cursor.id = vmsvga_fifo_read(s); 642 cursor.hot_x = vmsvga_fifo_read(s); 643 cursor.hot_y = vmsvga_fifo_read(s); 644 cursor.width = x = vmsvga_fifo_read(s); 645 cursor.height = y = vmsvga_fifo_read(s); 646 vmsvga_fifo_read(s); 647 cursor.bpp = vmsvga_fifo_read(s); 648 649 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); 650 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || 651 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { 652 goto badcmd; 653 } 654 655 len -= args; 656 if (len < 0) { 657 goto rewind; 658 } 659 660 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { 661 cursor.mask[args] = vmsvga_fifo_read_raw(s); 662 } 663 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { 664 cursor.image[args] = vmsvga_fifo_read_raw(s); 665 } 666 #ifdef HW_MOUSE_ACCEL 667 vmsvga_cursor_define(s, &cursor); 668 break; 669 #else 670 args = 0; 671 goto badcmd; 672 #endif 673 674 /* 675 * Other commands that we at least know the number of arguments 676 * for so we can avoid FIFO desync if driver uses them illegally. 677 */ 678 case SVGA_CMD_DEFINE_ALPHA_CURSOR: 679 len -= 6; 680 if (len < 0) { 681 goto rewind; 682 } 683 vmsvga_fifo_read(s); 684 vmsvga_fifo_read(s); 685 vmsvga_fifo_read(s); 686 x = vmsvga_fifo_read(s); 687 y = vmsvga_fifo_read(s); 688 args = x * y; 689 goto badcmd; 690 case SVGA_CMD_RECT_ROP_FILL: 691 args = 6; 692 goto badcmd; 693 case SVGA_CMD_RECT_ROP_COPY: 694 args = 7; 695 goto badcmd; 696 case SVGA_CMD_DRAW_GLYPH_CLIPPED: 697 len -= 4; 698 if (len < 0) { 699 goto rewind; 700 } 701 vmsvga_fifo_read(s); 702 vmsvga_fifo_read(s); 703 args = 7 + (vmsvga_fifo_read(s) >> 2); 704 goto badcmd; 705 case SVGA_CMD_SURFACE_ALPHA_BLEND: 706 args = 12; 707 goto badcmd; 708 709 /* 710 * Other commands that are not listed as depending on any 711 * CAPABILITIES bits, but are not described in the README either. 712 */ 713 case SVGA_CMD_SURFACE_FILL: 714 case SVGA_CMD_SURFACE_COPY: 715 case SVGA_CMD_FRONT_ROP_FILL: 716 case SVGA_CMD_FENCE: 717 case SVGA_CMD_INVALID_CMD: 718 break; /* Nop */ 719 720 default: 721 args = 0; 722 badcmd: 723 len -= args; 724 if (len < 0) { 725 goto rewind; 726 } 727 while (args--) { 728 vmsvga_fifo_read(s); 729 } 730 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", 731 __func__, cmd); 732 break; 733 734 rewind: 735 s->cmd->stop = cmd_start; 736 break; 737 } 738 } 739 740 s->syncing = 0; 741 } 742 743 static uint32_t vmsvga_index_read(void *opaque, uint32_t address) 744 { 745 struct vmsvga_state_s *s = opaque; 746 747 return s->index; 748 } 749 750 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) 751 { 752 struct vmsvga_state_s *s = opaque; 753 754 s->index = index; 755 } 756 757 static uint32_t vmsvga_value_read(void *opaque, uint32_t address) 758 { 759 uint32_t caps; 760 struct vmsvga_state_s *s = opaque; 761 DisplaySurface *surface = qemu_console_surface(s->vga.con); 762 PixelFormat pf; 763 uint32_t ret; 764 765 switch (s->index) { 766 case SVGA_REG_ID: 767 ret = s->svgaid; 768 break; 769 770 case SVGA_REG_ENABLE: 771 ret = s->enable; 772 break; 773 774 case SVGA_REG_WIDTH: 775 ret = s->new_width ? s->new_width : surface_width(surface); 776 break; 777 778 case SVGA_REG_HEIGHT: 779 ret = s->new_height ? s->new_height : surface_height(surface); 780 break; 781 782 case SVGA_REG_MAX_WIDTH: 783 ret = SVGA_MAX_WIDTH; 784 break; 785 786 case SVGA_REG_MAX_HEIGHT: 787 ret = SVGA_MAX_HEIGHT; 788 break; 789 790 case SVGA_REG_DEPTH: 791 ret = (s->new_depth == 32) ? 24 : s->new_depth; 792 break; 793 794 case SVGA_REG_BITS_PER_PIXEL: 795 case SVGA_REG_HOST_BITS_PER_PIXEL: 796 ret = s->new_depth; 797 break; 798 799 case SVGA_REG_PSEUDOCOLOR: 800 ret = 0x0; 801 break; 802 803 case SVGA_REG_RED_MASK: 804 pf = qemu_default_pixelformat(s->new_depth); 805 ret = pf.rmask; 806 break; 807 808 case SVGA_REG_GREEN_MASK: 809 pf = qemu_default_pixelformat(s->new_depth); 810 ret = pf.gmask; 811 break; 812 813 case SVGA_REG_BLUE_MASK: 814 pf = qemu_default_pixelformat(s->new_depth); 815 ret = pf.bmask; 816 break; 817 818 case SVGA_REG_BYTES_PER_LINE: 819 if (s->new_width) { 820 ret = (s->new_depth * s->new_width) / 8; 821 } else { 822 ret = surface_stride(surface); 823 } 824 break; 825 826 case SVGA_REG_FB_START: { 827 struct pci_vmsvga_state_s *pci_vmsvga 828 = container_of(s, struct pci_vmsvga_state_s, chip); 829 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1); 830 break; 831 } 832 833 case SVGA_REG_FB_OFFSET: 834 ret = 0x0; 835 break; 836 837 case SVGA_REG_VRAM_SIZE: 838 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ 839 break; 840 841 case SVGA_REG_FB_SIZE: 842 ret = s->vga.vram_size; 843 break; 844 845 case SVGA_REG_CAPABILITIES: 846 caps = SVGA_CAP_NONE; 847 #ifdef HW_RECT_ACCEL 848 caps |= SVGA_CAP_RECT_COPY; 849 #endif 850 #ifdef HW_FILL_ACCEL 851 caps |= SVGA_CAP_RECT_FILL; 852 #endif 853 #ifdef HW_MOUSE_ACCEL 854 if (dpy_cursor_define_supported(s->vga.con)) { 855 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 856 SVGA_CAP_CURSOR_BYPASS; 857 } 858 #endif 859 ret = caps; 860 break; 861 862 case SVGA_REG_MEM_START: { 863 struct pci_vmsvga_state_s *pci_vmsvga 864 = container_of(s, struct pci_vmsvga_state_s, chip); 865 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2); 866 break; 867 } 868 869 case SVGA_REG_MEM_SIZE: 870 ret = s->fifo_size; 871 break; 872 873 case SVGA_REG_CONFIG_DONE: 874 ret = s->config; 875 break; 876 877 case SVGA_REG_SYNC: 878 case SVGA_REG_BUSY: 879 ret = s->syncing; 880 break; 881 882 case SVGA_REG_GUEST_ID: 883 ret = s->guest; 884 break; 885 886 case SVGA_REG_CURSOR_ID: 887 ret = s->cursor.id; 888 break; 889 890 case SVGA_REG_CURSOR_X: 891 ret = s->cursor.x; 892 break; 893 894 case SVGA_REG_CURSOR_Y: 895 ret = s->cursor.y; 896 break; 897 898 case SVGA_REG_CURSOR_ON: 899 ret = s->cursor.on; 900 break; 901 902 case SVGA_REG_SCRATCH_SIZE: 903 ret = s->scratch_size; 904 break; 905 906 case SVGA_REG_MEM_REGS: 907 case SVGA_REG_NUM_DISPLAYS: 908 case SVGA_REG_PITCHLOCK: 909 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 910 ret = 0; 911 break; 912 913 default: 914 if (s->index >= SVGA_SCRATCH_BASE && 915 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 916 ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; 917 break; 918 } 919 printf("%s: Bad register %02x\n", __func__, s->index); 920 ret = 0; 921 break; 922 } 923 924 if (s->index >= SVGA_SCRATCH_BASE) { 925 trace_vmware_scratch_read(s->index, ret); 926 } else if (s->index >= SVGA_PALETTE_BASE) { 927 trace_vmware_palette_read(s->index, ret); 928 } else { 929 trace_vmware_value_read(s->index, ret); 930 } 931 return ret; 932 } 933 934 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) 935 { 936 struct vmsvga_state_s *s = opaque; 937 938 if (s->index >= SVGA_SCRATCH_BASE) { 939 trace_vmware_scratch_write(s->index, value); 940 } else if (s->index >= SVGA_PALETTE_BASE) { 941 trace_vmware_palette_write(s->index, value); 942 } else { 943 trace_vmware_value_write(s->index, value); 944 } 945 switch (s->index) { 946 case SVGA_REG_ID: 947 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { 948 s->svgaid = value; 949 } 950 break; 951 952 case SVGA_REG_ENABLE: 953 s->enable = !!value; 954 s->invalidated = 1; 955 s->vga.hw_ops->invalidate(&s->vga); 956 if (s->enable && s->config) { 957 vga_dirty_log_stop(&s->vga); 958 } else { 959 vga_dirty_log_start(&s->vga); 960 } 961 break; 962 963 case SVGA_REG_WIDTH: 964 if (value <= SVGA_MAX_WIDTH) { 965 s->new_width = value; 966 s->invalidated = 1; 967 } else { 968 printf("%s: Bad width: %i\n", __func__, value); 969 } 970 break; 971 972 case SVGA_REG_HEIGHT: 973 if (value <= SVGA_MAX_HEIGHT) { 974 s->new_height = value; 975 s->invalidated = 1; 976 } else { 977 printf("%s: Bad height: %i\n", __func__, value); 978 } 979 break; 980 981 case SVGA_REG_BITS_PER_PIXEL: 982 if (value != 32) { 983 printf("%s: Bad bits per pixel: %i bits\n", __func__, value); 984 s->config = 0; 985 s->invalidated = 1; 986 } 987 break; 988 989 case SVGA_REG_CONFIG_DONE: 990 if (value) { 991 s->fifo = (uint32_t *) s->fifo_ptr; 992 /* Check range and alignment. */ 993 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { 994 break; 995 } 996 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { 997 break; 998 } 999 if (CMD(max) > SVGA_FIFO_SIZE) { 1000 break; 1001 } 1002 if (CMD(max) < CMD(min) + 10 * 1024) { 1003 break; 1004 } 1005 vga_dirty_log_stop(&s->vga); 1006 } 1007 s->config = !!value; 1008 break; 1009 1010 case SVGA_REG_SYNC: 1011 s->syncing = 1; 1012 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ 1013 break; 1014 1015 case SVGA_REG_GUEST_ID: 1016 s->guest = value; 1017 #ifdef VERBOSE 1018 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + 1019 ARRAY_SIZE(vmsvga_guest_id)) { 1020 printf("%s: guest runs %s.\n", __func__, 1021 vmsvga_guest_id[value - GUEST_OS_BASE]); 1022 } 1023 #endif 1024 break; 1025 1026 case SVGA_REG_CURSOR_ID: 1027 s->cursor.id = value; 1028 break; 1029 1030 case SVGA_REG_CURSOR_X: 1031 s->cursor.x = value; 1032 break; 1033 1034 case SVGA_REG_CURSOR_Y: 1035 s->cursor.y = value; 1036 break; 1037 1038 case SVGA_REG_CURSOR_ON: 1039 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 1040 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 1041 #ifdef HW_MOUSE_ACCEL 1042 if (value <= SVGA_CURSOR_ON_SHOW) { 1043 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); 1044 } 1045 #endif 1046 break; 1047 1048 case SVGA_REG_DEPTH: 1049 case SVGA_REG_MEM_REGS: 1050 case SVGA_REG_NUM_DISPLAYS: 1051 case SVGA_REG_PITCHLOCK: 1052 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 1053 break; 1054 1055 default: 1056 if (s->index >= SVGA_SCRATCH_BASE && 1057 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 1058 s->scratch[s->index - SVGA_SCRATCH_BASE] = value; 1059 break; 1060 } 1061 printf("%s: Bad register %02x\n", __func__, s->index); 1062 } 1063 } 1064 1065 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) 1066 { 1067 printf("%s: what are we supposed to return?\n", __func__); 1068 return 0xcafe; 1069 } 1070 1071 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) 1072 { 1073 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); 1074 } 1075 1076 static inline void vmsvga_check_size(struct vmsvga_state_s *s) 1077 { 1078 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1079 1080 if (s->new_width != surface_width(surface) || 1081 s->new_height != surface_height(surface) || 1082 s->new_depth != surface_bits_per_pixel(surface)) { 1083 int stride = (s->new_depth * s->new_width) / 8; 1084 pixman_format_code_t format = 1085 qemu_default_pixman_format(s->new_depth, true); 1086 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); 1087 surface = qemu_create_displaysurface_from(s->new_width, s->new_height, 1088 format, stride, 1089 s->vga.vram_ptr); 1090 dpy_gfx_replace_surface(s->vga.con, surface); 1091 s->invalidated = 1; 1092 } 1093 } 1094 1095 static void vmsvga_update_display(void *opaque) 1096 { 1097 struct vmsvga_state_s *s = opaque; 1098 DisplaySurface *surface; 1099 bool dirty = false; 1100 1101 if (!s->enable) { 1102 s->vga.hw_ops->gfx_update(&s->vga); 1103 return; 1104 } 1105 1106 vmsvga_check_size(s); 1107 surface = qemu_console_surface(s->vga.con); 1108 1109 vmsvga_fifo_run(s); 1110 vmsvga_update_rect_flush(s); 1111 1112 /* 1113 * Is it more efficient to look at vram VGA-dirty bits or wait 1114 * for the driver to issue SVGA_CMD_UPDATE? 1115 */ 1116 if (memory_region_is_logging(&s->vga.vram)) { 1117 vga_sync_dirty_bitmap(&s->vga); 1118 dirty = memory_region_get_dirty(&s->vga.vram, 0, 1119 surface_stride(surface) * surface_height(surface), 1120 DIRTY_MEMORY_VGA); 1121 } 1122 if (s->invalidated || dirty) { 1123 s->invalidated = 0; 1124 dpy_gfx_update(s->vga.con, 0, 0, 1125 surface_width(surface), surface_height(surface)); 1126 } 1127 if (dirty) { 1128 memory_region_reset_dirty(&s->vga.vram, 0, 1129 surface_stride(surface) * surface_height(surface), 1130 DIRTY_MEMORY_VGA); 1131 } 1132 } 1133 1134 static void vmsvga_reset(DeviceState *dev) 1135 { 1136 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev); 1137 struct vmsvga_state_s *s = &pci->chip; 1138 1139 s->index = 0; 1140 s->enable = 0; 1141 s->config = 0; 1142 s->svgaid = SVGA_ID; 1143 s->cursor.on = 0; 1144 s->redraw_fifo_first = 0; 1145 s->redraw_fifo_last = 0; 1146 s->syncing = 0; 1147 1148 vga_dirty_log_start(&s->vga); 1149 } 1150 1151 static void vmsvga_invalidate_display(void *opaque) 1152 { 1153 struct vmsvga_state_s *s = opaque; 1154 if (!s->enable) { 1155 s->vga.hw_ops->invalidate(&s->vga); 1156 return; 1157 } 1158 1159 s->invalidated = 1; 1160 } 1161 1162 static void vmsvga_text_update(void *opaque, console_ch_t *chardata) 1163 { 1164 struct vmsvga_state_s *s = opaque; 1165 1166 if (s->vga.hw_ops->text_update) { 1167 s->vga.hw_ops->text_update(&s->vga, chardata); 1168 } 1169 } 1170 1171 static int vmsvga_post_load(void *opaque, int version_id) 1172 { 1173 struct vmsvga_state_s *s = opaque; 1174 1175 s->invalidated = 1; 1176 if (s->config) { 1177 s->fifo = (uint32_t *) s->fifo_ptr; 1178 } 1179 return 0; 1180 } 1181 1182 static const VMStateDescription vmstate_vmware_vga_internal = { 1183 .name = "vmware_vga_internal", 1184 .version_id = 0, 1185 .minimum_version_id = 0, 1186 .post_load = vmsvga_post_load, 1187 .fields = (VMStateField[]) { 1188 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), 1189 VMSTATE_INT32(enable, struct vmsvga_state_s), 1190 VMSTATE_INT32(config, struct vmsvga_state_s), 1191 VMSTATE_INT32(cursor.id, struct vmsvga_state_s), 1192 VMSTATE_INT32(cursor.x, struct vmsvga_state_s), 1193 VMSTATE_INT32(cursor.y, struct vmsvga_state_s), 1194 VMSTATE_INT32(cursor.on, struct vmsvga_state_s), 1195 VMSTATE_INT32(index, struct vmsvga_state_s), 1196 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, 1197 scratch_size, 0, vmstate_info_uint32, uint32_t), 1198 VMSTATE_INT32(new_width, struct vmsvga_state_s), 1199 VMSTATE_INT32(new_height, struct vmsvga_state_s), 1200 VMSTATE_UINT32(guest, struct vmsvga_state_s), 1201 VMSTATE_UINT32(svgaid, struct vmsvga_state_s), 1202 VMSTATE_INT32(syncing, struct vmsvga_state_s), 1203 VMSTATE_UNUSED(4), /* was fb_size */ 1204 VMSTATE_END_OF_LIST() 1205 } 1206 }; 1207 1208 static const VMStateDescription vmstate_vmware_vga = { 1209 .name = "vmware_vga", 1210 .version_id = 0, 1211 .minimum_version_id = 0, 1212 .fields = (VMStateField[]) { 1213 VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s), 1214 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, 1215 vmstate_vmware_vga_internal, struct vmsvga_state_s), 1216 VMSTATE_END_OF_LIST() 1217 } 1218 }; 1219 1220 static const GraphicHwOps vmsvga_ops = { 1221 .invalidate = vmsvga_invalidate_display, 1222 .gfx_update = vmsvga_update_display, 1223 .text_update = vmsvga_text_update, 1224 }; 1225 1226 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, 1227 MemoryRegion *address_space, MemoryRegion *io) 1228 { 1229 s->scratch_size = SVGA_SCRATCH_SIZE; 1230 s->scratch = g_malloc(s->scratch_size * 4); 1231 1232 s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s); 1233 1234 s->fifo_size = SVGA_FIFO_SIZE; 1235 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, 1236 &error_abort); 1237 vmstate_register_ram_global(&s->fifo_ram); 1238 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); 1239 1240 vga_common_init(&s->vga, OBJECT(dev), true); 1241 vga_init(&s->vga, OBJECT(dev), address_space, io, true); 1242 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); 1243 s->new_depth = 32; 1244 } 1245 1246 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) 1247 { 1248 struct vmsvga_state_s *s = opaque; 1249 1250 switch (addr) { 1251 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); 1252 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); 1253 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); 1254 default: return -1u; 1255 } 1256 } 1257 1258 static void vmsvga_io_write(void *opaque, hwaddr addr, 1259 uint64_t data, unsigned size) 1260 { 1261 struct vmsvga_state_s *s = opaque; 1262 1263 switch (addr) { 1264 case SVGA_IO_MUL * SVGA_INDEX_PORT: 1265 vmsvga_index_write(s, addr, data); 1266 break; 1267 case SVGA_IO_MUL * SVGA_VALUE_PORT: 1268 vmsvga_value_write(s, addr, data); 1269 break; 1270 case SVGA_IO_MUL * SVGA_BIOS_PORT: 1271 vmsvga_bios_write(s, addr, data); 1272 break; 1273 } 1274 } 1275 1276 static const MemoryRegionOps vmsvga_io_ops = { 1277 .read = vmsvga_io_read, 1278 .write = vmsvga_io_write, 1279 .endianness = DEVICE_LITTLE_ENDIAN, 1280 .valid = { 1281 .min_access_size = 4, 1282 .max_access_size = 4, 1283 .unaligned = true, 1284 }, 1285 .impl = { 1286 .unaligned = true, 1287 }, 1288 }; 1289 1290 static int pci_vmsvga_initfn(PCIDevice *dev) 1291 { 1292 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev); 1293 1294 dev->config[PCI_CACHE_LINE_SIZE] = 0x08; 1295 dev->config[PCI_LATENCY_TIMER] = 0x40; 1296 dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */ 1297 1298 memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, 1299 "vmsvga-io", 0x10); 1300 memory_region_set_flush_coalesced(&s->io_bar); 1301 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1302 1303 vmsvga_init(DEVICE(dev), &s->chip, 1304 pci_address_space(dev), pci_address_space_io(dev)); 1305 1306 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, 1307 &s->chip.vga.vram); 1308 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, 1309 &s->chip.fifo_ram); 1310 1311 if (!dev->rom_bar) { 1312 /* compatibility with pc-0.13 and older */ 1313 vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev)); 1314 } 1315 1316 return 0; 1317 } 1318 1319 static Property vga_vmware_properties[] = { 1320 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, 1321 chip.vga.vram_size_mb, 16), 1322 DEFINE_PROP_END_OF_LIST(), 1323 }; 1324 1325 static void vmsvga_class_init(ObjectClass *klass, void *data) 1326 { 1327 DeviceClass *dc = DEVICE_CLASS(klass); 1328 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1329 1330 k->init = pci_vmsvga_initfn; 1331 k->romfile = "vgabios-vmware.bin"; 1332 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1333 k->device_id = SVGA_PCI_DEVICE_ID; 1334 k->class_id = PCI_CLASS_DISPLAY_VGA; 1335 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 1336 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1337 dc->reset = vmsvga_reset; 1338 dc->vmsd = &vmstate_vmware_vga; 1339 dc->props = vga_vmware_properties; 1340 dc->hotpluggable = false; 1341 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1342 } 1343 1344 static const TypeInfo vmsvga_info = { 1345 .name = TYPE_VMWARE_SVGA, 1346 .parent = TYPE_PCI_DEVICE, 1347 .instance_size = sizeof(struct pci_vmsvga_state_s), 1348 .class_init = vmsvga_class_init, 1349 }; 1350 1351 static void vmsvga_register_types(void) 1352 { 1353 type_register_static(&vmsvga_info); 1354 } 1355 1356 type_init(vmsvga_register_types) 1357