1 /* 2 * QEMU VMware-SVGA "chipset". 3 * 4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/loader.h" 26 #include "trace.h" 27 #include "ui/console.h" 28 #include "ui/vnc.h" 29 #include "hw/pci/pci.h" 30 31 #undef VERBOSE 32 #if 0 33 #define HW_RECT_ACCEL 34 #define HW_FILL_ACCEL 35 #endif 36 #define HW_MOUSE_ACCEL 37 38 #include "vga_int.h" 39 40 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ 41 42 struct vmsvga_state_s { 43 VGACommonState vga; 44 45 int invalidated; 46 int enable; 47 int config; 48 struct { 49 int id; 50 int x; 51 int y; 52 int on; 53 } cursor; 54 55 int index; 56 int scratch_size; 57 uint32_t *scratch; 58 int new_width; 59 int new_height; 60 int new_depth; 61 uint32_t guest; 62 uint32_t svgaid; 63 int syncing; 64 65 MemoryRegion fifo_ram; 66 uint8_t *fifo_ptr; 67 unsigned int fifo_size; 68 69 union { 70 uint32_t *fifo; 71 struct QEMU_PACKED { 72 uint32_t min; 73 uint32_t max; 74 uint32_t next_cmd; 75 uint32_t stop; 76 /* Add registers here when adding capabilities. */ 77 uint32_t fifo[0]; 78 } *cmd; 79 }; 80 81 #define REDRAW_FIFO_LEN 512 82 struct vmsvga_rect_s { 83 int x, y, w, h; 84 } redraw_fifo[REDRAW_FIFO_LEN]; 85 int redraw_fifo_first, redraw_fifo_last; 86 }; 87 88 #define TYPE_VMWARE_SVGA "vmware-svga" 89 90 #define VMWARE_SVGA(obj) \ 91 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA) 92 93 struct pci_vmsvga_state_s { 94 /*< private >*/ 95 PCIDevice parent_obj; 96 /*< public >*/ 97 98 struct vmsvga_state_s chip; 99 MemoryRegion io_bar; 100 }; 101 102 #define SVGA_MAGIC 0x900000UL 103 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 104 #define SVGA_ID_0 SVGA_MAKE_ID(0) 105 #define SVGA_ID_1 SVGA_MAKE_ID(1) 106 #define SVGA_ID_2 SVGA_MAKE_ID(2) 107 108 #define SVGA_LEGACY_BASE_PORT 0x4560 109 #define SVGA_INDEX_PORT 0x0 110 #define SVGA_VALUE_PORT 0x1 111 #define SVGA_BIOS_PORT 0x2 112 113 #define SVGA_VERSION_2 114 115 #ifdef SVGA_VERSION_2 116 # define SVGA_ID SVGA_ID_2 117 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 118 # define SVGA_IO_MUL 1 119 # define SVGA_FIFO_SIZE 0x10000 120 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 121 #else 122 # define SVGA_ID SVGA_ID_1 123 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT 124 # define SVGA_IO_MUL 4 125 # define SVGA_FIFO_SIZE 0x10000 126 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA 127 #endif 128 129 enum { 130 /* ID 0, 1 and 2 registers */ 131 SVGA_REG_ID = 0, 132 SVGA_REG_ENABLE = 1, 133 SVGA_REG_WIDTH = 2, 134 SVGA_REG_HEIGHT = 3, 135 SVGA_REG_MAX_WIDTH = 4, 136 SVGA_REG_MAX_HEIGHT = 5, 137 SVGA_REG_DEPTH = 6, 138 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 139 SVGA_REG_PSEUDOCOLOR = 8, 140 SVGA_REG_RED_MASK = 9, 141 SVGA_REG_GREEN_MASK = 10, 142 SVGA_REG_BLUE_MASK = 11, 143 SVGA_REG_BYTES_PER_LINE = 12, 144 SVGA_REG_FB_START = 13, 145 SVGA_REG_FB_OFFSET = 14, 146 SVGA_REG_VRAM_SIZE = 15, 147 SVGA_REG_FB_SIZE = 16, 148 149 /* ID 1 and 2 registers */ 150 SVGA_REG_CAPABILITIES = 17, 151 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ 152 SVGA_REG_MEM_SIZE = 19, 153 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 154 SVGA_REG_SYNC = 21, /* Write to force synchronization */ 155 SVGA_REG_BUSY = 22, /* Read to check if sync is done */ 156 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 157 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ 158 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ 159 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ 160 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ 161 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ 162 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 163 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 164 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ 165 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 166 167 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 168 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, 169 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, 170 }; 171 172 #define SVGA_CAP_NONE 0 173 #define SVGA_CAP_RECT_FILL (1 << 0) 174 #define SVGA_CAP_RECT_COPY (1 << 1) 175 #define SVGA_CAP_RECT_PAT_FILL (1 << 2) 176 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) 177 #define SVGA_CAP_RASTER_OP (1 << 4) 178 #define SVGA_CAP_CURSOR (1 << 5) 179 #define SVGA_CAP_CURSOR_BYPASS (1 << 6) 180 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) 181 #define SVGA_CAP_8BIT_EMULATION (1 << 8) 182 #define SVGA_CAP_ALPHA_CURSOR (1 << 9) 183 #define SVGA_CAP_GLYPH (1 << 10) 184 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) 185 #define SVGA_CAP_OFFSCREEN_1 (1 << 12) 186 #define SVGA_CAP_ALPHA_BLEND (1 << 13) 187 #define SVGA_CAP_3D (1 << 14) 188 #define SVGA_CAP_EXTENDED_FIFO (1 << 15) 189 #define SVGA_CAP_MULTIMON (1 << 16) 190 #define SVGA_CAP_PITCHLOCK (1 << 17) 191 192 /* 193 * FIFO offsets (seen as an array of 32-bit words) 194 */ 195 enum { 196 /* 197 * The original defined FIFO offsets 198 */ 199 SVGA_FIFO_MIN = 0, 200 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 201 SVGA_FIFO_NEXT_CMD, 202 SVGA_FIFO_STOP, 203 204 /* 205 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO 206 */ 207 SVGA_FIFO_CAPABILITIES = 4, 208 SVGA_FIFO_FLAGS, 209 SVGA_FIFO_FENCE, 210 SVGA_FIFO_3D_HWVERSION, 211 SVGA_FIFO_PITCHLOCK, 212 }; 213 214 #define SVGA_FIFO_CAP_NONE 0 215 #define SVGA_FIFO_CAP_FENCE (1 << 0) 216 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 217 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 218 219 #define SVGA_FIFO_FLAG_NONE 0 220 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 221 222 /* These values can probably be changed arbitrarily. */ 223 #define SVGA_SCRATCH_SIZE 0x8000 224 #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT) 225 #define SVGA_MAX_HEIGHT 1770 226 227 #ifdef VERBOSE 228 # define GUEST_OS_BASE 0x5001 229 static const char *vmsvga_guest_id[] = { 230 [0x00] = "Dos", 231 [0x01] = "Windows 3.1", 232 [0x02] = "Windows 95", 233 [0x03] = "Windows 98", 234 [0x04] = "Windows ME", 235 [0x05] = "Windows NT", 236 [0x06] = "Windows 2000", 237 [0x07] = "Linux", 238 [0x08] = "OS/2", 239 [0x09] = "an unknown OS", 240 [0x0a] = "BSD", 241 [0x0b] = "Whistler", 242 [0x0c] = "an unknown OS", 243 [0x0d] = "an unknown OS", 244 [0x0e] = "an unknown OS", 245 [0x0f] = "an unknown OS", 246 [0x10] = "an unknown OS", 247 [0x11] = "an unknown OS", 248 [0x12] = "an unknown OS", 249 [0x13] = "an unknown OS", 250 [0x14] = "an unknown OS", 251 [0x15] = "Windows 2003", 252 }; 253 #endif 254 255 enum { 256 SVGA_CMD_INVALID_CMD = 0, 257 SVGA_CMD_UPDATE = 1, 258 SVGA_CMD_RECT_FILL = 2, 259 SVGA_CMD_RECT_COPY = 3, 260 SVGA_CMD_DEFINE_BITMAP = 4, 261 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, 262 SVGA_CMD_DEFINE_PIXMAP = 6, 263 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, 264 SVGA_CMD_RECT_BITMAP_FILL = 8, 265 SVGA_CMD_RECT_PIXMAP_FILL = 9, 266 SVGA_CMD_RECT_BITMAP_COPY = 10, 267 SVGA_CMD_RECT_PIXMAP_COPY = 11, 268 SVGA_CMD_FREE_OBJECT = 12, 269 SVGA_CMD_RECT_ROP_FILL = 13, 270 SVGA_CMD_RECT_ROP_COPY = 14, 271 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, 272 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, 273 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, 274 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, 275 SVGA_CMD_DEFINE_CURSOR = 19, 276 SVGA_CMD_DISPLAY_CURSOR = 20, 277 SVGA_CMD_MOVE_CURSOR = 21, 278 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 279 SVGA_CMD_DRAW_GLYPH = 23, 280 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, 281 SVGA_CMD_UPDATE_VERBOSE = 25, 282 SVGA_CMD_SURFACE_FILL = 26, 283 SVGA_CMD_SURFACE_COPY = 27, 284 SVGA_CMD_SURFACE_ALPHA_BLEND = 28, 285 SVGA_CMD_FRONT_ROP_FILL = 29, 286 SVGA_CMD_FENCE = 30, 287 }; 288 289 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ 290 enum { 291 SVGA_CURSOR_ON_HIDE = 0, 292 SVGA_CURSOR_ON_SHOW = 1, 293 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, 294 SVGA_CURSOR_ON_RESTORE_TO_FB = 3, 295 }; 296 297 static inline bool vmsvga_verify_rect(DisplaySurface *surface, 298 const char *name, 299 int x, int y, int w, int h) 300 { 301 if (x < 0) { 302 fprintf(stderr, "%s: x was < 0 (%d)\n", name, x); 303 return false; 304 } 305 if (x > SVGA_MAX_WIDTH) { 306 fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x); 307 return false; 308 } 309 if (w < 0) { 310 fprintf(stderr, "%s: w was < 0 (%d)\n", name, w); 311 return false; 312 } 313 if (w > SVGA_MAX_WIDTH) { 314 fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w); 315 return false; 316 } 317 if (x + w > surface_width(surface)) { 318 fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n", 319 name, surface_width(surface), x, w); 320 return false; 321 } 322 323 if (y < 0) { 324 fprintf(stderr, "%s: y was < 0 (%d)\n", name, y); 325 return false; 326 } 327 if (y > SVGA_MAX_HEIGHT) { 328 fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y); 329 return false; 330 } 331 if (h < 0) { 332 fprintf(stderr, "%s: h was < 0 (%d)\n", name, h); 333 return false; 334 } 335 if (h > SVGA_MAX_HEIGHT) { 336 fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h); 337 return false; 338 } 339 if (y + h > surface_height(surface)) { 340 fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n", 341 name, surface_height(surface), y, h); 342 return false; 343 } 344 345 return true; 346 } 347 348 static inline void vmsvga_update_rect(struct vmsvga_state_s *s, 349 int x, int y, int w, int h) 350 { 351 DisplaySurface *surface = qemu_console_surface(s->vga.con); 352 int line; 353 int bypl; 354 int width; 355 int start; 356 uint8_t *src; 357 uint8_t *dst; 358 359 if (x < 0) { 360 fprintf(stderr, "%s: update x was < 0 (%d)\n", __func__, x); 361 w += x; 362 x = 0; 363 } 364 if (w < 0) { 365 fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w); 366 w = 0; 367 } 368 if (x + w > surface_width(surface)) { 369 fprintf(stderr, "%s: update width too large x: %d, w: %d\n", 370 __func__, x, w); 371 x = MIN(x, surface_width(surface)); 372 w = surface_width(surface) - x; 373 } 374 375 if (y < 0) { 376 fprintf(stderr, "%s: update y was < 0 (%d)\n", __func__, y); 377 h += y; 378 y = 0; 379 } 380 if (h < 0) { 381 fprintf(stderr, "%s: update h was < 0 (%d)\n", __func__, h); 382 h = 0; 383 } 384 if (y + h > surface_height(surface)) { 385 fprintf(stderr, "%s: update height too large y: %d, h: %d\n", 386 __func__, y, h); 387 y = MIN(y, surface_height(surface)); 388 h = surface_height(surface) - y; 389 } 390 391 bypl = surface_stride(surface); 392 width = surface_bytes_per_pixel(surface) * w; 393 start = surface_bytes_per_pixel(surface) * x + bypl * y; 394 src = s->vga.vram_ptr + start; 395 dst = surface_data(surface) + start; 396 397 for (line = h; line > 0; line--, src += bypl, dst += bypl) { 398 memcpy(dst, src, width); 399 } 400 dpy_gfx_update(s->vga.con, x, y, w, h); 401 } 402 403 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, 404 int x, int y, int w, int h) 405 { 406 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; 407 408 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; 409 rect->x = x; 410 rect->y = y; 411 rect->w = w; 412 rect->h = h; 413 } 414 415 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) 416 { 417 struct vmsvga_rect_s *rect; 418 419 if (s->invalidated) { 420 s->redraw_fifo_first = s->redraw_fifo_last; 421 return; 422 } 423 /* Overlapping region updates can be optimised out here - if someone 424 * knows a smart algorithm to do that, please share. */ 425 while (s->redraw_fifo_first != s->redraw_fifo_last) { 426 rect = &s->redraw_fifo[s->redraw_fifo_first++]; 427 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; 428 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); 429 } 430 } 431 432 #ifdef HW_RECT_ACCEL 433 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, 434 int x0, int y0, int x1, int y1, int w, int h) 435 { 436 DisplaySurface *surface = qemu_console_surface(s->vga.con); 437 uint8_t *vram = s->vga.vram_ptr; 438 int bypl = surface_stride(surface); 439 int bypp = surface_bytes_per_pixel(surface); 440 int width = bypp * w; 441 int line = h; 442 uint8_t *ptr[2]; 443 444 if (y1 > y0) { 445 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); 446 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); 447 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { 448 memmove(ptr[1], ptr[0], width); 449 } 450 } else { 451 ptr[0] = vram + bypp * x0 + bypl * y0; 452 ptr[1] = vram + bypp * x1 + bypl * y1; 453 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { 454 memmove(ptr[1], ptr[0], width); 455 } 456 } 457 458 vmsvga_update_rect_delayed(s, x1, y1, w, h); 459 } 460 #endif 461 462 #ifdef HW_FILL_ACCEL 463 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, 464 uint32_t c, int x, int y, int w, int h) 465 { 466 DisplaySurface *surface = qemu_console_surface(s->vga.con); 467 int bypl = surface_stride(surface); 468 int width = surface_bytes_per_pixel(surface) * w; 469 int line = h; 470 int column; 471 uint8_t *fst; 472 uint8_t *dst; 473 uint8_t *src; 474 uint8_t col[4]; 475 476 col[0] = c; 477 col[1] = c >> 8; 478 col[2] = c >> 16; 479 col[3] = c >> 24; 480 481 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; 482 483 if (line--) { 484 dst = fst; 485 src = col; 486 for (column = width; column > 0; column--) { 487 *(dst++) = *(src++); 488 if (src - col == surface_bytes_per_pixel(surface)) { 489 src = col; 490 } 491 } 492 dst = fst; 493 for (; line > 0; line--) { 494 dst += bypl; 495 memcpy(dst, fst, width); 496 } 497 } 498 499 vmsvga_update_rect_delayed(s, x, y, w, h); 500 } 501 #endif 502 503 struct vmsvga_cursor_definition_s { 504 int width; 505 int height; 506 int id; 507 int bpp; 508 int hot_x; 509 int hot_y; 510 uint32_t mask[1024]; 511 uint32_t image[4096]; 512 }; 513 514 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) 515 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) 516 517 #ifdef HW_MOUSE_ACCEL 518 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, 519 struct vmsvga_cursor_definition_s *c) 520 { 521 QEMUCursor *qc; 522 int i, pixels; 523 524 qc = cursor_alloc(c->width, c->height); 525 qc->hot_x = c->hot_x; 526 qc->hot_y = c->hot_y; 527 switch (c->bpp) { 528 case 1: 529 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, 530 1, (void *)c->mask); 531 #ifdef DEBUG 532 cursor_print_ascii_art(qc, "vmware/mono"); 533 #endif 534 break; 535 case 32: 536 /* fill alpha channel from mask, set color to zero */ 537 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, 538 1, (void *)c->mask); 539 /* add in rgb values */ 540 pixels = c->width * c->height; 541 for (i = 0; i < pixels; i++) { 542 qc->data[i] |= c->image[i] & 0xffffff; 543 } 544 #ifdef DEBUG 545 cursor_print_ascii_art(qc, "vmware/32bit"); 546 #endif 547 break; 548 default: 549 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", 550 __func__, c->bpp); 551 cursor_put(qc); 552 qc = cursor_builtin_left_ptr(); 553 } 554 555 dpy_cursor_define(s->vga.con, qc); 556 cursor_put(qc); 557 } 558 #endif 559 560 #define CMD(f) le32_to_cpu(s->cmd->f) 561 562 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) 563 { 564 int num; 565 566 if (!s->config || !s->enable) { 567 return 0; 568 } 569 num = CMD(next_cmd) - CMD(stop); 570 if (num < 0) { 571 num += CMD(max) - CMD(min); 572 } 573 return num >> 2; 574 } 575 576 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) 577 { 578 uint32_t cmd = s->fifo[CMD(stop) >> 2]; 579 580 s->cmd->stop = cpu_to_le32(CMD(stop) + 4); 581 if (CMD(stop) >= CMD(max)) { 582 s->cmd->stop = s->cmd->min; 583 } 584 return cmd; 585 } 586 587 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) 588 { 589 return le32_to_cpu(vmsvga_fifo_read_raw(s)); 590 } 591 592 static void vmsvga_fifo_run(struct vmsvga_state_s *s) 593 { 594 uint32_t cmd, colour; 595 int args, len; 596 int x, y, dx, dy, width, height; 597 struct vmsvga_cursor_definition_s cursor; 598 uint32_t cmd_start; 599 600 len = vmsvga_fifo_length(s); 601 while (len > 0) { 602 /* May need to go back to the start of the command if incomplete */ 603 cmd_start = s->cmd->stop; 604 605 switch (cmd = vmsvga_fifo_read(s)) { 606 case SVGA_CMD_UPDATE: 607 case SVGA_CMD_UPDATE_VERBOSE: 608 len -= 5; 609 if (len < 0) { 610 goto rewind; 611 } 612 613 x = vmsvga_fifo_read(s); 614 y = vmsvga_fifo_read(s); 615 width = vmsvga_fifo_read(s); 616 height = vmsvga_fifo_read(s); 617 vmsvga_update_rect_delayed(s, x, y, width, height); 618 break; 619 620 case SVGA_CMD_RECT_FILL: 621 len -= 6; 622 if (len < 0) { 623 goto rewind; 624 } 625 626 colour = vmsvga_fifo_read(s); 627 x = vmsvga_fifo_read(s); 628 y = vmsvga_fifo_read(s); 629 width = vmsvga_fifo_read(s); 630 height = vmsvga_fifo_read(s); 631 #ifdef HW_FILL_ACCEL 632 vmsvga_fill_rect(s, colour, x, y, width, height); 633 break; 634 #else 635 args = 0; 636 goto badcmd; 637 #endif 638 639 case SVGA_CMD_RECT_COPY: 640 len -= 7; 641 if (len < 0) { 642 goto rewind; 643 } 644 645 x = vmsvga_fifo_read(s); 646 y = vmsvga_fifo_read(s); 647 dx = vmsvga_fifo_read(s); 648 dy = vmsvga_fifo_read(s); 649 width = vmsvga_fifo_read(s); 650 height = vmsvga_fifo_read(s); 651 #ifdef HW_RECT_ACCEL 652 vmsvga_copy_rect(s, x, y, dx, dy, width, height); 653 break; 654 #else 655 args = 0; 656 goto badcmd; 657 #endif 658 659 case SVGA_CMD_DEFINE_CURSOR: 660 len -= 8; 661 if (len < 0) { 662 goto rewind; 663 } 664 665 cursor.id = vmsvga_fifo_read(s); 666 cursor.hot_x = vmsvga_fifo_read(s); 667 cursor.hot_y = vmsvga_fifo_read(s); 668 cursor.width = x = vmsvga_fifo_read(s); 669 cursor.height = y = vmsvga_fifo_read(s); 670 vmsvga_fifo_read(s); 671 cursor.bpp = vmsvga_fifo_read(s); 672 673 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); 674 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || 675 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { 676 goto badcmd; 677 } 678 679 len -= args; 680 if (len < 0) { 681 goto rewind; 682 } 683 684 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { 685 cursor.mask[args] = vmsvga_fifo_read_raw(s); 686 } 687 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { 688 cursor.image[args] = vmsvga_fifo_read_raw(s); 689 } 690 #ifdef HW_MOUSE_ACCEL 691 vmsvga_cursor_define(s, &cursor); 692 break; 693 #else 694 args = 0; 695 goto badcmd; 696 #endif 697 698 /* 699 * Other commands that we at least know the number of arguments 700 * for so we can avoid FIFO desync if driver uses them illegally. 701 */ 702 case SVGA_CMD_DEFINE_ALPHA_CURSOR: 703 len -= 6; 704 if (len < 0) { 705 goto rewind; 706 } 707 vmsvga_fifo_read(s); 708 vmsvga_fifo_read(s); 709 vmsvga_fifo_read(s); 710 x = vmsvga_fifo_read(s); 711 y = vmsvga_fifo_read(s); 712 args = x * y; 713 goto badcmd; 714 case SVGA_CMD_RECT_ROP_FILL: 715 args = 6; 716 goto badcmd; 717 case SVGA_CMD_RECT_ROP_COPY: 718 args = 7; 719 goto badcmd; 720 case SVGA_CMD_DRAW_GLYPH_CLIPPED: 721 len -= 4; 722 if (len < 0) { 723 goto rewind; 724 } 725 vmsvga_fifo_read(s); 726 vmsvga_fifo_read(s); 727 args = 7 + (vmsvga_fifo_read(s) >> 2); 728 goto badcmd; 729 case SVGA_CMD_SURFACE_ALPHA_BLEND: 730 args = 12; 731 goto badcmd; 732 733 /* 734 * Other commands that are not listed as depending on any 735 * CAPABILITIES bits, but are not described in the README either. 736 */ 737 case SVGA_CMD_SURFACE_FILL: 738 case SVGA_CMD_SURFACE_COPY: 739 case SVGA_CMD_FRONT_ROP_FILL: 740 case SVGA_CMD_FENCE: 741 case SVGA_CMD_INVALID_CMD: 742 break; /* Nop */ 743 744 default: 745 args = 0; 746 badcmd: 747 len -= args; 748 if (len < 0) { 749 goto rewind; 750 } 751 while (args--) { 752 vmsvga_fifo_read(s); 753 } 754 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", 755 __func__, cmd); 756 break; 757 758 rewind: 759 s->cmd->stop = cmd_start; 760 break; 761 } 762 } 763 764 s->syncing = 0; 765 } 766 767 static uint32_t vmsvga_index_read(void *opaque, uint32_t address) 768 { 769 struct vmsvga_state_s *s = opaque; 770 771 return s->index; 772 } 773 774 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) 775 { 776 struct vmsvga_state_s *s = opaque; 777 778 s->index = index; 779 } 780 781 static uint32_t vmsvga_value_read(void *opaque, uint32_t address) 782 { 783 uint32_t caps; 784 struct vmsvga_state_s *s = opaque; 785 DisplaySurface *surface = qemu_console_surface(s->vga.con); 786 PixelFormat pf; 787 uint32_t ret; 788 789 switch (s->index) { 790 case SVGA_REG_ID: 791 ret = s->svgaid; 792 break; 793 794 case SVGA_REG_ENABLE: 795 ret = s->enable; 796 break; 797 798 case SVGA_REG_WIDTH: 799 ret = s->new_width ? s->new_width : surface_width(surface); 800 break; 801 802 case SVGA_REG_HEIGHT: 803 ret = s->new_height ? s->new_height : surface_height(surface); 804 break; 805 806 case SVGA_REG_MAX_WIDTH: 807 ret = SVGA_MAX_WIDTH; 808 break; 809 810 case SVGA_REG_MAX_HEIGHT: 811 ret = SVGA_MAX_HEIGHT; 812 break; 813 814 case SVGA_REG_DEPTH: 815 ret = (s->new_depth == 32) ? 24 : s->new_depth; 816 break; 817 818 case SVGA_REG_BITS_PER_PIXEL: 819 case SVGA_REG_HOST_BITS_PER_PIXEL: 820 ret = s->new_depth; 821 break; 822 823 case SVGA_REG_PSEUDOCOLOR: 824 ret = 0x0; 825 break; 826 827 case SVGA_REG_RED_MASK: 828 pf = qemu_default_pixelformat(s->new_depth); 829 ret = pf.rmask; 830 break; 831 832 case SVGA_REG_GREEN_MASK: 833 pf = qemu_default_pixelformat(s->new_depth); 834 ret = pf.gmask; 835 break; 836 837 case SVGA_REG_BLUE_MASK: 838 pf = qemu_default_pixelformat(s->new_depth); 839 ret = pf.bmask; 840 break; 841 842 case SVGA_REG_BYTES_PER_LINE: 843 if (s->new_width) { 844 ret = (s->new_depth * s->new_width) / 8; 845 } else { 846 ret = surface_stride(surface); 847 } 848 break; 849 850 case SVGA_REG_FB_START: { 851 struct pci_vmsvga_state_s *pci_vmsvga 852 = container_of(s, struct pci_vmsvga_state_s, chip); 853 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1); 854 break; 855 } 856 857 case SVGA_REG_FB_OFFSET: 858 ret = 0x0; 859 break; 860 861 case SVGA_REG_VRAM_SIZE: 862 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ 863 break; 864 865 case SVGA_REG_FB_SIZE: 866 ret = s->vga.vram_size; 867 break; 868 869 case SVGA_REG_CAPABILITIES: 870 caps = SVGA_CAP_NONE; 871 #ifdef HW_RECT_ACCEL 872 caps |= SVGA_CAP_RECT_COPY; 873 #endif 874 #ifdef HW_FILL_ACCEL 875 caps |= SVGA_CAP_RECT_FILL; 876 #endif 877 #ifdef HW_MOUSE_ACCEL 878 if (dpy_cursor_define_supported(s->vga.con)) { 879 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 880 SVGA_CAP_CURSOR_BYPASS; 881 } 882 #endif 883 ret = caps; 884 break; 885 886 case SVGA_REG_MEM_START: { 887 struct pci_vmsvga_state_s *pci_vmsvga 888 = container_of(s, struct pci_vmsvga_state_s, chip); 889 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2); 890 break; 891 } 892 893 case SVGA_REG_MEM_SIZE: 894 ret = s->fifo_size; 895 break; 896 897 case SVGA_REG_CONFIG_DONE: 898 ret = s->config; 899 break; 900 901 case SVGA_REG_SYNC: 902 case SVGA_REG_BUSY: 903 ret = s->syncing; 904 break; 905 906 case SVGA_REG_GUEST_ID: 907 ret = s->guest; 908 break; 909 910 case SVGA_REG_CURSOR_ID: 911 ret = s->cursor.id; 912 break; 913 914 case SVGA_REG_CURSOR_X: 915 ret = s->cursor.x; 916 break; 917 918 case SVGA_REG_CURSOR_Y: 919 ret = s->cursor.y; 920 break; 921 922 case SVGA_REG_CURSOR_ON: 923 ret = s->cursor.on; 924 break; 925 926 case SVGA_REG_SCRATCH_SIZE: 927 ret = s->scratch_size; 928 break; 929 930 case SVGA_REG_MEM_REGS: 931 case SVGA_REG_NUM_DISPLAYS: 932 case SVGA_REG_PITCHLOCK: 933 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 934 ret = 0; 935 break; 936 937 default: 938 if (s->index >= SVGA_SCRATCH_BASE && 939 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 940 ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; 941 break; 942 } 943 printf("%s: Bad register %02x\n", __func__, s->index); 944 ret = 0; 945 break; 946 } 947 948 if (s->index >= SVGA_SCRATCH_BASE) { 949 trace_vmware_scratch_read(s->index, ret); 950 } else if (s->index >= SVGA_PALETTE_BASE) { 951 trace_vmware_palette_read(s->index, ret); 952 } else { 953 trace_vmware_value_read(s->index, ret); 954 } 955 return ret; 956 } 957 958 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) 959 { 960 struct vmsvga_state_s *s = opaque; 961 962 if (s->index >= SVGA_SCRATCH_BASE) { 963 trace_vmware_scratch_write(s->index, value); 964 } else if (s->index >= SVGA_PALETTE_BASE) { 965 trace_vmware_palette_write(s->index, value); 966 } else { 967 trace_vmware_value_write(s->index, value); 968 } 969 switch (s->index) { 970 case SVGA_REG_ID: 971 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { 972 s->svgaid = value; 973 } 974 break; 975 976 case SVGA_REG_ENABLE: 977 s->enable = !!value; 978 s->invalidated = 1; 979 s->vga.hw_ops->invalidate(&s->vga); 980 if (s->enable && s->config) { 981 vga_dirty_log_stop(&s->vga); 982 } else { 983 vga_dirty_log_start(&s->vga); 984 } 985 break; 986 987 case SVGA_REG_WIDTH: 988 if (value <= SVGA_MAX_WIDTH) { 989 s->new_width = value; 990 s->invalidated = 1; 991 } else { 992 printf("%s: Bad width: %i\n", __func__, value); 993 } 994 break; 995 996 case SVGA_REG_HEIGHT: 997 if (value <= SVGA_MAX_HEIGHT) { 998 s->new_height = value; 999 s->invalidated = 1; 1000 } else { 1001 printf("%s: Bad height: %i\n", __func__, value); 1002 } 1003 break; 1004 1005 case SVGA_REG_BITS_PER_PIXEL: 1006 if (value != 32) { 1007 printf("%s: Bad bits per pixel: %i bits\n", __func__, value); 1008 s->config = 0; 1009 s->invalidated = 1; 1010 } 1011 break; 1012 1013 case SVGA_REG_CONFIG_DONE: 1014 if (value) { 1015 s->fifo = (uint32_t *) s->fifo_ptr; 1016 /* Check range and alignment. */ 1017 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { 1018 break; 1019 } 1020 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { 1021 break; 1022 } 1023 if (CMD(max) > SVGA_FIFO_SIZE) { 1024 break; 1025 } 1026 if (CMD(max) < CMD(min) + 10 * 1024) { 1027 break; 1028 } 1029 vga_dirty_log_stop(&s->vga); 1030 } 1031 s->config = !!value; 1032 break; 1033 1034 case SVGA_REG_SYNC: 1035 s->syncing = 1; 1036 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ 1037 break; 1038 1039 case SVGA_REG_GUEST_ID: 1040 s->guest = value; 1041 #ifdef VERBOSE 1042 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + 1043 ARRAY_SIZE(vmsvga_guest_id)) { 1044 printf("%s: guest runs %s.\n", __func__, 1045 vmsvga_guest_id[value - GUEST_OS_BASE]); 1046 } 1047 #endif 1048 break; 1049 1050 case SVGA_REG_CURSOR_ID: 1051 s->cursor.id = value; 1052 break; 1053 1054 case SVGA_REG_CURSOR_X: 1055 s->cursor.x = value; 1056 break; 1057 1058 case SVGA_REG_CURSOR_Y: 1059 s->cursor.y = value; 1060 break; 1061 1062 case SVGA_REG_CURSOR_ON: 1063 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 1064 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 1065 #ifdef HW_MOUSE_ACCEL 1066 if (value <= SVGA_CURSOR_ON_SHOW) { 1067 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); 1068 } 1069 #endif 1070 break; 1071 1072 case SVGA_REG_DEPTH: 1073 case SVGA_REG_MEM_REGS: 1074 case SVGA_REG_NUM_DISPLAYS: 1075 case SVGA_REG_PITCHLOCK: 1076 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: 1077 break; 1078 1079 default: 1080 if (s->index >= SVGA_SCRATCH_BASE && 1081 s->index < SVGA_SCRATCH_BASE + s->scratch_size) { 1082 s->scratch[s->index - SVGA_SCRATCH_BASE] = value; 1083 break; 1084 } 1085 printf("%s: Bad register %02x\n", __func__, s->index); 1086 } 1087 } 1088 1089 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) 1090 { 1091 printf("%s: what are we supposed to return?\n", __func__); 1092 return 0xcafe; 1093 } 1094 1095 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) 1096 { 1097 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); 1098 } 1099 1100 static inline void vmsvga_check_size(struct vmsvga_state_s *s) 1101 { 1102 DisplaySurface *surface = qemu_console_surface(s->vga.con); 1103 1104 if (s->new_width != surface_width(surface) || 1105 s->new_height != surface_height(surface) || 1106 s->new_depth != surface_bits_per_pixel(surface)) { 1107 int stride = (s->new_depth * s->new_width) / 8; 1108 pixman_format_code_t format = 1109 qemu_default_pixman_format(s->new_depth, true); 1110 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); 1111 surface = qemu_create_displaysurface_from(s->new_width, s->new_height, 1112 format, stride, 1113 s->vga.vram_ptr); 1114 dpy_gfx_replace_surface(s->vga.con, surface); 1115 s->invalidated = 1; 1116 } 1117 } 1118 1119 static void vmsvga_update_display(void *opaque) 1120 { 1121 struct vmsvga_state_s *s = opaque; 1122 DisplaySurface *surface; 1123 bool dirty = false; 1124 1125 if (!s->enable) { 1126 s->vga.hw_ops->gfx_update(&s->vga); 1127 return; 1128 } 1129 1130 vmsvga_check_size(s); 1131 surface = qemu_console_surface(s->vga.con); 1132 1133 vmsvga_fifo_run(s); 1134 vmsvga_update_rect_flush(s); 1135 1136 /* 1137 * Is it more efficient to look at vram VGA-dirty bits or wait 1138 * for the driver to issue SVGA_CMD_UPDATE? 1139 */ 1140 if (memory_region_is_logging(&s->vga.vram)) { 1141 vga_sync_dirty_bitmap(&s->vga); 1142 dirty = memory_region_get_dirty(&s->vga.vram, 0, 1143 surface_stride(surface) * surface_height(surface), 1144 DIRTY_MEMORY_VGA); 1145 } 1146 if (s->invalidated || dirty) { 1147 s->invalidated = 0; 1148 dpy_gfx_update(s->vga.con, 0, 0, 1149 surface_width(surface), surface_height(surface)); 1150 } 1151 if (dirty) { 1152 memory_region_reset_dirty(&s->vga.vram, 0, 1153 surface_stride(surface) * surface_height(surface), 1154 DIRTY_MEMORY_VGA); 1155 } 1156 } 1157 1158 static void vmsvga_reset(DeviceState *dev) 1159 { 1160 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev); 1161 struct vmsvga_state_s *s = &pci->chip; 1162 1163 s->index = 0; 1164 s->enable = 0; 1165 s->config = 0; 1166 s->svgaid = SVGA_ID; 1167 s->cursor.on = 0; 1168 s->redraw_fifo_first = 0; 1169 s->redraw_fifo_last = 0; 1170 s->syncing = 0; 1171 1172 vga_dirty_log_start(&s->vga); 1173 } 1174 1175 static void vmsvga_invalidate_display(void *opaque) 1176 { 1177 struct vmsvga_state_s *s = opaque; 1178 if (!s->enable) { 1179 s->vga.hw_ops->invalidate(&s->vga); 1180 return; 1181 } 1182 1183 s->invalidated = 1; 1184 } 1185 1186 static void vmsvga_text_update(void *opaque, console_ch_t *chardata) 1187 { 1188 struct vmsvga_state_s *s = opaque; 1189 1190 if (s->vga.hw_ops->text_update) { 1191 s->vga.hw_ops->text_update(&s->vga, chardata); 1192 } 1193 } 1194 1195 static int vmsvga_post_load(void *opaque, int version_id) 1196 { 1197 struct vmsvga_state_s *s = opaque; 1198 1199 s->invalidated = 1; 1200 if (s->config) { 1201 s->fifo = (uint32_t *) s->fifo_ptr; 1202 } 1203 return 0; 1204 } 1205 1206 static const VMStateDescription vmstate_vmware_vga_internal = { 1207 .name = "vmware_vga_internal", 1208 .version_id = 0, 1209 .minimum_version_id = 0, 1210 .post_load = vmsvga_post_load, 1211 .fields = (VMStateField[]) { 1212 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), 1213 VMSTATE_INT32(enable, struct vmsvga_state_s), 1214 VMSTATE_INT32(config, struct vmsvga_state_s), 1215 VMSTATE_INT32(cursor.id, struct vmsvga_state_s), 1216 VMSTATE_INT32(cursor.x, struct vmsvga_state_s), 1217 VMSTATE_INT32(cursor.y, struct vmsvga_state_s), 1218 VMSTATE_INT32(cursor.on, struct vmsvga_state_s), 1219 VMSTATE_INT32(index, struct vmsvga_state_s), 1220 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, 1221 scratch_size, 0, vmstate_info_uint32, uint32_t), 1222 VMSTATE_INT32(new_width, struct vmsvga_state_s), 1223 VMSTATE_INT32(new_height, struct vmsvga_state_s), 1224 VMSTATE_UINT32(guest, struct vmsvga_state_s), 1225 VMSTATE_UINT32(svgaid, struct vmsvga_state_s), 1226 VMSTATE_INT32(syncing, struct vmsvga_state_s), 1227 VMSTATE_UNUSED(4), /* was fb_size */ 1228 VMSTATE_END_OF_LIST() 1229 } 1230 }; 1231 1232 static const VMStateDescription vmstate_vmware_vga = { 1233 .name = "vmware_vga", 1234 .version_id = 0, 1235 .minimum_version_id = 0, 1236 .fields = (VMStateField[]) { 1237 VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s), 1238 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, 1239 vmstate_vmware_vga_internal, struct vmsvga_state_s), 1240 VMSTATE_END_OF_LIST() 1241 } 1242 }; 1243 1244 static const GraphicHwOps vmsvga_ops = { 1245 .invalidate = vmsvga_invalidate_display, 1246 .gfx_update = vmsvga_update_display, 1247 .text_update = vmsvga_text_update, 1248 }; 1249 1250 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, 1251 MemoryRegion *address_space, MemoryRegion *io) 1252 { 1253 s->scratch_size = SVGA_SCRATCH_SIZE; 1254 s->scratch = g_malloc(s->scratch_size * 4); 1255 1256 s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s); 1257 1258 s->fifo_size = SVGA_FIFO_SIZE; 1259 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, 1260 &error_abort); 1261 vmstate_register_ram_global(&s->fifo_ram); 1262 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); 1263 1264 vga_common_init(&s->vga, OBJECT(dev), true); 1265 vga_init(&s->vga, OBJECT(dev), address_space, io, true); 1266 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); 1267 s->new_depth = 32; 1268 } 1269 1270 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) 1271 { 1272 struct vmsvga_state_s *s = opaque; 1273 1274 switch (addr) { 1275 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); 1276 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); 1277 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); 1278 default: return -1u; 1279 } 1280 } 1281 1282 static void vmsvga_io_write(void *opaque, hwaddr addr, 1283 uint64_t data, unsigned size) 1284 { 1285 struct vmsvga_state_s *s = opaque; 1286 1287 switch (addr) { 1288 case SVGA_IO_MUL * SVGA_INDEX_PORT: 1289 vmsvga_index_write(s, addr, data); 1290 break; 1291 case SVGA_IO_MUL * SVGA_VALUE_PORT: 1292 vmsvga_value_write(s, addr, data); 1293 break; 1294 case SVGA_IO_MUL * SVGA_BIOS_PORT: 1295 vmsvga_bios_write(s, addr, data); 1296 break; 1297 } 1298 } 1299 1300 static const MemoryRegionOps vmsvga_io_ops = { 1301 .read = vmsvga_io_read, 1302 .write = vmsvga_io_write, 1303 .endianness = DEVICE_LITTLE_ENDIAN, 1304 .valid = { 1305 .min_access_size = 4, 1306 .max_access_size = 4, 1307 .unaligned = true, 1308 }, 1309 .impl = { 1310 .unaligned = true, 1311 }, 1312 }; 1313 1314 static int pci_vmsvga_initfn(PCIDevice *dev) 1315 { 1316 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev); 1317 1318 dev->config[PCI_CACHE_LINE_SIZE] = 0x08; 1319 dev->config[PCI_LATENCY_TIMER] = 0x40; 1320 dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */ 1321 1322 memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, 1323 "vmsvga-io", 0x10); 1324 memory_region_set_flush_coalesced(&s->io_bar); 1325 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1326 1327 vmsvga_init(DEVICE(dev), &s->chip, 1328 pci_address_space(dev), pci_address_space_io(dev)); 1329 1330 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, 1331 &s->chip.vga.vram); 1332 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, 1333 &s->chip.fifo_ram); 1334 1335 if (!dev->rom_bar) { 1336 /* compatibility with pc-0.13 and older */ 1337 vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev)); 1338 } 1339 1340 return 0; 1341 } 1342 1343 static Property vga_vmware_properties[] = { 1344 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, 1345 chip.vga.vram_size_mb, 16), 1346 DEFINE_PROP_END_OF_LIST(), 1347 }; 1348 1349 static void vmsvga_class_init(ObjectClass *klass, void *data) 1350 { 1351 DeviceClass *dc = DEVICE_CLASS(klass); 1352 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1353 1354 k->init = pci_vmsvga_initfn; 1355 k->romfile = "vgabios-vmware.bin"; 1356 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1357 k->device_id = SVGA_PCI_DEVICE_ID; 1358 k->class_id = PCI_CLASS_DISPLAY_VGA; 1359 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 1360 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1361 dc->reset = vmsvga_reset; 1362 dc->vmsd = &vmstate_vmware_vga; 1363 dc->props = vga_vmware_properties; 1364 dc->hotpluggable = false; 1365 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1366 } 1367 1368 static const TypeInfo vmsvga_info = { 1369 .name = TYPE_VMWARE_SVGA, 1370 .parent = TYPE_PCI_DEVICE, 1371 .instance_size = sizeof(struct pci_vmsvga_state_s), 1372 .class_init = vmsvga_class_init, 1373 }; 1374 1375 static void vmsvga_register_types(void) 1376 { 1377 type_register_static(&vmsvga_info); 1378 } 1379 1380 type_init(vmsvga_register_types) 1381