1 /* 2 * QEMU SM501 Device 3 * 4 * Copyright (c) 2008 Shin-ichiro KAWASAKI 5 * Copyright (c) 2016-2020 BALATON Zoltan 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qapi/error.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 #include "hw/usb/hcd-ohci.h" 32 #include "hw/char/serial.h" 33 #include "ui/console.h" 34 #include "hw/sysbus.h" 35 #include "migration/vmstate.h" 36 #include "hw/pci/pci_device.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/i2c/i2c.h" 39 #include "hw/display/i2c-ddc.h" 40 #include "qemu/range.h" 41 #include "ui/pixel_ops.h" 42 #include "qemu/bswap.h" 43 #include "trace.h" 44 #include "qom/object.h" 45 46 #define MMIO_BASE_OFFSET 0x3e00000 47 #define MMIO_SIZE 0x200000 48 #define DC_PALETTE_ENTRIES (0x400 * 3) 49 50 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */ 51 52 /* System Configuration area */ 53 /* System config base */ 54 #define SM501_SYS_CONFIG 0x000000 55 56 /* config 1 */ 57 #define SM501_SYSTEM_CONTROL 0x000000 58 59 #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) 60 #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) 61 #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) 62 63 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) 64 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) 65 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) 66 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) 67 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) 68 69 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) 70 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) 71 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) 72 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) 73 74 /* miscellaneous control */ 75 76 #define SM501_MISC_CONTROL 0x000004 77 78 #define SM501_MISC_BUS_SH 0x0 79 #define SM501_MISC_BUS_PCI 0x1 80 #define SM501_MISC_BUS_XSCALE 0x2 81 #define SM501_MISC_BUS_NEC 0x6 82 #define SM501_MISC_BUS_MASK 0x7 83 84 #define SM501_MISC_VR_62MB (1 << 3) 85 #define SM501_MISC_CDR_RESET (1 << 7) 86 #define SM501_MISC_USB_LB (1 << 8) 87 #define SM501_MISC_USB_SLAVE (1 << 9) 88 #define SM501_MISC_BL_1 (1 << 10) 89 #define SM501_MISC_MC (1 << 11) 90 #define SM501_MISC_DAC_POWER (1 << 12) 91 #define SM501_MISC_IRQ_INVERT (1 << 16) 92 #define SM501_MISC_SH (1 << 17) 93 94 #define SM501_MISC_HOLD_EMPTY (0 << 18) 95 #define SM501_MISC_HOLD_8 (1 << 18) 96 #define SM501_MISC_HOLD_16 (2 << 18) 97 #define SM501_MISC_HOLD_24 (3 << 18) 98 #define SM501_MISC_HOLD_32 (4 << 18) 99 #define SM501_MISC_HOLD_MASK (7 << 18) 100 101 #define SM501_MISC_FREQ_12 (1 << 24) 102 #define SM501_MISC_PNL_24BIT (1 << 25) 103 #define SM501_MISC_8051_LE (1 << 26) 104 105 106 107 #define SM501_GPIO31_0_CONTROL 0x000008 108 #define SM501_GPIO63_32_CONTROL 0x00000C 109 #define SM501_DRAM_CONTROL 0x000010 110 111 /* command list */ 112 #define SM501_ARBTRTN_CONTROL 0x000014 113 114 /* command list */ 115 #define SM501_COMMAND_LIST_STATUS 0x000024 116 117 /* interrupt debug */ 118 #define SM501_RAW_IRQ_STATUS 0x000028 119 #define SM501_RAW_IRQ_CLEAR 0x000028 120 #define SM501_IRQ_STATUS 0x00002C 121 #define SM501_IRQ_MASK 0x000030 122 #define SM501_DEBUG_CONTROL 0x000034 123 124 /* power management */ 125 #define SM501_POWERMODE_P2X_SRC (1 << 29) 126 #define SM501_POWERMODE_V2X_SRC (1 << 20) 127 #define SM501_POWERMODE_M_SRC (1 << 12) 128 #define SM501_POWERMODE_M1_SRC (1 << 4) 129 130 #define SM501_CURRENT_GATE 0x000038 131 #define SM501_CURRENT_CLOCK 0x00003C 132 #define SM501_POWER_MODE_0_GATE 0x000040 133 #define SM501_POWER_MODE_0_CLOCK 0x000044 134 #define SM501_POWER_MODE_1_GATE 0x000048 135 #define SM501_POWER_MODE_1_CLOCK 0x00004C 136 #define SM501_SLEEP_MODE_GATE 0x000050 137 #define SM501_POWER_MODE_CONTROL 0x000054 138 139 /* power gates for units within the 501 */ 140 #define SM501_GATE_HOST 0 141 #define SM501_GATE_MEMORY 1 142 #define SM501_GATE_DISPLAY 2 143 #define SM501_GATE_2D_ENGINE 3 144 #define SM501_GATE_CSC 4 145 #define SM501_GATE_ZVPORT 5 146 #define SM501_GATE_GPIO 6 147 #define SM501_GATE_UART0 7 148 #define SM501_GATE_UART1 8 149 #define SM501_GATE_SSP 10 150 #define SM501_GATE_USB_HOST 11 151 #define SM501_GATE_USB_GADGET 12 152 #define SM501_GATE_UCONTROLLER 17 153 #define SM501_GATE_AC97 18 154 155 /* panel clock */ 156 #define SM501_CLOCK_P2XCLK 24 157 /* crt clock */ 158 #define SM501_CLOCK_V2XCLK 16 159 /* main clock */ 160 #define SM501_CLOCK_MCLK 8 161 /* SDRAM controller clock */ 162 #define SM501_CLOCK_M1XCLK 0 163 164 /* config 2 */ 165 #define SM501_PCI_MASTER_BASE 0x000058 166 #define SM501_ENDIAN_CONTROL 0x00005C 167 #define SM501_DEVICEID 0x000060 168 /* 0x050100A0 */ 169 170 #define SM501_DEVICEID_SM501 0x05010000 171 #define SM501_DEVICEID_IDMASK 0xffff0000 172 #define SM501_DEVICEID_REVMASK 0x000000ff 173 174 #define SM501_PLLCLOCK_COUNT 0x000064 175 #define SM501_MISC_TIMING 0x000068 176 #define SM501_CURRENT_SDRAM_CLOCK 0x00006C 177 178 #define SM501_PROGRAMMABLE_PLL_CONTROL 0x000074 179 180 /* GPIO base */ 181 #define SM501_GPIO 0x010000 182 #define SM501_GPIO_DATA_LOW 0x00 183 #define SM501_GPIO_DATA_HIGH 0x04 184 #define SM501_GPIO_DDR_LOW 0x08 185 #define SM501_GPIO_DDR_HIGH 0x0C 186 #define SM501_GPIO_IRQ_SETUP 0x10 187 #define SM501_GPIO_IRQ_STATUS 0x14 188 #define SM501_GPIO_IRQ_RESET 0x14 189 190 /* I2C controller base */ 191 #define SM501_I2C 0x010040 192 #define SM501_I2C_BYTE_COUNT 0x00 193 #define SM501_I2C_CONTROL 0x01 194 #define SM501_I2C_STATUS 0x02 195 #define SM501_I2C_RESET 0x02 196 #define SM501_I2C_SLAVE_ADDRESS 0x03 197 #define SM501_I2C_DATA 0x04 198 199 #define SM501_I2C_CONTROL_START (1 << 2) 200 #define SM501_I2C_CONTROL_ENABLE (1 << 0) 201 202 #define SM501_I2C_STATUS_COMPLETE (1 << 3) 203 #define SM501_I2C_STATUS_ERROR (1 << 2) 204 205 #define SM501_I2C_RESET_ERROR (1 << 2) 206 207 /* SSP base */ 208 #define SM501_SSP 0x020000 209 210 /* Uart 0 base */ 211 #define SM501_UART0 0x030000 212 213 /* Uart 1 base */ 214 #define SM501_UART1 0x030020 215 216 /* USB host port base */ 217 #define SM501_USB_HOST 0x040000 218 219 /* USB slave/gadget base */ 220 #define SM501_USB_GADGET 0x060000 221 222 /* USB slave/gadget data port base */ 223 #define SM501_USB_GADGET_DATA 0x070000 224 225 /* Display controller/video engine base */ 226 #define SM501_DC 0x080000 227 228 /* common defines for the SM501 address registers */ 229 #define SM501_ADDR_FLIP (1 << 31) 230 #define SM501_ADDR_EXT (1 << 27) 231 #define SM501_ADDR_CS1 (1 << 26) 232 #define SM501_ADDR_MASK (0x3f << 26) 233 234 #define SM501_FIFO_MASK (0x3 << 16) 235 #define SM501_FIFO_1 (0x0 << 16) 236 #define SM501_FIFO_3 (0x1 << 16) 237 #define SM501_FIFO_7 (0x2 << 16) 238 #define SM501_FIFO_11 (0x3 << 16) 239 240 /* common registers for panel and the crt */ 241 #define SM501_OFF_DC_H_TOT 0x000 242 #define SM501_OFF_DC_V_TOT 0x008 243 #define SM501_OFF_DC_H_SYNC 0x004 244 #define SM501_OFF_DC_V_SYNC 0x00C 245 246 #define SM501_DC_PANEL_CONTROL 0x000 247 248 #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) 249 #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) 250 #define SM501_DC_PANEL_CONTROL_DATA (1 << 25) 251 #define SM501_DC_PANEL_CONTROL_VDD (1 << 24) 252 #define SM501_DC_PANEL_CONTROL_DP (1 << 23) 253 254 #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) 255 #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) 256 #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) 257 258 #define SM501_DC_PANEL_CONTROL_DE (1 << 20) 259 260 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) 261 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) 262 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) 263 264 #define SM501_DC_PANEL_CONTROL_CP (1 << 14) 265 #define SM501_DC_PANEL_CONTROL_VSP (1 << 13) 266 #define SM501_DC_PANEL_CONTROL_HSP (1 << 12) 267 #define SM501_DC_PANEL_CONTROL_CK (1 << 9) 268 #define SM501_DC_PANEL_CONTROL_TE (1 << 8) 269 #define SM501_DC_PANEL_CONTROL_VPD (1 << 7) 270 #define SM501_DC_PANEL_CONTROL_VP (1 << 6) 271 #define SM501_DC_PANEL_CONTROL_HPD (1 << 5) 272 #define SM501_DC_PANEL_CONTROL_HP (1 << 4) 273 #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) 274 #define SM501_DC_PANEL_CONTROL_EN (1 << 2) 275 276 #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) 277 #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) 278 #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) 279 280 281 #define SM501_DC_PANEL_PANNING_CONTROL 0x004 282 #define SM501_DC_PANEL_COLOR_KEY 0x008 283 #define SM501_DC_PANEL_FB_ADDR 0x00C 284 #define SM501_DC_PANEL_FB_OFFSET 0x010 285 #define SM501_DC_PANEL_FB_WIDTH 0x014 286 #define SM501_DC_PANEL_FB_HEIGHT 0x018 287 #define SM501_DC_PANEL_TL_LOC 0x01C 288 #define SM501_DC_PANEL_BR_LOC 0x020 289 #define SM501_DC_PANEL_H_TOT 0x024 290 #define SM501_DC_PANEL_H_SYNC 0x028 291 #define SM501_DC_PANEL_V_TOT 0x02C 292 #define SM501_DC_PANEL_V_SYNC 0x030 293 #define SM501_DC_PANEL_CUR_LINE 0x034 294 295 #define SM501_DC_VIDEO_CONTROL 0x040 296 #define SM501_DC_VIDEO_FB0_ADDR 0x044 297 #define SM501_DC_VIDEO_FB_WIDTH 0x048 298 #define SM501_DC_VIDEO_FB0_LAST_ADDR 0x04C 299 #define SM501_DC_VIDEO_TL_LOC 0x050 300 #define SM501_DC_VIDEO_BR_LOC 0x054 301 #define SM501_DC_VIDEO_SCALE 0x058 302 #define SM501_DC_VIDEO_INIT_SCALE 0x05C 303 #define SM501_DC_VIDEO_YUV_CONSTANTS 0x060 304 #define SM501_DC_VIDEO_FB1_ADDR 0x064 305 #define SM501_DC_VIDEO_FB1_LAST_ADDR 0x068 306 307 #define SM501_DC_VIDEO_ALPHA_CONTROL 0x080 308 #define SM501_DC_VIDEO_ALPHA_FB_ADDR 0x084 309 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET 0x088 310 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR 0x08C 311 #define SM501_DC_VIDEO_ALPHA_TL_LOC 0x090 312 #define SM501_DC_VIDEO_ALPHA_BR_LOC 0x094 313 #define SM501_DC_VIDEO_ALPHA_SCALE 0x098 314 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE 0x09C 315 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY 0x0A0 316 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP 0x0A4 317 318 #define SM501_DC_PANEL_HWC_BASE 0x0F0 319 #define SM501_DC_PANEL_HWC_ADDR 0x0F0 320 #define SM501_DC_PANEL_HWC_LOC 0x0F4 321 #define SM501_DC_PANEL_HWC_COLOR_1_2 0x0F8 322 #define SM501_DC_PANEL_HWC_COLOR_3 0x0FC 323 324 #define SM501_HWC_EN (1 << 31) 325 326 #define SM501_OFF_HWC_ADDR 0x00 327 #define SM501_OFF_HWC_LOC 0x04 328 #define SM501_OFF_HWC_COLOR_1_2 0x08 329 #define SM501_OFF_HWC_COLOR_3 0x0C 330 331 #define SM501_DC_ALPHA_CONTROL 0x100 332 #define SM501_DC_ALPHA_FB_ADDR 0x104 333 #define SM501_DC_ALPHA_FB_OFFSET 0x108 334 #define SM501_DC_ALPHA_TL_LOC 0x10C 335 #define SM501_DC_ALPHA_BR_LOC 0x110 336 #define SM501_DC_ALPHA_CHROMA_KEY 0x114 337 #define SM501_DC_ALPHA_COLOR_LOOKUP 0x118 338 339 #define SM501_DC_CRT_CONTROL 0x200 340 341 #define SM501_DC_CRT_CONTROL_TVP (1 << 15) 342 #define SM501_DC_CRT_CONTROL_CP (1 << 14) 343 #define SM501_DC_CRT_CONTROL_VSP (1 << 13) 344 #define SM501_DC_CRT_CONTROL_HSP (1 << 12) 345 #define SM501_DC_CRT_CONTROL_VS (1 << 11) 346 #define SM501_DC_CRT_CONTROL_BLANK (1 << 10) 347 #define SM501_DC_CRT_CONTROL_SEL (1 << 9) 348 #define SM501_DC_CRT_CONTROL_TE (1 << 8) 349 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) 350 #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) 351 #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) 352 353 #define SM501_DC_CRT_CONTROL_8BPP (0 << 0) 354 #define SM501_DC_CRT_CONTROL_16BPP (1 << 0) 355 #define SM501_DC_CRT_CONTROL_32BPP (2 << 0) 356 357 #define SM501_DC_CRT_FB_ADDR 0x204 358 #define SM501_DC_CRT_FB_OFFSET 0x208 359 #define SM501_DC_CRT_H_TOT 0x20C 360 #define SM501_DC_CRT_H_SYNC 0x210 361 #define SM501_DC_CRT_V_TOT 0x214 362 #define SM501_DC_CRT_V_SYNC 0x218 363 #define SM501_DC_CRT_SIGNATURE_ANALYZER 0x21C 364 #define SM501_DC_CRT_CUR_LINE 0x220 365 #define SM501_DC_CRT_MONITOR_DETECT 0x224 366 367 #define SM501_DC_CRT_HWC_BASE 0x230 368 #define SM501_DC_CRT_HWC_ADDR 0x230 369 #define SM501_DC_CRT_HWC_LOC 0x234 370 #define SM501_DC_CRT_HWC_COLOR_1_2 0x238 371 #define SM501_DC_CRT_HWC_COLOR_3 0x23C 372 373 #define SM501_DC_PANEL_PALETTE 0x400 374 375 #define SM501_DC_VIDEO_PALETTE 0x800 376 377 #define SM501_DC_CRT_PALETTE 0xC00 378 379 /* Zoom Video port base */ 380 #define SM501_ZVPORT 0x090000 381 382 /* AC97/I2S base */ 383 #define SM501_AC97 0x0A0000 384 385 /* 8051 micro controller base */ 386 #define SM501_UCONTROLLER 0x0B0000 387 388 /* 8051 micro controller SRAM base */ 389 #define SM501_UCONTROLLER_SRAM 0x0C0000 390 391 /* DMA base */ 392 #define SM501_DMA 0x0D0000 393 394 /* 2d engine base */ 395 #define SM501_2D_ENGINE 0x100000 396 #define SM501_2D_SOURCE 0x00 397 #define SM501_2D_DESTINATION 0x04 398 #define SM501_2D_DIMENSION 0x08 399 #define SM501_2D_CONTROL 0x0C 400 #define SM501_2D_PITCH 0x10 401 #define SM501_2D_FOREGROUND 0x14 402 #define SM501_2D_BACKGROUND 0x18 403 #define SM501_2D_STRETCH 0x1C 404 #define SM501_2D_COLOR_COMPARE 0x20 405 #define SM501_2D_COLOR_COMPARE_MASK 0x24 406 #define SM501_2D_MASK 0x28 407 #define SM501_2D_CLIP_TL 0x2C 408 #define SM501_2D_CLIP_BR 0x30 409 #define SM501_2D_MONO_PATTERN_LOW 0x34 410 #define SM501_2D_MONO_PATTERN_HIGH 0x38 411 #define SM501_2D_WINDOW_WIDTH 0x3C 412 #define SM501_2D_SOURCE_BASE 0x40 413 #define SM501_2D_DESTINATION_BASE 0x44 414 #define SM501_2D_ALPHA 0x48 415 #define SM501_2D_WRAP 0x4C 416 #define SM501_2D_STATUS 0x50 417 418 #define SM501_CSC_Y_SOURCE_BASE 0xC8 419 #define SM501_CSC_CONSTANTS 0xCC 420 #define SM501_CSC_Y_SOURCE_X 0xD0 421 #define SM501_CSC_Y_SOURCE_Y 0xD4 422 #define SM501_CSC_U_SOURCE_BASE 0xD8 423 #define SM501_CSC_V_SOURCE_BASE 0xDC 424 #define SM501_CSC_SOURCE_DIMENSION 0xE0 425 #define SM501_CSC_SOURCE_PITCH 0xE4 426 #define SM501_CSC_DESTINATION 0xE8 427 #define SM501_CSC_DESTINATION_DIMENSION 0xEC 428 #define SM501_CSC_DESTINATION_PITCH 0xF0 429 #define SM501_CSC_SCALE_FACTOR 0xF4 430 #define SM501_CSC_DESTINATION_BASE 0xF8 431 #define SM501_CSC_CONTROL 0xFC 432 433 /* 2d engine data port base */ 434 #define SM501_2D_ENGINE_DATA 0x110000 435 436 /* end of register definitions */ 437 438 #define SM501_HWC_WIDTH 64 439 #define SM501_HWC_HEIGHT 64 440 441 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ 442 static const uint32_t sm501_mem_local_size[] = { 443 [0] = 4 * MiB, 444 [1] = 8 * MiB, 445 [2] = 16 * MiB, 446 [3] = 32 * MiB, 447 [4] = 64 * MiB, 448 [5] = 2 * MiB, 449 }; 450 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index] 451 452 typedef struct SM501State { 453 /* graphic console status */ 454 QemuConsole *con; 455 456 /* status & internal resources */ 457 uint32_t local_mem_size_index; 458 uint8_t *local_mem; 459 MemoryRegion local_mem_region; 460 MemoryRegion mmio_region; 461 MemoryRegion system_config_region; 462 MemoryRegion i2c_region; 463 MemoryRegion disp_ctrl_region; 464 MemoryRegion twoD_engine_region; 465 uint32_t last_width; 466 uint32_t last_height; 467 bool do_full_update; /* perform a full update next time */ 468 I2CBus *i2c_bus; 469 470 /* mmio registers */ 471 uint32_t system_control; 472 uint32_t misc_control; 473 uint32_t gpio_31_0_control; 474 uint32_t gpio_63_32_control; 475 uint32_t dram_control; 476 uint32_t arbitration_control; 477 uint32_t irq_mask; 478 uint32_t misc_timing; 479 uint32_t power_mode_control; 480 481 uint8_t i2c_byte_count; 482 uint8_t i2c_status; 483 uint8_t i2c_addr; 484 uint8_t i2c_data[16]; 485 486 uint32_t uart0_ier; 487 uint32_t uart0_lcr; 488 uint32_t uart0_mcr; 489 uint32_t uart0_scr; 490 491 uint8_t dc_palette[DC_PALETTE_ENTRIES]; 492 493 uint32_t dc_panel_control; 494 uint32_t dc_panel_panning_control; 495 uint32_t dc_panel_fb_addr; 496 uint32_t dc_panel_fb_offset; 497 uint32_t dc_panel_fb_width; 498 uint32_t dc_panel_fb_height; 499 uint32_t dc_panel_tl_location; 500 uint32_t dc_panel_br_location; 501 uint32_t dc_panel_h_total; 502 uint32_t dc_panel_h_sync; 503 uint32_t dc_panel_v_total; 504 uint32_t dc_panel_v_sync; 505 506 uint32_t dc_panel_hwc_addr; 507 uint32_t dc_panel_hwc_location; 508 uint32_t dc_panel_hwc_color_1_2; 509 uint32_t dc_panel_hwc_color_3; 510 511 uint32_t dc_video_control; 512 513 uint32_t dc_crt_control; 514 uint32_t dc_crt_fb_addr; 515 uint32_t dc_crt_fb_offset; 516 uint32_t dc_crt_h_total; 517 uint32_t dc_crt_h_sync; 518 uint32_t dc_crt_v_total; 519 uint32_t dc_crt_v_sync; 520 521 uint32_t dc_crt_hwc_addr; 522 uint32_t dc_crt_hwc_location; 523 uint32_t dc_crt_hwc_color_1_2; 524 uint32_t dc_crt_hwc_color_3; 525 526 uint32_t twoD_source; 527 uint32_t twoD_destination; 528 uint32_t twoD_dimension; 529 uint32_t twoD_control; 530 uint32_t twoD_pitch; 531 uint32_t twoD_foreground; 532 uint32_t twoD_background; 533 uint32_t twoD_stretch; 534 uint32_t twoD_color_compare; 535 uint32_t twoD_color_compare_mask; 536 uint32_t twoD_mask; 537 uint32_t twoD_clip_tl; 538 uint32_t twoD_clip_br; 539 uint32_t twoD_mono_pattern_low; 540 uint32_t twoD_mono_pattern_high; 541 uint32_t twoD_window_width; 542 uint32_t twoD_source_base; 543 uint32_t twoD_destination_base; 544 uint32_t twoD_alpha; 545 uint32_t twoD_wrap; 546 } SM501State; 547 548 static uint32_t get_local_mem_size_index(uint32_t size) 549 { 550 uint32_t norm_size = 0; 551 int i, index = 0; 552 553 for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { 554 uint32_t new_size = sm501_mem_local_size[i]; 555 if (new_size >= size) { 556 if (norm_size == 0 || norm_size > new_size) { 557 norm_size = new_size; 558 index = i; 559 } 560 } 561 } 562 563 return index; 564 } 565 566 static ram_addr_t get_fb_addr(SM501State *s, int crt) 567 { 568 return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0; 569 } 570 571 static inline int get_width(SM501State *s, int crt) 572 { 573 int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total; 574 return (width & 0x00000FFF) + 1; 575 } 576 577 static inline int get_height(SM501State *s, int crt) 578 { 579 int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total; 580 return (height & 0x00000FFF) + 1; 581 } 582 583 static inline int get_bpp(SM501State *s, int crt) 584 { 585 int bpp = crt ? s->dc_crt_control : s->dc_panel_control; 586 return 1 << (bpp & 3); 587 } 588 589 /** 590 * Check the availability of hardware cursor. 591 * @param crt 0 for PANEL, 1 for CRT. 592 */ 593 static inline int is_hwc_enabled(SM501State *state, int crt) 594 { 595 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; 596 return addr & SM501_HWC_EN; 597 } 598 599 /** 600 * Get the address which holds cursor pattern data. 601 * @param crt 0 for PANEL, 1 for CRT. 602 */ 603 static inline uint8_t *get_hwc_address(SM501State *state, int crt) 604 { 605 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr; 606 return state->local_mem + (addr & 0x03FFFFF0); 607 } 608 609 /** 610 * Get the cursor position in y coordinate. 611 * @param crt 0 for PANEL, 1 for CRT. 612 */ 613 static inline uint32_t get_hwc_y(SM501State *state, int crt) 614 { 615 uint32_t location = crt ? state->dc_crt_hwc_location 616 : state->dc_panel_hwc_location; 617 return (location & 0x07FF0000) >> 16; 618 } 619 620 /** 621 * Get the cursor position in x coordinate. 622 * @param crt 0 for PANEL, 1 for CRT. 623 */ 624 static inline uint32_t get_hwc_x(SM501State *state, int crt) 625 { 626 uint32_t location = crt ? state->dc_crt_hwc_location 627 : state->dc_panel_hwc_location; 628 return location & 0x000007FF; 629 } 630 631 /** 632 * Get the hardware cursor palette. 633 * @param crt 0 for PANEL, 1 for CRT. 634 * @param palette pointer to a [3 * 3] array to store color values in 635 */ 636 static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette) 637 { 638 int i; 639 uint32_t color_reg; 640 uint16_t rgb565; 641 642 for (i = 0; i < 3; i++) { 643 if (i + 1 == 3) { 644 color_reg = crt ? state->dc_crt_hwc_color_3 645 : state->dc_panel_hwc_color_3; 646 } else { 647 color_reg = crt ? state->dc_crt_hwc_color_1_2 648 : state->dc_panel_hwc_color_1_2; 649 } 650 651 if (i + 1 == 2) { 652 rgb565 = (color_reg >> 16) & 0xFFFF; 653 } else { 654 rgb565 = color_reg & 0xFFFF; 655 } 656 palette[i * 3 + 0] = ((rgb565 >> 11) * 527 + 23) >> 6; /* r */ 657 palette[i * 3 + 1] = (((rgb565 >> 5) & 0x3f) * 259 + 33) >> 6; /* g */ 658 palette[i * 3 + 2] = ((rgb565 & 0x1f) * 527 + 23) >> 6; /* b */ 659 } 660 } 661 662 static inline void hwc_invalidate(SM501State *s, int crt) 663 { 664 int w = get_width(s, crt); 665 int h = get_height(s, crt); 666 int bpp = get_bpp(s, crt); 667 int start = get_hwc_y(s, crt); 668 int end = MIN(h, start + SM501_HWC_HEIGHT) + 1; 669 670 start *= w * bpp; 671 end *= w * bpp; 672 673 memory_region_set_dirty(&s->local_mem_region, 674 get_fb_addr(s, crt) + start, end - start); 675 } 676 677 static void sm501_2d_operation(SM501State *s) 678 { 679 int cmd = (s->twoD_control >> 16) & 0x1F; 680 int rtl = s->twoD_control & BIT(27); 681 int format = (s->twoD_stretch >> 20) & 3; 682 int bypp = 1 << format; /* bytes per pixel */ 683 int rop_mode = (s->twoD_control >> 15) & 1; /* 1 for rop2, else rop3 */ 684 /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */ 685 int rop2_source_is_pattern = (s->twoD_control >> 14) & 1; 686 int rop = s->twoD_control & 0xFF; 687 unsigned int dst_x = (s->twoD_destination >> 16) & 0x01FFF; 688 unsigned int dst_y = s->twoD_destination & 0xFFFF; 689 unsigned int width = (s->twoD_dimension >> 16) & 0x1FFF; 690 unsigned int height = s->twoD_dimension & 0xFFFF; 691 uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF; 692 unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF; 693 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; 694 int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt); 695 bool overlap = false; 696 697 if ((s->twoD_stretch >> 16) & 0xF) { 698 qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n"); 699 return; 700 } 701 702 if (s->twoD_source_base & BIT(27) || s->twoD_destination_base & BIT(27)) { 703 qemu_log_mask(LOG_UNIMP, "sm501: only local memory is supported.\n"); 704 return; 705 } 706 707 if (!dst_pitch) { 708 qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero dest pitch.\n"); 709 return; 710 } 711 712 if (!width || !height) { 713 qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero size 2D op.\n"); 714 return; 715 } 716 717 if (rtl) { 718 dst_x -= width - 1; 719 dst_y -= height - 1; 720 } 721 722 if (dst_base >= get_local_mem_size(s) || 723 dst_base + (dst_x + width + (dst_y + height) * dst_pitch) * bypp >= 724 get_local_mem_size(s)) { 725 qemu_log_mask(LOG_GUEST_ERROR, "sm501: 2D op dest is outside vram.\n"); 726 return; 727 } 728 729 switch (cmd) { 730 case 0: /* BitBlt */ 731 { 732 static uint32_t tmp_buf[16384]; 733 unsigned int src_x = (s->twoD_source >> 16) & 0x01FFF; 734 unsigned int src_y = s->twoD_source & 0xFFFF; 735 uint32_t src_base = s->twoD_source_base & 0x03FFFFFF; 736 unsigned int src_pitch = s->twoD_pitch & 0x1FFF; 737 738 if (!src_pitch) { 739 qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero src pitch.\n"); 740 return; 741 } 742 743 if (rtl) { 744 src_x -= width - 1; 745 src_y -= height - 1; 746 } 747 748 if (src_base >= get_local_mem_size(s) || 749 src_base + (src_x + width + (src_y + height) * src_pitch) * bypp >= 750 get_local_mem_size(s)) { 751 qemu_log_mask(LOG_GUEST_ERROR, 752 "sm501: 2D op src is outside vram.\n"); 753 return; 754 } 755 756 if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) { 757 /* Invert dest, is there a way to do this with pixman? */ 758 unsigned int x, y, i; 759 uint8_t *d = s->local_mem + dst_base; 760 761 for (y = 0; y < height; y++) { 762 i = (dst_x + (dst_y + y) * dst_pitch) * bypp; 763 for (x = 0; x < width; x++, i += bypp) { 764 stn_he_p(&d[i], bypp, ~ldn_he_p(&d[i], bypp)); 765 } 766 } 767 } else { 768 /* Do copy src for unimplemented ops, better than unpainted area */ 769 if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) || 770 (!rop_mode && rop != 0xcc)) { 771 qemu_log_mask(LOG_UNIMP, 772 "sm501: rop%d op %x%s not implemented\n", 773 (rop_mode ? 2 : 3), rop, 774 (rop2_source_is_pattern ? 775 " with pattern source" : "")); 776 } 777 /* Ignore no-op blits, some guests seem to do this */ 778 if (src_base == dst_base && src_pitch == dst_pitch && 779 src_x == dst_x && src_y == dst_y) { 780 break; 781 } 782 /* Some clients also do 1 pixel blits, avoid overhead for these */ 783 if (width == 1 && height == 1) { 784 unsigned int si = (src_x + src_y * src_pitch) * bypp; 785 unsigned int di = (dst_x + dst_y * dst_pitch) * bypp; 786 stn_he_p(&s->local_mem[dst_base + di], bypp, 787 ldn_he_p(&s->local_mem[src_base + si], bypp)); 788 break; 789 } 790 /* If reverse blit do simple check for overlaps */ 791 if (rtl && src_base == dst_base && src_pitch == dst_pitch) { 792 overlap = (src_x < dst_x + width && src_x + width > dst_x && 793 src_y < dst_y + height && src_y + height > dst_y); 794 } else if (rtl) { 795 unsigned int sb, se, db, de; 796 sb = src_base + (src_x + src_y * src_pitch) * bypp; 797 se = sb + (width + (height - 1) * src_pitch) * bypp; 798 db = dst_base + (dst_x + dst_y * dst_pitch) * bypp; 799 de = db + (width + (height - 1) * dst_pitch) * bypp; 800 overlap = (db < se && sb < de); 801 } 802 if (overlap) { 803 /* pixman can't do reverse blit: copy via temporary */ 804 int tmp_stride = DIV_ROUND_UP(width * bypp, sizeof(uint32_t)); 805 uint32_t *tmp = tmp_buf; 806 807 if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) { 808 tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height); 809 } 810 pixman_blt((uint32_t *)&s->local_mem[src_base], tmp, 811 src_pitch * bypp / sizeof(uint32_t), 812 tmp_stride, 8 * bypp, 8 * bypp, 813 src_x, src_y, 0, 0, width, height); 814 pixman_blt(tmp, (uint32_t *)&s->local_mem[dst_base], 815 tmp_stride, 816 dst_pitch * bypp / sizeof(uint32_t), 817 8 * bypp, 8 * bypp, 818 0, 0, dst_x, dst_y, width, height); 819 if (tmp != tmp_buf) { 820 g_free(tmp); 821 } 822 } else { 823 pixman_blt((uint32_t *)&s->local_mem[src_base], 824 (uint32_t *)&s->local_mem[dst_base], 825 src_pitch * bypp / sizeof(uint32_t), 826 dst_pitch * bypp / sizeof(uint32_t), 827 8 * bypp, 8 * bypp, 828 src_x, src_y, dst_x, dst_y, width, height); 829 } 830 } 831 break; 832 } 833 case 1: /* Rectangle Fill */ 834 { 835 uint32_t color = s->twoD_foreground; 836 837 if (format == 2) { 838 color = cpu_to_le32(color); 839 } else if (format == 1) { 840 color = cpu_to_le16(color); 841 } 842 843 if (width == 1 && height == 1) { 844 unsigned int i = (dst_x + dst_y * dst_pitch) * bypp; 845 stn_he_p(&s->local_mem[dst_base + i], bypp, color); 846 } else { 847 pixman_fill((uint32_t *)&s->local_mem[dst_base], 848 dst_pitch * bypp / sizeof(uint32_t), 849 8 * bypp, dst_x, dst_y, width, height, color); 850 } 851 break; 852 } 853 default: 854 qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n", 855 cmd); 856 return; 857 } 858 859 if (dst_base >= get_fb_addr(s, crt) && 860 dst_base <= get_fb_addr(s, crt) + fb_len) { 861 int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch + 862 dst_x + width) * bypp); 863 if (dst_len) { 864 memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len); 865 } 866 } 867 } 868 869 static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, 870 unsigned size) 871 { 872 SM501State *s = opaque; 873 uint32_t ret = 0; 874 875 switch (addr) { 876 case SM501_SYSTEM_CONTROL: 877 ret = s->system_control; 878 break; 879 case SM501_MISC_CONTROL: 880 ret = s->misc_control; 881 break; 882 case SM501_GPIO31_0_CONTROL: 883 ret = s->gpio_31_0_control; 884 break; 885 case SM501_GPIO63_32_CONTROL: 886 ret = s->gpio_63_32_control; 887 break; 888 case SM501_DEVICEID: 889 ret = 0x050100A0; 890 break; 891 case SM501_DRAM_CONTROL: 892 ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; 893 break; 894 case SM501_ARBTRTN_CONTROL: 895 ret = s->arbitration_control; 896 break; 897 case SM501_COMMAND_LIST_STATUS: 898 ret = 0x00180002; /* FIFOs are empty, everything idle */ 899 break; 900 case SM501_IRQ_MASK: 901 ret = s->irq_mask; 902 break; 903 case SM501_MISC_TIMING: 904 /* TODO : simulate gate control */ 905 ret = s->misc_timing; 906 break; 907 case SM501_CURRENT_GATE: 908 /* TODO : simulate gate control */ 909 ret = 0x00021807; 910 break; 911 case SM501_CURRENT_CLOCK: 912 ret = 0x2A1A0A09; 913 break; 914 case SM501_POWER_MODE_CONTROL: 915 ret = s->power_mode_control; 916 break; 917 case SM501_ENDIAN_CONTROL: 918 ret = 0; /* Only default little endian mode is supported */ 919 break; 920 921 default: 922 qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" 923 "register read. addr=%" HWADDR_PRIx "\n", addr); 924 } 925 trace_sm501_system_config_read(addr, ret); 926 return ret; 927 } 928 929 static void sm501_system_config_write(void *opaque, hwaddr addr, 930 uint64_t value, unsigned size) 931 { 932 SM501State *s = opaque; 933 934 trace_sm501_system_config_write((uint32_t)addr, (uint32_t)value); 935 switch (addr) { 936 case SM501_SYSTEM_CONTROL: 937 s->system_control &= 0x10DB0000; 938 s->system_control |= value & 0xEF00B8F7; 939 break; 940 case SM501_MISC_CONTROL: 941 s->misc_control &= 0xEF; 942 s->misc_control |= value & 0xFF7FFF10; 943 break; 944 case SM501_GPIO31_0_CONTROL: 945 s->gpio_31_0_control = value; 946 break; 947 case SM501_GPIO63_32_CONTROL: 948 s->gpio_63_32_control = value & 0xFF80FFFF; 949 break; 950 case SM501_DRAM_CONTROL: 951 s->local_mem_size_index = (value >> 13) & 0x7; 952 /* TODO : check validity of size change */ 953 s->dram_control &= 0x80000000; 954 s->dram_control |= value & 0x7FFFFFC3; 955 break; 956 case SM501_ARBTRTN_CONTROL: 957 s->arbitration_control = value & 0x37777777; 958 break; 959 case SM501_IRQ_MASK: 960 s->irq_mask = value & 0xFFDF3F5F; 961 break; 962 case SM501_MISC_TIMING: 963 s->misc_timing = value & 0xF31F1FFF; 964 break; 965 case SM501_POWER_MODE_0_GATE: 966 case SM501_POWER_MODE_1_GATE: 967 case SM501_POWER_MODE_0_CLOCK: 968 case SM501_POWER_MODE_1_CLOCK: 969 /* TODO : simulate gate & clock control */ 970 break; 971 case SM501_POWER_MODE_CONTROL: 972 s->power_mode_control = value & 0x00000003; 973 break; 974 case SM501_ENDIAN_CONTROL: 975 if (value & 0x00000001) { 976 qemu_log_mask(LOG_UNIMP, "sm501: system config big endian mode not" 977 " implemented.\n"); 978 } 979 break; 980 981 default: 982 qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" 983 "register write. addr=%" HWADDR_PRIx 984 ", val=%" PRIx64 "\n", addr, value); 985 } 986 } 987 988 static const MemoryRegionOps sm501_system_config_ops = { 989 .read = sm501_system_config_read, 990 .write = sm501_system_config_write, 991 .valid = { 992 .min_access_size = 4, 993 .max_access_size = 4, 994 }, 995 .endianness = DEVICE_LITTLE_ENDIAN, 996 }; 997 998 static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size) 999 { 1000 SM501State *s = opaque; 1001 uint8_t ret = 0; 1002 1003 switch (addr) { 1004 case SM501_I2C_BYTE_COUNT: 1005 ret = s->i2c_byte_count; 1006 break; 1007 case SM501_I2C_STATUS: 1008 ret = s->i2c_status; 1009 break; 1010 case SM501_I2C_SLAVE_ADDRESS: 1011 ret = s->i2c_addr; 1012 break; 1013 case SM501_I2C_DATA ... SM501_I2C_DATA + 15: 1014 ret = s->i2c_data[addr - SM501_I2C_DATA]; 1015 break; 1016 default: 1017 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read." 1018 " addr=0x%" HWADDR_PRIx "\n", addr); 1019 } 1020 trace_sm501_i2c_read((uint32_t)addr, ret); 1021 return ret; 1022 } 1023 1024 static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value, 1025 unsigned size) 1026 { 1027 SM501State *s = opaque; 1028 1029 trace_sm501_i2c_write((uint32_t)addr, (uint32_t)value); 1030 switch (addr) { 1031 case SM501_I2C_BYTE_COUNT: 1032 s->i2c_byte_count = value & 0xf; 1033 break; 1034 case SM501_I2C_CONTROL: 1035 if (value & SM501_I2C_CONTROL_ENABLE) { 1036 if (value & SM501_I2C_CONTROL_START) { 1037 bool is_recv = s->i2c_addr & 1; 1038 int res = i2c_start_transfer(s->i2c_bus, 1039 s->i2c_addr >> 1, 1040 is_recv); 1041 if (res) { 1042 s->i2c_status |= SM501_I2C_STATUS_ERROR; 1043 } else { 1044 int i; 1045 for (i = 0; i <= s->i2c_byte_count; i++) { 1046 if (is_recv) { 1047 s->i2c_data[i] = i2c_recv(s->i2c_bus); 1048 } else if (i2c_send(s->i2c_bus, s->i2c_data[i]) < 0) { 1049 s->i2c_status |= SM501_I2C_STATUS_ERROR; 1050 return; 1051 } 1052 } 1053 if (i) { 1054 s->i2c_status = SM501_I2C_STATUS_COMPLETE; 1055 } 1056 } 1057 } else { 1058 i2c_end_transfer(s->i2c_bus); 1059 s->i2c_status &= ~SM501_I2C_STATUS_ERROR; 1060 } 1061 } 1062 break; 1063 case SM501_I2C_RESET: 1064 if ((value & SM501_I2C_RESET_ERROR) == 0) { 1065 s->i2c_status &= ~SM501_I2C_STATUS_ERROR; 1066 } 1067 break; 1068 case SM501_I2C_SLAVE_ADDRESS: 1069 s->i2c_addr = value & 0xff; 1070 break; 1071 case SM501_I2C_DATA ... SM501_I2C_DATA + 15: 1072 s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff; 1073 break; 1074 default: 1075 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. " 1076 "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value); 1077 } 1078 } 1079 1080 static const MemoryRegionOps sm501_i2c_ops = { 1081 .read = sm501_i2c_read, 1082 .write = sm501_i2c_write, 1083 .valid = { 1084 .min_access_size = 1, 1085 .max_access_size = 1, 1086 }, 1087 .impl = { 1088 .min_access_size = 1, 1089 .max_access_size = 1, 1090 }, 1091 .endianness = DEVICE_LITTLE_ENDIAN, 1092 }; 1093 1094 static uint32_t sm501_palette_read(void *opaque, hwaddr addr) 1095 { 1096 SM501State *s = opaque; 1097 1098 trace_sm501_palette_read((uint32_t)addr); 1099 1100 /* TODO : consider BYTE/WORD access */ 1101 /* TODO : consider endian */ 1102 1103 assert(range_covers_byte(0, 0x400 * 3, addr)); 1104 return *(uint32_t *)&s->dc_palette[addr]; 1105 } 1106 1107 static void sm501_palette_write(void *opaque, hwaddr addr, 1108 uint32_t value) 1109 { 1110 SM501State *s = opaque; 1111 1112 trace_sm501_palette_write((uint32_t)addr, value); 1113 1114 /* TODO : consider BYTE/WORD access */ 1115 /* TODO : consider endian */ 1116 1117 assert(range_covers_byte(0, 0x400 * 3, addr)); 1118 *(uint32_t *)&s->dc_palette[addr] = value; 1119 s->do_full_update = true; 1120 } 1121 1122 static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, 1123 unsigned size) 1124 { 1125 SM501State *s = opaque; 1126 uint32_t ret = 0; 1127 1128 switch (addr) { 1129 1130 case SM501_DC_PANEL_CONTROL: 1131 ret = s->dc_panel_control; 1132 break; 1133 case SM501_DC_PANEL_PANNING_CONTROL: 1134 ret = s->dc_panel_panning_control; 1135 break; 1136 case SM501_DC_PANEL_COLOR_KEY: 1137 /* Not implemented yet */ 1138 break; 1139 case SM501_DC_PANEL_FB_ADDR: 1140 ret = s->dc_panel_fb_addr; 1141 break; 1142 case SM501_DC_PANEL_FB_OFFSET: 1143 ret = s->dc_panel_fb_offset; 1144 break; 1145 case SM501_DC_PANEL_FB_WIDTH: 1146 ret = s->dc_panel_fb_width; 1147 break; 1148 case SM501_DC_PANEL_FB_HEIGHT: 1149 ret = s->dc_panel_fb_height; 1150 break; 1151 case SM501_DC_PANEL_TL_LOC: 1152 ret = s->dc_panel_tl_location; 1153 break; 1154 case SM501_DC_PANEL_BR_LOC: 1155 ret = s->dc_panel_br_location; 1156 break; 1157 1158 case SM501_DC_PANEL_H_TOT: 1159 ret = s->dc_panel_h_total; 1160 break; 1161 case SM501_DC_PANEL_H_SYNC: 1162 ret = s->dc_panel_h_sync; 1163 break; 1164 case SM501_DC_PANEL_V_TOT: 1165 ret = s->dc_panel_v_total; 1166 break; 1167 case SM501_DC_PANEL_V_SYNC: 1168 ret = s->dc_panel_v_sync; 1169 break; 1170 1171 case SM501_DC_PANEL_HWC_ADDR: 1172 ret = s->dc_panel_hwc_addr; 1173 break; 1174 case SM501_DC_PANEL_HWC_LOC: 1175 ret = s->dc_panel_hwc_location; 1176 break; 1177 case SM501_DC_PANEL_HWC_COLOR_1_2: 1178 ret = s->dc_panel_hwc_color_1_2; 1179 break; 1180 case SM501_DC_PANEL_HWC_COLOR_3: 1181 ret = s->dc_panel_hwc_color_3; 1182 break; 1183 1184 case SM501_DC_VIDEO_CONTROL: 1185 ret = s->dc_video_control; 1186 break; 1187 1188 case SM501_DC_CRT_CONTROL: 1189 ret = s->dc_crt_control; 1190 break; 1191 case SM501_DC_CRT_FB_ADDR: 1192 ret = s->dc_crt_fb_addr; 1193 break; 1194 case SM501_DC_CRT_FB_OFFSET: 1195 ret = s->dc_crt_fb_offset; 1196 break; 1197 case SM501_DC_CRT_H_TOT: 1198 ret = s->dc_crt_h_total; 1199 break; 1200 case SM501_DC_CRT_H_SYNC: 1201 ret = s->dc_crt_h_sync; 1202 break; 1203 case SM501_DC_CRT_V_TOT: 1204 ret = s->dc_crt_v_total; 1205 break; 1206 case SM501_DC_CRT_V_SYNC: 1207 ret = s->dc_crt_v_sync; 1208 break; 1209 1210 case SM501_DC_CRT_HWC_ADDR: 1211 ret = s->dc_crt_hwc_addr; 1212 break; 1213 case SM501_DC_CRT_HWC_LOC: 1214 ret = s->dc_crt_hwc_location; 1215 break; 1216 case SM501_DC_CRT_HWC_COLOR_1_2: 1217 ret = s->dc_crt_hwc_color_1_2; 1218 break; 1219 case SM501_DC_CRT_HWC_COLOR_3: 1220 ret = s->dc_crt_hwc_color_3; 1221 break; 1222 1223 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: 1224 ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); 1225 break; 1226 1227 default: 1228 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " 1229 "read. addr=%" HWADDR_PRIx "\n", addr); 1230 } 1231 trace_sm501_disp_ctrl_read((uint32_t)addr, ret); 1232 return ret; 1233 } 1234 1235 static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, 1236 uint64_t value, unsigned size) 1237 { 1238 SM501State *s = opaque; 1239 1240 trace_sm501_disp_ctrl_write((uint32_t)addr, (uint32_t)value); 1241 switch (addr) { 1242 case SM501_DC_PANEL_CONTROL: 1243 s->dc_panel_control = value & 0x0FFF73FF; 1244 break; 1245 case SM501_DC_PANEL_PANNING_CONTROL: 1246 s->dc_panel_panning_control = value & 0xFF3FFF3F; 1247 break; 1248 case SM501_DC_PANEL_COLOR_KEY: 1249 /* Not implemented yet */ 1250 break; 1251 case SM501_DC_PANEL_FB_ADDR: 1252 s->dc_panel_fb_addr = value & 0x8FFFFFF0; 1253 if (value & 0x8000000) { 1254 qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n"); 1255 } 1256 s->do_full_update = true; 1257 break; 1258 case SM501_DC_PANEL_FB_OFFSET: 1259 s->dc_panel_fb_offset = value & 0x3FF03FF0; 1260 break; 1261 case SM501_DC_PANEL_FB_WIDTH: 1262 s->dc_panel_fb_width = value & 0x0FFF0FFF; 1263 break; 1264 case SM501_DC_PANEL_FB_HEIGHT: 1265 s->dc_panel_fb_height = value & 0x0FFF0FFF; 1266 break; 1267 case SM501_DC_PANEL_TL_LOC: 1268 s->dc_panel_tl_location = value & 0x07FF07FF; 1269 break; 1270 case SM501_DC_PANEL_BR_LOC: 1271 s->dc_panel_br_location = value & 0x07FF07FF; 1272 break; 1273 1274 case SM501_DC_PANEL_H_TOT: 1275 s->dc_panel_h_total = value & 0x0FFF0FFF; 1276 break; 1277 case SM501_DC_PANEL_H_SYNC: 1278 s->dc_panel_h_sync = value & 0x00FF0FFF; 1279 break; 1280 case SM501_DC_PANEL_V_TOT: 1281 s->dc_panel_v_total = value & 0x0FFF0FFF; 1282 break; 1283 case SM501_DC_PANEL_V_SYNC: 1284 s->dc_panel_v_sync = value & 0x003F0FFF; 1285 break; 1286 1287 case SM501_DC_PANEL_HWC_ADDR: 1288 value &= 0x8FFFFFF0; 1289 if (value != s->dc_panel_hwc_addr) { 1290 hwc_invalidate(s, 0); 1291 s->dc_panel_hwc_addr = value; 1292 } 1293 break; 1294 case SM501_DC_PANEL_HWC_LOC: 1295 value &= 0x0FFF0FFF; 1296 if (value != s->dc_panel_hwc_location) { 1297 hwc_invalidate(s, 0); 1298 s->dc_panel_hwc_location = value; 1299 } 1300 break; 1301 case SM501_DC_PANEL_HWC_COLOR_1_2: 1302 s->dc_panel_hwc_color_1_2 = value; 1303 break; 1304 case SM501_DC_PANEL_HWC_COLOR_3: 1305 s->dc_panel_hwc_color_3 = value & 0x0000FFFF; 1306 break; 1307 1308 case SM501_DC_VIDEO_CONTROL: 1309 s->dc_video_control = value & 0x00037FFF; 1310 break; 1311 1312 case SM501_DC_CRT_CONTROL: 1313 s->dc_crt_control = value & 0x0003FFFF; 1314 break; 1315 case SM501_DC_CRT_FB_ADDR: 1316 s->dc_crt_fb_addr = value & 0x8FFFFFF0; 1317 if (value & 0x8000000) { 1318 qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n"); 1319 } 1320 s->do_full_update = true; 1321 break; 1322 case SM501_DC_CRT_FB_OFFSET: 1323 s->dc_crt_fb_offset = value & 0x3FF03FF0; 1324 break; 1325 case SM501_DC_CRT_H_TOT: 1326 s->dc_crt_h_total = value & 0x0FFF0FFF; 1327 break; 1328 case SM501_DC_CRT_H_SYNC: 1329 s->dc_crt_h_sync = value & 0x00FF0FFF; 1330 break; 1331 case SM501_DC_CRT_V_TOT: 1332 s->dc_crt_v_total = value & 0x0FFF0FFF; 1333 break; 1334 case SM501_DC_CRT_V_SYNC: 1335 s->dc_crt_v_sync = value & 0x003F0FFF; 1336 break; 1337 1338 case SM501_DC_CRT_HWC_ADDR: 1339 value &= 0x8FFFFFF0; 1340 if (value != s->dc_crt_hwc_addr) { 1341 hwc_invalidate(s, 1); 1342 s->dc_crt_hwc_addr = value; 1343 } 1344 break; 1345 case SM501_DC_CRT_HWC_LOC: 1346 value &= 0x0FFF0FFF; 1347 if (value != s->dc_crt_hwc_location) { 1348 hwc_invalidate(s, 1); 1349 s->dc_crt_hwc_location = value; 1350 } 1351 break; 1352 case SM501_DC_CRT_HWC_COLOR_1_2: 1353 s->dc_crt_hwc_color_1_2 = value; 1354 break; 1355 case SM501_DC_CRT_HWC_COLOR_3: 1356 s->dc_crt_hwc_color_3 = value & 0x0000FFFF; 1357 break; 1358 1359 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: 1360 sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); 1361 break; 1362 1363 default: 1364 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " 1365 "write. addr=%" HWADDR_PRIx 1366 ", val=%" PRIx64 "\n", addr, value); 1367 } 1368 } 1369 1370 static const MemoryRegionOps sm501_disp_ctrl_ops = { 1371 .read = sm501_disp_ctrl_read, 1372 .write = sm501_disp_ctrl_write, 1373 .valid = { 1374 .min_access_size = 4, 1375 .max_access_size = 4, 1376 }, 1377 .endianness = DEVICE_LITTLE_ENDIAN, 1378 }; 1379 1380 static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, 1381 unsigned size) 1382 { 1383 SM501State *s = opaque; 1384 uint32_t ret = 0; 1385 1386 switch (addr) { 1387 case SM501_2D_SOURCE: 1388 ret = s->twoD_source; 1389 break; 1390 case SM501_2D_DESTINATION: 1391 ret = s->twoD_destination; 1392 break; 1393 case SM501_2D_DIMENSION: 1394 ret = s->twoD_dimension; 1395 break; 1396 case SM501_2D_CONTROL: 1397 ret = s->twoD_control; 1398 break; 1399 case SM501_2D_PITCH: 1400 ret = s->twoD_pitch; 1401 break; 1402 case SM501_2D_FOREGROUND: 1403 ret = s->twoD_foreground; 1404 break; 1405 case SM501_2D_BACKGROUND: 1406 ret = s->twoD_background; 1407 break; 1408 case SM501_2D_STRETCH: 1409 ret = s->twoD_stretch; 1410 break; 1411 case SM501_2D_COLOR_COMPARE: 1412 ret = s->twoD_color_compare; 1413 break; 1414 case SM501_2D_COLOR_COMPARE_MASK: 1415 ret = s->twoD_color_compare_mask; 1416 break; 1417 case SM501_2D_MASK: 1418 ret = s->twoD_mask; 1419 break; 1420 case SM501_2D_CLIP_TL: 1421 ret = s->twoD_clip_tl; 1422 break; 1423 case SM501_2D_CLIP_BR: 1424 ret = s->twoD_clip_br; 1425 break; 1426 case SM501_2D_MONO_PATTERN_LOW: 1427 ret = s->twoD_mono_pattern_low; 1428 break; 1429 case SM501_2D_MONO_PATTERN_HIGH: 1430 ret = s->twoD_mono_pattern_high; 1431 break; 1432 case SM501_2D_WINDOW_WIDTH: 1433 ret = s->twoD_window_width; 1434 break; 1435 case SM501_2D_SOURCE_BASE: 1436 ret = s->twoD_source_base; 1437 break; 1438 case SM501_2D_DESTINATION_BASE: 1439 ret = s->twoD_destination_base; 1440 break; 1441 case SM501_2D_ALPHA: 1442 ret = s->twoD_alpha; 1443 break; 1444 case SM501_2D_WRAP: 1445 ret = s->twoD_wrap; 1446 break; 1447 case SM501_2D_STATUS: 1448 ret = 0; /* Should return interrupt status */ 1449 break; 1450 default: 1451 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " 1452 "read. addr=%" HWADDR_PRIx "\n", addr); 1453 } 1454 trace_sm501_2d_engine_read((uint32_t)addr, ret); 1455 return ret; 1456 } 1457 1458 static void sm501_2d_engine_write(void *opaque, hwaddr addr, 1459 uint64_t value, unsigned size) 1460 { 1461 SM501State *s = opaque; 1462 1463 trace_sm501_2d_engine_write((uint32_t)addr, (uint32_t)value); 1464 switch (addr) { 1465 case SM501_2D_SOURCE: 1466 s->twoD_source = value; 1467 break; 1468 case SM501_2D_DESTINATION: 1469 s->twoD_destination = value; 1470 break; 1471 case SM501_2D_DIMENSION: 1472 s->twoD_dimension = value; 1473 break; 1474 case SM501_2D_CONTROL: 1475 s->twoD_control = value; 1476 1477 /* do 2d operation if start flag is set. */ 1478 if (value & 0x80000000) { 1479 sm501_2d_operation(s); 1480 s->twoD_control &= ~0x80000000; /* start flag down */ 1481 } 1482 1483 break; 1484 case SM501_2D_PITCH: 1485 s->twoD_pitch = value; 1486 break; 1487 case SM501_2D_FOREGROUND: 1488 s->twoD_foreground = value; 1489 break; 1490 case SM501_2D_BACKGROUND: 1491 s->twoD_background = value; 1492 break; 1493 case SM501_2D_STRETCH: 1494 if (((value >> 20) & 3) == 3) { 1495 value &= ~BIT(20); 1496 } 1497 s->twoD_stretch = value; 1498 break; 1499 case SM501_2D_COLOR_COMPARE: 1500 s->twoD_color_compare = value; 1501 break; 1502 case SM501_2D_COLOR_COMPARE_MASK: 1503 s->twoD_color_compare_mask = value; 1504 break; 1505 case SM501_2D_MASK: 1506 s->twoD_mask = value; 1507 break; 1508 case SM501_2D_CLIP_TL: 1509 s->twoD_clip_tl = value; 1510 break; 1511 case SM501_2D_CLIP_BR: 1512 s->twoD_clip_br = value; 1513 break; 1514 case SM501_2D_MONO_PATTERN_LOW: 1515 s->twoD_mono_pattern_low = value; 1516 break; 1517 case SM501_2D_MONO_PATTERN_HIGH: 1518 s->twoD_mono_pattern_high = value; 1519 break; 1520 case SM501_2D_WINDOW_WIDTH: 1521 s->twoD_window_width = value; 1522 break; 1523 case SM501_2D_SOURCE_BASE: 1524 s->twoD_source_base = value; 1525 break; 1526 case SM501_2D_DESTINATION_BASE: 1527 s->twoD_destination_base = value; 1528 break; 1529 case SM501_2D_ALPHA: 1530 s->twoD_alpha = value; 1531 break; 1532 case SM501_2D_WRAP: 1533 s->twoD_wrap = value; 1534 break; 1535 case SM501_2D_STATUS: 1536 /* ignored, writing 0 should clear interrupt status */ 1537 break; 1538 default: 1539 qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2d engine register " 1540 "write. addr=%" HWADDR_PRIx 1541 ", val=%" PRIx64 "\n", addr, value); 1542 } 1543 } 1544 1545 static const MemoryRegionOps sm501_2d_engine_ops = { 1546 .read = sm501_2d_engine_read, 1547 .write = sm501_2d_engine_write, 1548 .valid = { 1549 .min_access_size = 4, 1550 .max_access_size = 4, 1551 }, 1552 .endianness = DEVICE_LITTLE_ENDIAN, 1553 }; 1554 1555 /* draw line functions for all console modes */ 1556 1557 typedef void draw_line_func(uint8_t *d, const uint8_t *s, 1558 int width, const uint32_t *pal); 1559 1560 typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s, 1561 int width, const uint8_t *palette, 1562 int c_x, int c_y); 1563 1564 static void draw_line8_32(uint8_t *d, const uint8_t *s, int width, 1565 const uint32_t *pal) 1566 { 1567 uint8_t v, r, g, b; 1568 do { 1569 v = ldub_p(s); 1570 r = (pal[v] >> 16) & 0xff; 1571 g = (pal[v] >> 8) & 0xff; 1572 b = (pal[v] >> 0) & 0xff; 1573 *(uint32_t *)d = rgb_to_pixel32(r, g, b); 1574 s++; 1575 d += 4; 1576 } while (--width != 0); 1577 } 1578 1579 static void draw_line16_32(uint8_t *d, const uint8_t *s, int width, 1580 const uint32_t *pal) 1581 { 1582 uint16_t rgb565; 1583 uint8_t r, g, b; 1584 1585 do { 1586 rgb565 = lduw_le_p(s); 1587 r = (rgb565 >> 8) & 0xf8; 1588 g = (rgb565 >> 3) & 0xfc; 1589 b = (rgb565 << 3) & 0xf8; 1590 *(uint32_t *)d = rgb_to_pixel32(r, g, b); 1591 s += 2; 1592 d += 4; 1593 } while (--width != 0); 1594 } 1595 1596 static void draw_line32_32(uint8_t *d, const uint8_t *s, int width, 1597 const uint32_t *pal) 1598 { 1599 uint8_t r, g, b; 1600 1601 do { 1602 r = s[2]; 1603 g = s[1]; 1604 b = s[0]; 1605 *(uint32_t *)d = rgb_to_pixel32(r, g, b); 1606 s += 4; 1607 d += 4; 1608 } while (--width != 0); 1609 } 1610 1611 /** 1612 * Draw hardware cursor image on the given line. 1613 */ 1614 static void draw_hwc_line_32(uint8_t *d, const uint8_t *s, int width, 1615 const uint8_t *palette, int c_x, int c_y) 1616 { 1617 int i; 1618 uint8_t r, g, b, v, bitset = 0; 1619 1620 /* get cursor position */ 1621 assert(0 <= c_y && c_y < SM501_HWC_HEIGHT); 1622 s += SM501_HWC_WIDTH * c_y / 4; /* 4 pixels per byte */ 1623 d += c_x * 4; 1624 1625 for (i = 0; i < SM501_HWC_WIDTH && c_x + i < width; i++) { 1626 /* get pixel value */ 1627 if (i % 4 == 0) { 1628 bitset = ldub_p(s); 1629 s++; 1630 } 1631 v = bitset & 3; 1632 bitset >>= 2; 1633 1634 /* write pixel */ 1635 if (v) { 1636 v--; 1637 r = palette[v * 3 + 0]; 1638 g = palette[v * 3 + 1]; 1639 b = palette[v * 3 + 2]; 1640 *(uint32_t *)d = rgb_to_pixel32(r, g, b); 1641 } 1642 d += 4; 1643 } 1644 } 1645 1646 static void sm501_update_display(void *opaque) 1647 { 1648 SM501State *s = opaque; 1649 DisplaySurface *surface = qemu_console_surface(s->con); 1650 DirtyBitmapSnapshot *snap; 1651 int y, c_x = 0, c_y = 0; 1652 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; 1653 int width = get_width(s, crt); 1654 int height = get_height(s, crt); 1655 int src_bpp = get_bpp(s, crt); 1656 int dst_bpp = surface_bytes_per_pixel(surface); 1657 draw_line_func *draw_line = NULL; 1658 draw_hwc_line_func *draw_hwc_line = NULL; 1659 int full_update = 0; 1660 int y_start = -1; 1661 ram_addr_t offset; 1662 uint32_t *palette; 1663 uint8_t hwc_palette[3 * 3]; 1664 uint8_t *hwc_src = NULL; 1665 1666 assert(dst_bpp == 4); /* Output is always 32-bit RGB */ 1667 1668 if (!((crt ? s->dc_crt_control : s->dc_panel_control) 1669 & SM501_DC_CRT_CONTROL_ENABLE)) { 1670 return; 1671 } 1672 1673 palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE - 1674 SM501_DC_PANEL_PALETTE] 1675 : &s->dc_palette[0]); 1676 1677 /* choose draw_line function */ 1678 switch (src_bpp) { 1679 case 1: 1680 draw_line = draw_line8_32; 1681 break; 1682 case 2: 1683 draw_line = draw_line16_32; 1684 break; 1685 case 4: 1686 draw_line = draw_line32_32; 1687 break; 1688 default: 1689 qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display" 1690 "invalid control register value.\n"); 1691 return; 1692 } 1693 1694 /* set up to draw hardware cursor */ 1695 if (is_hwc_enabled(s, crt)) { 1696 /* choose cursor draw line function */ 1697 draw_hwc_line = draw_hwc_line_32; 1698 hwc_src = get_hwc_address(s, crt); 1699 c_x = get_hwc_x(s, crt); 1700 c_y = get_hwc_y(s, crt); 1701 get_hwc_palette(s, crt, hwc_palette); 1702 } 1703 1704 /* adjust console size */ 1705 if (s->last_width != width || s->last_height != height) { 1706 qemu_console_resize(s->con, width, height); 1707 surface = qemu_console_surface(s->con); 1708 s->last_width = width; 1709 s->last_height = height; 1710 full_update = 1; 1711 } 1712 1713 /* someone else requested a full update */ 1714 if (s->do_full_update) { 1715 s->do_full_update = false; 1716 full_update = 1; 1717 } 1718 1719 /* draw each line according to conditions */ 1720 offset = get_fb_addr(s, crt); 1721 snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region, 1722 offset, width * height * src_bpp, DIRTY_MEMORY_VGA); 1723 for (y = 0; y < height; y++, offset += width * src_bpp) { 1724 int update, update_hwc; 1725 1726 /* check if hardware cursor is enabled and we're within its range */ 1727 update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT; 1728 update = full_update || update_hwc; 1729 /* check dirty flags for each line */ 1730 update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap, 1731 offset, width * src_bpp); 1732 1733 /* draw line and change status */ 1734 if (update) { 1735 uint8_t *d = surface_data(surface); 1736 d += y * width * dst_bpp; 1737 1738 /* draw graphics layer */ 1739 draw_line(d, s->local_mem + offset, width, palette); 1740 1741 /* draw hardware cursor */ 1742 if (update_hwc) { 1743 draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y); 1744 } 1745 1746 if (y_start < 0) { 1747 y_start = y; 1748 } 1749 } else { 1750 if (y_start >= 0) { 1751 /* flush to display */ 1752 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 1753 y_start = -1; 1754 } 1755 } 1756 } 1757 g_free(snap); 1758 1759 /* complete flush to display */ 1760 if (y_start >= 0) { 1761 dpy_gfx_update(s->con, 0, y_start, width, y - y_start); 1762 } 1763 } 1764 1765 static const GraphicHwOps sm501_ops = { 1766 .gfx_update = sm501_update_display, 1767 }; 1768 1769 static void sm501_reset(SM501State *s) 1770 { 1771 s->system_control = 0x00100000; /* 2D engine FIFO empty */ 1772 /* 1773 * Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed 1774 * to be determined at reset by GPIO lines which set config bits. 1775 * We hardwire them: 1776 * SH = 0 : Hitachi Ready Polarity == Active Low 1777 * CDR = 0 : do not reset clock divider 1778 * TEST = 0 : Normal mode (not testing the silicon) 1779 * BUS = 0 : Hitachi SH3/SH4 1780 */ 1781 s->misc_control = SM501_MISC_DAC_POWER; 1782 s->gpio_31_0_control = 0; 1783 s->gpio_63_32_control = 0; 1784 s->dram_control = 0; 1785 s->arbitration_control = 0x05146732; 1786 s->irq_mask = 0; 1787 s->misc_timing = 0; 1788 s->power_mode_control = 0; 1789 s->i2c_byte_count = 0; 1790 s->i2c_status = 0; 1791 s->i2c_addr = 0; 1792 memset(s->i2c_data, 0, 16); 1793 s->dc_panel_control = 0x00010000; /* FIFO level 3 */ 1794 s->dc_video_control = 0; 1795 s->dc_crt_control = 0x00010000; 1796 s->twoD_source = 0; 1797 s->twoD_destination = 0; 1798 s->twoD_dimension = 0; 1799 s->twoD_control = 0; 1800 s->twoD_pitch = 0; 1801 s->twoD_foreground = 0; 1802 s->twoD_background = 0; 1803 s->twoD_stretch = 0; 1804 s->twoD_color_compare = 0; 1805 s->twoD_color_compare_mask = 0; 1806 s->twoD_mask = 0; 1807 s->twoD_clip_tl = 0; 1808 s->twoD_clip_br = 0; 1809 s->twoD_mono_pattern_low = 0; 1810 s->twoD_mono_pattern_high = 0; 1811 s->twoD_window_width = 0; 1812 s->twoD_source_base = 0; 1813 s->twoD_destination_base = 0; 1814 s->twoD_alpha = 0; 1815 s->twoD_wrap = 0; 1816 } 1817 1818 static void sm501_init(SM501State *s, DeviceState *dev, 1819 uint32_t local_mem_bytes) 1820 { 1821 s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); 1822 1823 /* local memory */ 1824 memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local", 1825 get_local_mem_size(s), &error_fatal); 1826 memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); 1827 s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); 1828 1829 /* i2c */ 1830 s->i2c_bus = i2c_init_bus(dev, "sm501.i2c"); 1831 /* ddc */ 1832 I2CDDCState *ddc = I2CDDC(qdev_new(TYPE_I2CDDC)); 1833 i2c_slave_set_address(I2C_SLAVE(ddc), 0x50); 1834 qdev_realize_and_unref(DEVICE(ddc), BUS(s->i2c_bus), &error_abort); 1835 1836 /* mmio */ 1837 memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE); 1838 memory_region_init_io(&s->system_config_region, OBJECT(dev), 1839 &sm501_system_config_ops, s, 1840 "sm501-system-config", 0x6c); 1841 memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG, 1842 &s->system_config_region); 1843 memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s, 1844 "sm501-i2c", 0x14); 1845 memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region); 1846 memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev), 1847 &sm501_disp_ctrl_ops, s, 1848 "sm501-disp-ctrl", 0x1000); 1849 memory_region_add_subregion(&s->mmio_region, SM501_DC, 1850 &s->disp_ctrl_region); 1851 memory_region_init_io(&s->twoD_engine_region, OBJECT(dev), 1852 &sm501_2d_engine_ops, s, 1853 "sm501-2d-engine", 0x54); 1854 memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE, 1855 &s->twoD_engine_region); 1856 1857 /* create qemu graphic console */ 1858 s->con = graphic_console_init(dev, 0, &sm501_ops, s); 1859 } 1860 1861 static const VMStateDescription vmstate_sm501_state = { 1862 .name = "sm501-state", 1863 .version_id = 1, 1864 .minimum_version_id = 1, 1865 .fields = (VMStateField[]) { 1866 VMSTATE_UINT32(local_mem_size_index, SM501State), 1867 VMSTATE_UINT32(system_control, SM501State), 1868 VMSTATE_UINT32(misc_control, SM501State), 1869 VMSTATE_UINT32(gpio_31_0_control, SM501State), 1870 VMSTATE_UINT32(gpio_63_32_control, SM501State), 1871 VMSTATE_UINT32(dram_control, SM501State), 1872 VMSTATE_UINT32(arbitration_control, SM501State), 1873 VMSTATE_UINT32(irq_mask, SM501State), 1874 VMSTATE_UINT32(misc_timing, SM501State), 1875 VMSTATE_UINT32(power_mode_control, SM501State), 1876 VMSTATE_UINT32(uart0_ier, SM501State), 1877 VMSTATE_UINT32(uart0_lcr, SM501State), 1878 VMSTATE_UINT32(uart0_mcr, SM501State), 1879 VMSTATE_UINT32(uart0_scr, SM501State), 1880 VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES), 1881 VMSTATE_UINT32(dc_panel_control, SM501State), 1882 VMSTATE_UINT32(dc_panel_panning_control, SM501State), 1883 VMSTATE_UINT32(dc_panel_fb_addr, SM501State), 1884 VMSTATE_UINT32(dc_panel_fb_offset, SM501State), 1885 VMSTATE_UINT32(dc_panel_fb_width, SM501State), 1886 VMSTATE_UINT32(dc_panel_fb_height, SM501State), 1887 VMSTATE_UINT32(dc_panel_tl_location, SM501State), 1888 VMSTATE_UINT32(dc_panel_br_location, SM501State), 1889 VMSTATE_UINT32(dc_panel_h_total, SM501State), 1890 VMSTATE_UINT32(dc_panel_h_sync, SM501State), 1891 VMSTATE_UINT32(dc_panel_v_total, SM501State), 1892 VMSTATE_UINT32(dc_panel_v_sync, SM501State), 1893 VMSTATE_UINT32(dc_panel_hwc_addr, SM501State), 1894 VMSTATE_UINT32(dc_panel_hwc_location, SM501State), 1895 VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State), 1896 VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State), 1897 VMSTATE_UINT32(dc_video_control, SM501State), 1898 VMSTATE_UINT32(dc_crt_control, SM501State), 1899 VMSTATE_UINT32(dc_crt_fb_addr, SM501State), 1900 VMSTATE_UINT32(dc_crt_fb_offset, SM501State), 1901 VMSTATE_UINT32(dc_crt_h_total, SM501State), 1902 VMSTATE_UINT32(dc_crt_h_sync, SM501State), 1903 VMSTATE_UINT32(dc_crt_v_total, SM501State), 1904 VMSTATE_UINT32(dc_crt_v_sync, SM501State), 1905 VMSTATE_UINT32(dc_crt_hwc_addr, SM501State), 1906 VMSTATE_UINT32(dc_crt_hwc_location, SM501State), 1907 VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State), 1908 VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State), 1909 VMSTATE_UINT32(twoD_source, SM501State), 1910 VMSTATE_UINT32(twoD_destination, SM501State), 1911 VMSTATE_UINT32(twoD_dimension, SM501State), 1912 VMSTATE_UINT32(twoD_control, SM501State), 1913 VMSTATE_UINT32(twoD_pitch, SM501State), 1914 VMSTATE_UINT32(twoD_foreground, SM501State), 1915 VMSTATE_UINT32(twoD_background, SM501State), 1916 VMSTATE_UINT32(twoD_stretch, SM501State), 1917 VMSTATE_UINT32(twoD_color_compare, SM501State), 1918 VMSTATE_UINT32(twoD_color_compare_mask, SM501State), 1919 VMSTATE_UINT32(twoD_mask, SM501State), 1920 VMSTATE_UINT32(twoD_clip_tl, SM501State), 1921 VMSTATE_UINT32(twoD_clip_br, SM501State), 1922 VMSTATE_UINT32(twoD_mono_pattern_low, SM501State), 1923 VMSTATE_UINT32(twoD_mono_pattern_high, SM501State), 1924 VMSTATE_UINT32(twoD_window_width, SM501State), 1925 VMSTATE_UINT32(twoD_source_base, SM501State), 1926 VMSTATE_UINT32(twoD_destination_base, SM501State), 1927 VMSTATE_UINT32(twoD_alpha, SM501State), 1928 VMSTATE_UINT32(twoD_wrap, SM501State), 1929 /* Added in version 2 */ 1930 VMSTATE_UINT8(i2c_byte_count, SM501State), 1931 VMSTATE_UINT8(i2c_status, SM501State), 1932 VMSTATE_UINT8(i2c_addr, SM501State), 1933 VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16), 1934 VMSTATE_END_OF_LIST() 1935 } 1936 }; 1937 1938 #define TYPE_SYSBUS_SM501 "sysbus-sm501" 1939 OBJECT_DECLARE_SIMPLE_TYPE(SM501SysBusState, SYSBUS_SM501) 1940 1941 struct SM501SysBusState { 1942 /*< private >*/ 1943 SysBusDevice parent_obj; 1944 /*< public >*/ 1945 SM501State state; 1946 uint32_t vram_size; 1947 SerialMM serial; 1948 OHCISysBusState ohci; 1949 }; 1950 1951 static void sm501_realize_sysbus(DeviceState *dev, Error **errp) 1952 { 1953 SM501SysBusState *s = SYSBUS_SM501(dev); 1954 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1955 MemoryRegion *mr; 1956 1957 sm501_init(&s->state, dev, s->vram_size); 1958 if (get_local_mem_size(&s->state) != s->vram_size) { 1959 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, 1960 get_local_mem_size(&s->state)); 1961 return; 1962 } 1963 sysbus_init_mmio(sbd, &s->state.local_mem_region); 1964 sysbus_init_mmio(sbd, &s->state.mmio_region); 1965 1966 /* bridge to usb host emulation module */ 1967 sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->ohci), &error_fatal); 1968 memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, 1969 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ohci), 0)); 1970 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->ohci)); 1971 1972 /* bridge to serial emulation module */ 1973 sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal); 1974 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0); 1975 memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr); 1976 /* TODO : chain irq to IRL */ 1977 } 1978 1979 static Property sm501_sysbus_properties[] = { 1980 DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), 1981 DEFINE_PROP_END_OF_LIST(), 1982 }; 1983 1984 static void sm501_reset_sysbus(DeviceState *dev) 1985 { 1986 SM501SysBusState *s = SYSBUS_SM501(dev); 1987 sm501_reset(&s->state); 1988 } 1989 1990 static const VMStateDescription vmstate_sm501_sysbus = { 1991 .name = TYPE_SYSBUS_SM501, 1992 .version_id = 2, 1993 .minimum_version_id = 2, 1994 .fields = (VMStateField[]) { 1995 VMSTATE_STRUCT(state, SM501SysBusState, 1, 1996 vmstate_sm501_state, SM501State), 1997 VMSTATE_END_OF_LIST() 1998 } 1999 }; 2000 2001 static void sm501_sysbus_class_init(ObjectClass *klass, void *data) 2002 { 2003 DeviceClass *dc = DEVICE_CLASS(klass); 2004 2005 dc->realize = sm501_realize_sysbus; 2006 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2007 dc->desc = "SM501 Multimedia Companion"; 2008 device_class_set_props(dc, sm501_sysbus_properties); 2009 dc->reset = sm501_reset_sysbus; 2010 dc->vmsd = &vmstate_sm501_sysbus; 2011 } 2012 2013 static void sm501_sysbus_init(Object *o) 2014 { 2015 SM501SysBusState *sm501 = SYSBUS_SM501(o); 2016 OHCISysBusState *ohci = &sm501->ohci; 2017 SerialMM *smm = &sm501->serial; 2018 2019 object_initialize_child(o, "ohci", ohci, TYPE_SYSBUS_OHCI); 2020 object_property_add_alias(o, "dma-offset", OBJECT(ohci), "dma-offset"); 2021 qdev_prop_set_uint32(DEVICE(ohci), "num-ports", 2); 2022 2023 object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM); 2024 qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2); 2025 qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); 2026 qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); 2027 2028 object_property_add_alias(o, "chardev", OBJECT(smm), "chardev"); 2029 } 2030 2031 static const TypeInfo sm501_sysbus_info = { 2032 .name = TYPE_SYSBUS_SM501, 2033 .parent = TYPE_SYS_BUS_DEVICE, 2034 .instance_size = sizeof(SM501SysBusState), 2035 .class_init = sm501_sysbus_class_init, 2036 .instance_init = sm501_sysbus_init, 2037 }; 2038 2039 #define TYPE_PCI_SM501 "sm501" 2040 OBJECT_DECLARE_SIMPLE_TYPE(SM501PCIState, PCI_SM501) 2041 2042 struct SM501PCIState { 2043 /*< private >*/ 2044 PCIDevice parent_obj; 2045 /*< public >*/ 2046 SM501State state; 2047 uint32_t vram_size; 2048 }; 2049 2050 static void sm501_realize_pci(PCIDevice *dev, Error **errp) 2051 { 2052 SM501PCIState *s = PCI_SM501(dev); 2053 2054 sm501_init(&s->state, DEVICE(dev), s->vram_size); 2055 if (get_local_mem_size(&s->state) != s->vram_size) { 2056 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, 2057 get_local_mem_size(&s->state)); 2058 return; 2059 } 2060 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, 2061 &s->state.local_mem_region); 2062 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, 2063 &s->state.mmio_region); 2064 } 2065 2066 static Property sm501_pci_properties[] = { 2067 DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), 2068 DEFINE_PROP_END_OF_LIST(), 2069 }; 2070 2071 static void sm501_reset_pci(DeviceState *dev) 2072 { 2073 SM501PCIState *s = PCI_SM501(dev); 2074 sm501_reset(&s->state); 2075 /* Bits 2:0 of misc_control register is 001 for PCI */ 2076 s->state.misc_control |= 1; 2077 } 2078 2079 static const VMStateDescription vmstate_sm501_pci = { 2080 .name = TYPE_PCI_SM501, 2081 .version_id = 2, 2082 .minimum_version_id = 2, 2083 .fields = (VMStateField[]) { 2084 VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState), 2085 VMSTATE_STRUCT(state, SM501PCIState, 1, 2086 vmstate_sm501_state, SM501State), 2087 VMSTATE_END_OF_LIST() 2088 } 2089 }; 2090 2091 static void sm501_pci_class_init(ObjectClass *klass, void *data) 2092 { 2093 DeviceClass *dc = DEVICE_CLASS(klass); 2094 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2095 2096 k->realize = sm501_realize_pci; 2097 k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION; 2098 k->device_id = PCI_DEVICE_ID_SM501; 2099 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2100 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2101 dc->desc = "SM501 Display Controller"; 2102 device_class_set_props(dc, sm501_pci_properties); 2103 dc->reset = sm501_reset_pci; 2104 dc->hotpluggable = false; 2105 dc->vmsd = &vmstate_sm501_pci; 2106 } 2107 2108 static const TypeInfo sm501_pci_info = { 2109 .name = TYPE_PCI_SM501, 2110 .parent = TYPE_PCI_DEVICE, 2111 .instance_size = sizeof(SM501PCIState), 2112 .class_init = sm501_pci_class_init, 2113 .interfaces = (InterfaceInfo[]) { 2114 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2115 { }, 2116 }, 2117 }; 2118 2119 static void sm501_register_types(void) 2120 { 2121 type_register_static(&sm501_sysbus_info); 2122 type_register_static(&sm501_pci_info); 2123 } 2124 2125 type_init(sm501_register_types) 2126