1a643bd77SLinus Walleij /* 2a643bd77SLinus Walleij * Silicon Image SiI9022 3a643bd77SLinus Walleij * 4a643bd77SLinus Walleij * This is a pretty hollow emulation: all we do is acknowledge that we 5a643bd77SLinus Walleij * exist (chip ID) and confirm that we get switched over into DDC mode 6a643bd77SLinus Walleij * so the emulated host can proceed to read out EDID data. All subsequent 7a643bd77SLinus Walleij * set-up of connectors etc will be acknowledged and ignored. 8a643bd77SLinus Walleij * 9a643bd77SLinus Walleij * Copyright (C) 2018 Linus Walleij 10a643bd77SLinus Walleij * 11a643bd77SLinus Walleij * This work is licensed under the terms of the GNU GPL, version 2 or later. 12a643bd77SLinus Walleij * See the COPYING file in the top-level directory. 13a643bd77SLinus Walleij * SPDX-License-Identifier: GPL-2.0-or-later 14a643bd77SLinus Walleij */ 15a643bd77SLinus Walleij 16a643bd77SLinus Walleij #include "qemu/osdep.h" 170b8fa32fSMarkus Armbruster #include "qemu/module.h" 18a643bd77SLinus Walleij #include "hw/i2c/i2c.h" 19d6454270SMarkus Armbruster #include "migration/vmstate.h" 206306cae2SPaolo Bonzini #include "hw/display/i2c-ddc.h" 21a643bd77SLinus Walleij #include "trace.h" 22*db1015e9SEduardo Habkost #include "qom/object.h" 23a643bd77SLinus Walleij 24a643bd77SLinus Walleij #define SII9022_SYS_CTRL_DATA 0x1a 25a643bd77SLinus Walleij #define SII9022_SYS_CTRL_PWR_DWN 0x10 26a643bd77SLinus Walleij #define SII9022_SYS_CTRL_AV_MUTE 0x08 27a643bd77SLinus Walleij #define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04 28a643bd77SLinus Walleij #define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02 29a643bd77SLinus Walleij #define SII9022_SYS_CTRL_OUTPUT_MODE 0x01 30a643bd77SLinus Walleij #define SII9022_SYS_CTRL_OUTPUT_HDMI 1 31a643bd77SLinus Walleij #define SII9022_SYS_CTRL_OUTPUT_DVI 0 32a643bd77SLinus Walleij #define SII9022_REG_CHIPID 0x1b 33a643bd77SLinus Walleij #define SII9022_INT_ENABLE 0x3c 34a643bd77SLinus Walleij #define SII9022_INT_STATUS 0x3d 35a643bd77SLinus Walleij #define SII9022_INT_STATUS_HOTPLUG 0x01; 36a643bd77SLinus Walleij #define SII9022_INT_STATUS_PLUGGED 0x04; 37a643bd77SLinus Walleij 38a643bd77SLinus Walleij #define TYPE_SII9022 "sii9022" 39*db1015e9SEduardo Habkost typedef struct sii9022_state sii9022_state; 40a643bd77SLinus Walleij #define SII9022(obj) OBJECT_CHECK(sii9022_state, (obj), TYPE_SII9022) 41a643bd77SLinus Walleij 42*db1015e9SEduardo Habkost struct sii9022_state { 43a643bd77SLinus Walleij I2CSlave parent_obj; 44a643bd77SLinus Walleij uint8_t ptr; 45a643bd77SLinus Walleij bool addr_byte; 46a643bd77SLinus Walleij bool ddc_req; 47a643bd77SLinus Walleij bool ddc_skip_finish; 48a643bd77SLinus Walleij bool ddc; 49*db1015e9SEduardo Habkost }; 50a643bd77SLinus Walleij 51a643bd77SLinus Walleij static const VMStateDescription vmstate_sii9022 = { 52a643bd77SLinus Walleij .name = "sii9022", 53a643bd77SLinus Walleij .version_id = 1, 54a643bd77SLinus Walleij .minimum_version_id = 1, 55a643bd77SLinus Walleij .fields = (VMStateField[]) { 56a643bd77SLinus Walleij VMSTATE_I2C_SLAVE(parent_obj, sii9022_state), 57a643bd77SLinus Walleij VMSTATE_UINT8(ptr, sii9022_state), 58a643bd77SLinus Walleij VMSTATE_BOOL(addr_byte, sii9022_state), 59a643bd77SLinus Walleij VMSTATE_BOOL(ddc_req, sii9022_state), 60a643bd77SLinus Walleij VMSTATE_BOOL(ddc_skip_finish, sii9022_state), 61a643bd77SLinus Walleij VMSTATE_BOOL(ddc, sii9022_state), 62a643bd77SLinus Walleij VMSTATE_END_OF_LIST() 63a643bd77SLinus Walleij } 64a643bd77SLinus Walleij }; 65a643bd77SLinus Walleij 66a643bd77SLinus Walleij static int sii9022_event(I2CSlave *i2c, enum i2c_event event) 67a643bd77SLinus Walleij { 68a643bd77SLinus Walleij sii9022_state *s = SII9022(i2c); 69a643bd77SLinus Walleij 70a643bd77SLinus Walleij switch (event) { 71a643bd77SLinus Walleij case I2C_START_SEND: 72a643bd77SLinus Walleij s->addr_byte = true; 73a643bd77SLinus Walleij break; 74a643bd77SLinus Walleij case I2C_START_RECV: 75a643bd77SLinus Walleij break; 76a643bd77SLinus Walleij case I2C_FINISH: 77a643bd77SLinus Walleij break; 78a643bd77SLinus Walleij case I2C_NACK: 79a643bd77SLinus Walleij break; 80a643bd77SLinus Walleij } 81a643bd77SLinus Walleij 82a643bd77SLinus Walleij return 0; 83a643bd77SLinus Walleij } 84a643bd77SLinus Walleij 852ac4c5f4SCorey Minyard static uint8_t sii9022_rx(I2CSlave *i2c) 86a643bd77SLinus Walleij { 87a643bd77SLinus Walleij sii9022_state *s = SII9022(i2c); 88a643bd77SLinus Walleij uint8_t res = 0x00; 89a643bd77SLinus Walleij 90a643bd77SLinus Walleij switch (s->ptr) { 91a643bd77SLinus Walleij case SII9022_SYS_CTRL_DATA: 92a643bd77SLinus Walleij if (s->ddc_req) { 93a643bd77SLinus Walleij /* Acknowledge DDC bus request */ 94a643bd77SLinus Walleij res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ; 95a643bd77SLinus Walleij } 96a643bd77SLinus Walleij break; 97a643bd77SLinus Walleij case SII9022_REG_CHIPID: 98a643bd77SLinus Walleij res = 0xb0; 99a643bd77SLinus Walleij break; 100a643bd77SLinus Walleij case SII9022_INT_STATUS: 101a643bd77SLinus Walleij /* Something is cold-plugged in, no interrupts */ 102a643bd77SLinus Walleij res = SII9022_INT_STATUS_PLUGGED; 103a643bd77SLinus Walleij break; 104a643bd77SLinus Walleij default: 105a643bd77SLinus Walleij break; 106a643bd77SLinus Walleij } 107a643bd77SLinus Walleij 108a643bd77SLinus Walleij trace_sii9022_read_reg(s->ptr, res); 109a643bd77SLinus Walleij s->ptr++; 110a643bd77SLinus Walleij 111a643bd77SLinus Walleij return res; 112a643bd77SLinus Walleij } 113a643bd77SLinus Walleij 114a643bd77SLinus Walleij static int sii9022_tx(I2CSlave *i2c, uint8_t data) 115a643bd77SLinus Walleij { 116a643bd77SLinus Walleij sii9022_state *s = SII9022(i2c); 117a643bd77SLinus Walleij 118a643bd77SLinus Walleij if (s->addr_byte) { 119a643bd77SLinus Walleij s->ptr = data; 120a643bd77SLinus Walleij s->addr_byte = false; 121a643bd77SLinus Walleij return 0; 122a643bd77SLinus Walleij } 123a643bd77SLinus Walleij 124a643bd77SLinus Walleij switch (s->ptr) { 125a643bd77SLinus Walleij case SII9022_SYS_CTRL_DATA: 126a643bd77SLinus Walleij if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) { 127a643bd77SLinus Walleij s->ddc_req = true; 128a643bd77SLinus Walleij if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) { 129a643bd77SLinus Walleij s->ddc = true; 130a643bd77SLinus Walleij /* Skip this finish since we just switched to DDC */ 131a643bd77SLinus Walleij s->ddc_skip_finish = true; 132a643bd77SLinus Walleij trace_sii9022_switch_mode("DDC"); 133a643bd77SLinus Walleij } 134a643bd77SLinus Walleij } else { 135a643bd77SLinus Walleij s->ddc_req = false; 136a643bd77SLinus Walleij s->ddc = false; 137a643bd77SLinus Walleij trace_sii9022_switch_mode("normal"); 138a643bd77SLinus Walleij } 139a643bd77SLinus Walleij break; 140a643bd77SLinus Walleij default: 141a643bd77SLinus Walleij break; 142a643bd77SLinus Walleij } 143a643bd77SLinus Walleij 144a643bd77SLinus Walleij trace_sii9022_write_reg(s->ptr, data); 145a643bd77SLinus Walleij s->ptr++; 146a643bd77SLinus Walleij 147a643bd77SLinus Walleij return 0; 148a643bd77SLinus Walleij } 149a643bd77SLinus Walleij 150a643bd77SLinus Walleij static void sii9022_reset(DeviceState *dev) 151a643bd77SLinus Walleij { 152a643bd77SLinus Walleij sii9022_state *s = SII9022(dev); 153a643bd77SLinus Walleij 154a643bd77SLinus Walleij s->ptr = 0; 155a643bd77SLinus Walleij s->addr_byte = false; 156a643bd77SLinus Walleij s->ddc_req = false; 157a643bd77SLinus Walleij s->ddc_skip_finish = false; 158a643bd77SLinus Walleij s->ddc = false; 159a643bd77SLinus Walleij } 160a643bd77SLinus Walleij 161a643bd77SLinus Walleij static void sii9022_realize(DeviceState *dev, Error **errp) 162a643bd77SLinus Walleij { 163a643bd77SLinus Walleij I2CBus *bus; 164a643bd77SLinus Walleij 165a643bd77SLinus Walleij bus = I2C_BUS(qdev_get_parent_bus(dev)); 1661373b15bSPhilippe Mathieu-Daudé i2c_slave_create_simple(bus, TYPE_I2CDDC, 0x50); 167a643bd77SLinus Walleij } 168a643bd77SLinus Walleij 169a643bd77SLinus Walleij static void sii9022_class_init(ObjectClass *klass, void *data) 170a643bd77SLinus Walleij { 171a643bd77SLinus Walleij DeviceClass *dc = DEVICE_CLASS(klass); 172a643bd77SLinus Walleij I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); 173a643bd77SLinus Walleij 174a643bd77SLinus Walleij k->event = sii9022_event; 175a643bd77SLinus Walleij k->recv = sii9022_rx; 176a643bd77SLinus Walleij k->send = sii9022_tx; 177a643bd77SLinus Walleij dc->reset = sii9022_reset; 178a643bd77SLinus Walleij dc->realize = sii9022_realize; 179a643bd77SLinus Walleij dc->vmsd = &vmstate_sii9022; 180a643bd77SLinus Walleij } 181a643bd77SLinus Walleij 182a643bd77SLinus Walleij static const TypeInfo sii9022_info = { 183a643bd77SLinus Walleij .name = TYPE_SII9022, 184a643bd77SLinus Walleij .parent = TYPE_I2C_SLAVE, 185a643bd77SLinus Walleij .instance_size = sizeof(sii9022_state), 186a643bd77SLinus Walleij .class_init = sii9022_class_init, 187a643bd77SLinus Walleij }; 188a643bd77SLinus Walleij 189a643bd77SLinus Walleij static void sii9022_register_types(void) 190a643bd77SLinus Walleij { 191a643bd77SLinus Walleij type_register_static(&sii9022_info); 192a643bd77SLinus Walleij } 193a643bd77SLinus Walleij 194a643bd77SLinus Walleij type_init(sii9022_register_types) 195