xref: /qemu/hw/display/sii9022.c (revision 2ac4c5f4d2415116d3f417a32311d437791dcfce)
1a643bd77SLinus Walleij /*
2a643bd77SLinus Walleij  * Silicon Image SiI9022
3a643bd77SLinus Walleij  *
4a643bd77SLinus Walleij  * This is a pretty hollow emulation: all we do is acknowledge that we
5a643bd77SLinus Walleij  * exist (chip ID) and confirm that we get switched over into DDC mode
6a643bd77SLinus Walleij  * so the emulated host can proceed to read out EDID data. All subsequent
7a643bd77SLinus Walleij  * set-up of connectors etc will be acknowledged and ignored.
8a643bd77SLinus Walleij  *
9a643bd77SLinus Walleij  * Copyright (C) 2018 Linus Walleij
10a643bd77SLinus Walleij  *
11a643bd77SLinus Walleij  * This work is licensed under the terms of the GNU GPL, version 2 or later.
12a643bd77SLinus Walleij  * See the COPYING file in the top-level directory.
13a643bd77SLinus Walleij  * SPDX-License-Identifier: GPL-2.0-or-later
14a643bd77SLinus Walleij  */
15a643bd77SLinus Walleij 
16a643bd77SLinus Walleij #include "qemu/osdep.h"
17a643bd77SLinus Walleij #include "qemu-common.h"
18a643bd77SLinus Walleij #include "hw/i2c/i2c.h"
19a643bd77SLinus Walleij #include "hw/i2c/i2c-ddc.h"
20a643bd77SLinus Walleij #include "trace.h"
21a643bd77SLinus Walleij 
22a643bd77SLinus Walleij #define SII9022_SYS_CTRL_DATA 0x1a
23a643bd77SLinus Walleij #define SII9022_SYS_CTRL_PWR_DWN 0x10
24a643bd77SLinus Walleij #define SII9022_SYS_CTRL_AV_MUTE 0x08
25a643bd77SLinus Walleij #define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04
26a643bd77SLinus Walleij #define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02
27a643bd77SLinus Walleij #define SII9022_SYS_CTRL_OUTPUT_MODE 0x01
28a643bd77SLinus Walleij #define SII9022_SYS_CTRL_OUTPUT_HDMI 1
29a643bd77SLinus Walleij #define SII9022_SYS_CTRL_OUTPUT_DVI 0
30a643bd77SLinus Walleij #define SII9022_REG_CHIPID 0x1b
31a643bd77SLinus Walleij #define SII9022_INT_ENABLE 0x3c
32a643bd77SLinus Walleij #define SII9022_INT_STATUS 0x3d
33a643bd77SLinus Walleij #define SII9022_INT_STATUS_HOTPLUG 0x01;
34a643bd77SLinus Walleij #define SII9022_INT_STATUS_PLUGGED 0x04;
35a643bd77SLinus Walleij 
36a643bd77SLinus Walleij #define TYPE_SII9022 "sii9022"
37a643bd77SLinus Walleij #define SII9022(obj) OBJECT_CHECK(sii9022_state, (obj), TYPE_SII9022)
38a643bd77SLinus Walleij 
39a643bd77SLinus Walleij typedef struct sii9022_state {
40a643bd77SLinus Walleij     I2CSlave parent_obj;
41a643bd77SLinus Walleij     uint8_t ptr;
42a643bd77SLinus Walleij     bool addr_byte;
43a643bd77SLinus Walleij     bool ddc_req;
44a643bd77SLinus Walleij     bool ddc_skip_finish;
45a643bd77SLinus Walleij     bool ddc;
46a643bd77SLinus Walleij } sii9022_state;
47a643bd77SLinus Walleij 
48a643bd77SLinus Walleij static const VMStateDescription vmstate_sii9022 = {
49a643bd77SLinus Walleij     .name = "sii9022",
50a643bd77SLinus Walleij     .version_id = 1,
51a643bd77SLinus Walleij     .minimum_version_id = 1,
52a643bd77SLinus Walleij     .fields = (VMStateField[]) {
53a643bd77SLinus Walleij         VMSTATE_I2C_SLAVE(parent_obj, sii9022_state),
54a643bd77SLinus Walleij         VMSTATE_UINT8(ptr, sii9022_state),
55a643bd77SLinus Walleij         VMSTATE_BOOL(addr_byte, sii9022_state),
56a643bd77SLinus Walleij         VMSTATE_BOOL(ddc_req, sii9022_state),
57a643bd77SLinus Walleij         VMSTATE_BOOL(ddc_skip_finish, sii9022_state),
58a643bd77SLinus Walleij         VMSTATE_BOOL(ddc, sii9022_state),
59a643bd77SLinus Walleij         VMSTATE_END_OF_LIST()
60a643bd77SLinus Walleij     }
61a643bd77SLinus Walleij };
62a643bd77SLinus Walleij 
63a643bd77SLinus Walleij static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
64a643bd77SLinus Walleij {
65a643bd77SLinus Walleij     sii9022_state *s = SII9022(i2c);
66a643bd77SLinus Walleij 
67a643bd77SLinus Walleij     switch (event) {
68a643bd77SLinus Walleij     case I2C_START_SEND:
69a643bd77SLinus Walleij         s->addr_byte = true;
70a643bd77SLinus Walleij         break;
71a643bd77SLinus Walleij     case I2C_START_RECV:
72a643bd77SLinus Walleij         break;
73a643bd77SLinus Walleij     case I2C_FINISH:
74a643bd77SLinus Walleij         break;
75a643bd77SLinus Walleij     case I2C_NACK:
76a643bd77SLinus Walleij         break;
77a643bd77SLinus Walleij     }
78a643bd77SLinus Walleij 
79a643bd77SLinus Walleij     return 0;
80a643bd77SLinus Walleij }
81a643bd77SLinus Walleij 
82*2ac4c5f4SCorey Minyard static uint8_t sii9022_rx(I2CSlave *i2c)
83a643bd77SLinus Walleij {
84a643bd77SLinus Walleij     sii9022_state *s = SII9022(i2c);
85a643bd77SLinus Walleij     uint8_t res = 0x00;
86a643bd77SLinus Walleij 
87a643bd77SLinus Walleij     switch (s->ptr) {
88a643bd77SLinus Walleij     case SII9022_SYS_CTRL_DATA:
89a643bd77SLinus Walleij         if (s->ddc_req) {
90a643bd77SLinus Walleij             /* Acknowledge DDC bus request */
91a643bd77SLinus Walleij             res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ;
92a643bd77SLinus Walleij         }
93a643bd77SLinus Walleij         break;
94a643bd77SLinus Walleij     case SII9022_REG_CHIPID:
95a643bd77SLinus Walleij         res = 0xb0;
96a643bd77SLinus Walleij         break;
97a643bd77SLinus Walleij     case SII9022_INT_STATUS:
98a643bd77SLinus Walleij         /* Something is cold-plugged in, no interrupts */
99a643bd77SLinus Walleij         res = SII9022_INT_STATUS_PLUGGED;
100a643bd77SLinus Walleij         break;
101a643bd77SLinus Walleij     default:
102a643bd77SLinus Walleij         break;
103a643bd77SLinus Walleij     }
104a643bd77SLinus Walleij 
105a643bd77SLinus Walleij     trace_sii9022_read_reg(s->ptr, res);
106a643bd77SLinus Walleij     s->ptr++;
107a643bd77SLinus Walleij 
108a643bd77SLinus Walleij     return res;
109a643bd77SLinus Walleij }
110a643bd77SLinus Walleij 
111a643bd77SLinus Walleij static int sii9022_tx(I2CSlave *i2c, uint8_t data)
112a643bd77SLinus Walleij {
113a643bd77SLinus Walleij     sii9022_state *s = SII9022(i2c);
114a643bd77SLinus Walleij 
115a643bd77SLinus Walleij     if (s->addr_byte) {
116a643bd77SLinus Walleij         s->ptr = data;
117a643bd77SLinus Walleij         s->addr_byte = false;
118a643bd77SLinus Walleij         return 0;
119a643bd77SLinus Walleij     }
120a643bd77SLinus Walleij 
121a643bd77SLinus Walleij     switch (s->ptr) {
122a643bd77SLinus Walleij     case SII9022_SYS_CTRL_DATA:
123a643bd77SLinus Walleij         if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) {
124a643bd77SLinus Walleij             s->ddc_req = true;
125a643bd77SLinus Walleij             if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) {
126a643bd77SLinus Walleij                 s->ddc = true;
127a643bd77SLinus Walleij                 /* Skip this finish since we just switched to DDC */
128a643bd77SLinus Walleij                 s->ddc_skip_finish = true;
129a643bd77SLinus Walleij                 trace_sii9022_switch_mode("DDC");
130a643bd77SLinus Walleij             }
131a643bd77SLinus Walleij         } else {
132a643bd77SLinus Walleij             s->ddc_req = false;
133a643bd77SLinus Walleij             s->ddc = false;
134a643bd77SLinus Walleij             trace_sii9022_switch_mode("normal");
135a643bd77SLinus Walleij         }
136a643bd77SLinus Walleij         break;
137a643bd77SLinus Walleij     default:
138a643bd77SLinus Walleij         break;
139a643bd77SLinus Walleij     }
140a643bd77SLinus Walleij 
141a643bd77SLinus Walleij     trace_sii9022_write_reg(s->ptr, data);
142a643bd77SLinus Walleij     s->ptr++;
143a643bd77SLinus Walleij 
144a643bd77SLinus Walleij     return 0;
145a643bd77SLinus Walleij }
146a643bd77SLinus Walleij 
147a643bd77SLinus Walleij static void sii9022_reset(DeviceState *dev)
148a643bd77SLinus Walleij {
149a643bd77SLinus Walleij     sii9022_state *s = SII9022(dev);
150a643bd77SLinus Walleij 
151a643bd77SLinus Walleij     s->ptr = 0;
152a643bd77SLinus Walleij     s->addr_byte = false;
153a643bd77SLinus Walleij     s->ddc_req = false;
154a643bd77SLinus Walleij     s->ddc_skip_finish = false;
155a643bd77SLinus Walleij     s->ddc = false;
156a643bd77SLinus Walleij }
157a643bd77SLinus Walleij 
158a643bd77SLinus Walleij static void sii9022_realize(DeviceState *dev, Error **errp)
159a643bd77SLinus Walleij {
160a643bd77SLinus Walleij     I2CBus *bus;
161a643bd77SLinus Walleij 
162a643bd77SLinus Walleij     bus = I2C_BUS(qdev_get_parent_bus(dev));
163a643bd77SLinus Walleij     i2c_create_slave(bus, TYPE_I2CDDC, 0x50);
164a643bd77SLinus Walleij }
165a643bd77SLinus Walleij 
166a643bd77SLinus Walleij static void sii9022_class_init(ObjectClass *klass, void *data)
167a643bd77SLinus Walleij {
168a643bd77SLinus Walleij     DeviceClass *dc = DEVICE_CLASS(klass);
169a643bd77SLinus Walleij     I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
170a643bd77SLinus Walleij 
171a643bd77SLinus Walleij     k->event = sii9022_event;
172a643bd77SLinus Walleij     k->recv = sii9022_rx;
173a643bd77SLinus Walleij     k->send = sii9022_tx;
174a643bd77SLinus Walleij     dc->reset = sii9022_reset;
175a643bd77SLinus Walleij     dc->realize = sii9022_realize;
176a643bd77SLinus Walleij     dc->vmsd = &vmstate_sii9022;
177a643bd77SLinus Walleij }
178a643bd77SLinus Walleij 
179a643bd77SLinus Walleij static const TypeInfo sii9022_info = {
180a643bd77SLinus Walleij     .name          = TYPE_SII9022,
181a643bd77SLinus Walleij     .parent        = TYPE_I2C_SLAVE,
182a643bd77SLinus Walleij     .instance_size = sizeof(sii9022_state),
183a643bd77SLinus Walleij     .class_init    = sii9022_class_init,
184a643bd77SLinus Walleij };
185a643bd77SLinus Walleij 
186a643bd77SLinus Walleij static void sii9022_register_types(void)
187a643bd77SLinus Walleij {
188a643bd77SLinus Walleij     type_register_static(&sii9022_info);
189a643bd77SLinus Walleij }
190a643bd77SLinus Walleij 
191a643bd77SLinus Walleij type_init(sii9022_register_types)
192