1 /* 2 * QEMU G364 framebuffer Emulator. 3 * 4 * Copyright (c) 2007-2011 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "hw.h" 21 #include "console.h" 22 #include "pixel_ops.h" 23 #include "trace.h" 24 #include "sysbus.h" 25 26 typedef struct G364State { 27 /* hardware */ 28 uint8_t *vram; 29 uint32_t vram_size; 30 qemu_irq irq; 31 MemoryRegion mem_vram; 32 MemoryRegion mem_ctrl; 33 /* registers */ 34 uint8_t color_palette[256][3]; 35 uint8_t cursor_palette[3][3]; 36 uint16_t cursor[512]; 37 uint32_t cursor_position; 38 uint32_t ctla; 39 uint32_t top_of_screen; 40 uint32_t width, height; /* in pixels */ 41 /* display refresh support */ 42 DisplayState *ds; 43 int depth; 44 int blanked; 45 } G364State; 46 47 #define REG_BOOT 0x000000 48 #define REG_DISPLAY 0x000118 49 #define REG_VDISPLAY 0x000150 50 #define REG_CTLA 0x000300 51 #define REG_TOP 0x000400 52 #define REG_CURS_PAL 0x000508 53 #define REG_CURS_POS 0x000638 54 #define REG_CLR_PAL 0x000800 55 #define REG_CURS_PAT 0x001000 56 #define REG_RESET 0x100000 57 58 #define CTLA_FORCE_BLANK 0x00000400 59 #define CTLA_NO_CURSOR 0x00800000 60 61 #define G364_PAGE_SIZE 4096 62 63 static inline int check_dirty(G364State *s, ram_addr_t page) 64 { 65 return memory_region_get_dirty(&s->mem_vram, page, G364_PAGE_SIZE, 66 DIRTY_MEMORY_VGA); 67 } 68 69 static inline void reset_dirty(G364State *s, 70 ram_addr_t page_min, ram_addr_t page_max) 71 { 72 memory_region_reset_dirty(&s->mem_vram, 73 page_min, 74 page_max + G364_PAGE_SIZE - page_min - 1, 75 DIRTY_MEMORY_VGA); 76 } 77 78 static void g364fb_draw_graphic8(G364State *s) 79 { 80 int i, w; 81 uint8_t *vram; 82 uint8_t *data_display, *dd; 83 ram_addr_t page, page_min, page_max; 84 int x, y; 85 int xmin, xmax; 86 int ymin, ymax; 87 int xcursor, ycursor; 88 unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b); 89 90 switch (ds_get_bits_per_pixel(s->ds)) { 91 case 8: 92 rgb_to_pixel = rgb_to_pixel8; 93 w = 1; 94 break; 95 case 15: 96 rgb_to_pixel = rgb_to_pixel15; 97 w = 2; 98 break; 99 case 16: 100 rgb_to_pixel = rgb_to_pixel16; 101 w = 2; 102 break; 103 case 32: 104 rgb_to_pixel = rgb_to_pixel32; 105 w = 4; 106 break; 107 default: 108 hw_error("g364: unknown host depth %d", 109 ds_get_bits_per_pixel(s->ds)); 110 return; 111 } 112 113 page = 0; 114 page_min = (ram_addr_t)-1; 115 page_max = 0; 116 117 x = y = 0; 118 xmin = s->width; 119 xmax = 0; 120 ymin = s->height; 121 ymax = 0; 122 123 if (!(s->ctla & CTLA_NO_CURSOR)) { 124 xcursor = s->cursor_position >> 12; 125 ycursor = s->cursor_position & 0xfff; 126 } else { 127 xcursor = ycursor = -65; 128 } 129 130 vram = s->vram + s->top_of_screen; 131 /* XXX: out of range in vram? */ 132 data_display = dd = ds_get_data(s->ds); 133 while (y < s->height) { 134 if (check_dirty(s, page)) { 135 if (y < ymin) 136 ymin = ymax = y; 137 if (page_min == (ram_addr_t)-1) 138 page_min = page; 139 page_max = page; 140 if (x < xmin) 141 xmin = x; 142 for (i = 0; i < G364_PAGE_SIZE; i++) { 143 uint8_t index; 144 unsigned int color; 145 if (unlikely((y >= ycursor && y < ycursor + 64) && 146 (x >= xcursor && x < xcursor + 64))) { 147 /* pointer area */ 148 int xdiff = x - xcursor; 149 uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8]; 150 int op = (curs >> ((xdiff & 7) * 2)) & 3; 151 if (likely(op == 0)) { 152 /* transparent */ 153 index = *vram; 154 color = (*rgb_to_pixel)( 155 s->color_palette[index][0], 156 s->color_palette[index][1], 157 s->color_palette[index][2]); 158 } else { 159 /* get cursor color */ 160 index = op - 1; 161 color = (*rgb_to_pixel)( 162 s->cursor_palette[index][0], 163 s->cursor_palette[index][1], 164 s->cursor_palette[index][2]); 165 } 166 } else { 167 /* normal area */ 168 index = *vram; 169 color = (*rgb_to_pixel)( 170 s->color_palette[index][0], 171 s->color_palette[index][1], 172 s->color_palette[index][2]); 173 } 174 memcpy(dd, &color, w); 175 dd += w; 176 x++; 177 vram++; 178 if (x == s->width) { 179 xmax = s->width - 1; 180 y++; 181 if (y == s->height) { 182 ymax = s->height - 1; 183 goto done; 184 } 185 data_display = dd = data_display + ds_get_linesize(s->ds); 186 xmin = 0; 187 x = 0; 188 } 189 } 190 if (x > xmax) 191 xmax = x; 192 if (y > ymax) 193 ymax = y; 194 } else { 195 int dy; 196 if (page_min != (ram_addr_t)-1) { 197 reset_dirty(s, page_min, page_max); 198 page_min = (ram_addr_t)-1; 199 page_max = 0; 200 dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); 201 xmin = s->width; 202 xmax = 0; 203 ymin = s->height; 204 ymax = 0; 205 } 206 x += G364_PAGE_SIZE; 207 dy = x / s->width; 208 x = x % s->width; 209 y += dy; 210 vram += G364_PAGE_SIZE; 211 data_display += dy * ds_get_linesize(s->ds); 212 dd = data_display + x * w; 213 } 214 page += G364_PAGE_SIZE; 215 } 216 217 done: 218 if (page_min != (ram_addr_t)-1) { 219 dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); 220 reset_dirty(s, page_min, page_max); 221 } 222 } 223 224 static void g364fb_draw_blank(G364State *s) 225 { 226 int i, w; 227 uint8_t *d; 228 229 if (s->blanked) { 230 /* Screen is already blank. No need to redraw it */ 231 return; 232 } 233 234 w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3); 235 d = ds_get_data(s->ds); 236 for (i = 0; i < s->height; i++) { 237 memset(d, 0, w); 238 d += ds_get_linesize(s->ds); 239 } 240 241 dpy_update(s->ds, 0, 0, s->width, s->height); 242 s->blanked = 1; 243 } 244 245 static void g364fb_update_display(void *opaque) 246 { 247 G364State *s = opaque; 248 249 qemu_flush_coalesced_mmio_buffer(); 250 251 if (s->width == 0 || s->height == 0) 252 return; 253 254 if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) { 255 qemu_console_resize(s->ds, s->width, s->height); 256 } 257 258 if (s->ctla & CTLA_FORCE_BLANK) { 259 g364fb_draw_blank(s); 260 } else if (s->depth == 8) { 261 g364fb_draw_graphic8(s); 262 } else { 263 error_report("g364: unknown guest depth %d", s->depth); 264 } 265 266 qemu_irq_raise(s->irq); 267 } 268 269 static inline void g364fb_invalidate_display(void *opaque) 270 { 271 G364State *s = opaque; 272 273 s->blanked = 0; 274 memory_region_set_dirty(&s->mem_vram, 0, s->vram_size); 275 } 276 277 static void g364fb_reset(G364State *s) 278 { 279 qemu_irq_lower(s->irq); 280 281 memset(s->color_palette, 0, sizeof(s->color_palette)); 282 memset(s->cursor_palette, 0, sizeof(s->cursor_palette)); 283 memset(s->cursor, 0, sizeof(s->cursor)); 284 s->cursor_position = 0; 285 s->ctla = 0; 286 s->top_of_screen = 0; 287 s->width = s->height = 0; 288 memset(s->vram, 0, s->vram_size); 289 g364fb_invalidate_display(s); 290 } 291 292 static void g364fb_screen_dump(void *opaque, const char *filename, bool cswitch, 293 Error **errp) 294 { 295 G364State *s = opaque; 296 int y, x; 297 uint8_t index; 298 uint8_t *data_buffer; 299 FILE *f; 300 301 qemu_flush_coalesced_mmio_buffer(); 302 303 if (s->depth != 8) { 304 error_report("g364: unknown guest depth %d", s->depth); 305 return; 306 } 307 308 f = fopen(filename, "wb"); 309 if (!f) 310 return; 311 312 if (s->ctla & CTLA_FORCE_BLANK) { 313 /* blank screen */ 314 fprintf(f, "P4\n%d %d\n", 315 s->width, s->height); 316 for (y = 0; y < s->height; y++) 317 for (x = 0; x < s->width; x++) 318 fputc(0, f); 319 } else { 320 data_buffer = s->vram + s->top_of_screen; 321 fprintf(f, "P6\n%d %d\n%d\n", 322 s->width, s->height, 255); 323 for (y = 0; y < s->height; y++) 324 for (x = 0; x < s->width; x++, data_buffer++) { 325 index = *data_buffer; 326 fputc(s->color_palette[index][0], f); 327 fputc(s->color_palette[index][1], f); 328 fputc(s->color_palette[index][2], f); 329 } 330 } 331 332 fclose(f); 333 } 334 335 /* called for accesses to io ports */ 336 static uint64_t g364fb_ctrl_read(void *opaque, 337 target_phys_addr_t addr, 338 unsigned int size) 339 { 340 G364State *s = opaque; 341 uint32_t val; 342 343 if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { 344 /* cursor pattern */ 345 int idx = (addr - REG_CURS_PAT) >> 3; 346 val = s->cursor[idx]; 347 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { 348 /* cursor palette */ 349 int idx = (addr - REG_CURS_PAL) >> 3; 350 val = ((uint32_t)s->cursor_palette[idx][0] << 16); 351 val |= ((uint32_t)s->cursor_palette[idx][1] << 8); 352 val |= ((uint32_t)s->cursor_palette[idx][2] << 0); 353 } else { 354 switch (addr) { 355 case REG_DISPLAY: 356 val = s->width / 4; 357 break; 358 case REG_VDISPLAY: 359 val = s->height * 2; 360 break; 361 case REG_CTLA: 362 val = s->ctla; 363 break; 364 default: 365 { 366 error_report("g364: invalid read at [" TARGET_FMT_plx "]", 367 addr); 368 val = 0; 369 break; 370 } 371 } 372 } 373 374 trace_g364fb_read(addr, val); 375 376 return val; 377 } 378 379 static void g364fb_update_depth(G364State *s) 380 { 381 static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 }; 382 s->depth = depths[(s->ctla & 0x00700000) >> 20]; 383 } 384 385 static void g364_invalidate_cursor_position(G364State *s) 386 { 387 int ymin, ymax, start, end; 388 389 /* invalidate only near the cursor */ 390 ymin = s->cursor_position & 0xfff; 391 ymax = MIN(s->height, ymin + 64); 392 start = ymin * ds_get_linesize(s->ds); 393 end = (ymax + 1) * ds_get_linesize(s->ds); 394 395 memory_region_set_dirty(&s->mem_vram, start, end - start); 396 } 397 398 static void g364fb_ctrl_write(void *opaque, 399 target_phys_addr_t addr, 400 uint64_t val, 401 unsigned int size) 402 { 403 G364State *s = opaque; 404 405 trace_g364fb_write(addr, val); 406 407 if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) { 408 /* color palette */ 409 int idx = (addr - REG_CLR_PAL) >> 3; 410 s->color_palette[idx][0] = (val >> 16) & 0xff; 411 s->color_palette[idx][1] = (val >> 8) & 0xff; 412 s->color_palette[idx][2] = val & 0xff; 413 g364fb_invalidate_display(s); 414 } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { 415 /* cursor pattern */ 416 int idx = (addr - REG_CURS_PAT) >> 3; 417 s->cursor[idx] = val; 418 g364fb_invalidate_display(s); 419 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { 420 /* cursor palette */ 421 int idx = (addr - REG_CURS_PAL) >> 3; 422 s->cursor_palette[idx][0] = (val >> 16) & 0xff; 423 s->cursor_palette[idx][1] = (val >> 8) & 0xff; 424 s->cursor_palette[idx][2] = val & 0xff; 425 g364fb_invalidate_display(s); 426 } else { 427 switch (addr) { 428 case REG_BOOT: /* Boot timing */ 429 case 0x00108: /* Line timing: half sync */ 430 case 0x00110: /* Line timing: back porch */ 431 case 0x00120: /* Line timing: short display */ 432 case 0x00128: /* Frame timing: broad pulse */ 433 case 0x00130: /* Frame timing: v sync */ 434 case 0x00138: /* Frame timing: v preequalise */ 435 case 0x00140: /* Frame timing: v postequalise */ 436 case 0x00148: /* Frame timing: v blank */ 437 case 0x00158: /* Line timing: line time */ 438 case 0x00160: /* Frame store: line start */ 439 case 0x00168: /* vram cycle: mem init */ 440 case 0x00170: /* vram cycle: transfer delay */ 441 case 0x00200: /* vram cycle: mask register */ 442 /* ignore */ 443 break; 444 case REG_TOP: 445 s->top_of_screen = val; 446 g364fb_invalidate_display(s); 447 break; 448 case REG_DISPLAY: 449 s->width = val * 4; 450 break; 451 case REG_VDISPLAY: 452 s->height = val / 2; 453 break; 454 case REG_CTLA: 455 s->ctla = val; 456 g364fb_update_depth(s); 457 g364fb_invalidate_display(s); 458 break; 459 case REG_CURS_POS: 460 g364_invalidate_cursor_position(s); 461 s->cursor_position = val; 462 g364_invalidate_cursor_position(s); 463 break; 464 case REG_RESET: 465 g364fb_reset(s); 466 break; 467 default: 468 error_report("g364: invalid write of 0x%" PRIx64 469 " at [" TARGET_FMT_plx "]", val, addr); 470 break; 471 } 472 } 473 qemu_irq_lower(s->irq); 474 } 475 476 static const MemoryRegionOps g364fb_ctrl_ops = { 477 .read = g364fb_ctrl_read, 478 .write = g364fb_ctrl_write, 479 .endianness = DEVICE_LITTLE_ENDIAN, 480 .impl.min_access_size = 4, 481 .impl.max_access_size = 4, 482 }; 483 484 static int g364fb_post_load(void *opaque, int version_id) 485 { 486 G364State *s = opaque; 487 488 /* force refresh */ 489 g364fb_update_depth(s); 490 g364fb_invalidate_display(s); 491 492 return 0; 493 } 494 495 static const VMStateDescription vmstate_g364fb = { 496 .name = "g364fb", 497 .version_id = 1, 498 .minimum_version_id = 1, 499 .minimum_version_id_old = 1, 500 .post_load = g364fb_post_load, 501 .fields = (VMStateField[]) { 502 VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size), 503 VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3), 504 VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9), 505 VMSTATE_UINT16_ARRAY(cursor, G364State, 512), 506 VMSTATE_UINT32(cursor_position, G364State), 507 VMSTATE_UINT32(ctla, G364State), 508 VMSTATE_UINT32(top_of_screen, G364State), 509 VMSTATE_UINT32(width, G364State), 510 VMSTATE_UINT32(height, G364State), 511 VMSTATE_END_OF_LIST() 512 } 513 }; 514 515 static void g364fb_init(DeviceState *dev, G364State *s) 516 { 517 s->vram = g_malloc0(s->vram_size); 518 519 s->ds = graphic_console_init(g364fb_update_display, 520 g364fb_invalidate_display, 521 g364fb_screen_dump, NULL, s); 522 523 memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000); 524 memory_region_init_ram_ptr(&s->mem_vram, "vram", 525 s->vram_size, s->vram); 526 vmstate_register_ram(&s->mem_vram, dev); 527 memory_region_set_coalescing(&s->mem_vram); 528 } 529 530 typedef struct { 531 SysBusDevice busdev; 532 G364State g364; 533 } G364SysBusState; 534 535 static int g364fb_sysbus_init(SysBusDevice *dev) 536 { 537 G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364; 538 539 g364fb_init(&dev->qdev, s); 540 sysbus_init_irq(dev, &s->irq); 541 sysbus_init_mmio(dev, &s->mem_ctrl); 542 sysbus_init_mmio(dev, &s->mem_vram); 543 544 return 0; 545 } 546 547 static void g364fb_sysbus_reset(DeviceState *d) 548 { 549 G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d); 550 g364fb_reset(&s->g364); 551 } 552 553 static Property g364fb_sysbus_properties[] = { 554 DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size, 555 8 * 1024 * 1024), 556 DEFINE_PROP_END_OF_LIST(), 557 }; 558 559 static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) 560 { 561 DeviceClass *dc = DEVICE_CLASS(klass); 562 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 563 564 k->init = g364fb_sysbus_init; 565 dc->desc = "G364 framebuffer"; 566 dc->reset = g364fb_sysbus_reset; 567 dc->vmsd = &vmstate_g364fb; 568 dc->props = g364fb_sysbus_properties; 569 } 570 571 static TypeInfo g364fb_sysbus_info = { 572 .name = "sysbus-g364", 573 .parent = TYPE_SYS_BUS_DEVICE, 574 .instance_size = sizeof(G364SysBusState), 575 .class_init = g364fb_sysbus_class_init, 576 }; 577 578 static void g364fb_register_types(void) 579 { 580 type_register_static(&g364fb_sysbus_info); 581 } 582 583 type_init(g364fb_register_types) 584