1 /* 2 * Samsung exynos4210 Display Controller (FIMD) 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * Based on LCD controller for Samsung S5PC1xx-based board emulation 7 * by Kirill Batuzov <batuzovk@ispras.ru> 8 * 9 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu-common.h" 26 #include "hw/sysbus.h" 27 #include "ui/console.h" 28 #include "ui/pixel_ops.h" 29 #include "qemu/bswap.h" 30 31 /* Debug messages configuration */ 32 #define EXYNOS4210_FIMD_DEBUG 0 33 #define EXYNOS4210_FIMD_MODE_TRACE 0 34 35 #if EXYNOS4210_FIMD_DEBUG == 0 36 #define DPRINT_L1(fmt, args...) do { } while (0) 37 #define DPRINT_L2(fmt, args...) do { } while (0) 38 #define DPRINT_ERROR(fmt, args...) do { } while (0) 39 #elif EXYNOS4210_FIMD_DEBUG == 1 40 #define DPRINT_L1(fmt, args...) \ 41 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 42 #define DPRINT_L2(fmt, args...) do { } while (0) 43 #define DPRINT_ERROR(fmt, args...) \ 44 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0) 45 #else 46 #define DPRINT_L1(fmt, args...) \ 47 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 48 #define DPRINT_L2(fmt, args...) \ 49 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 50 #define DPRINT_ERROR(fmt, args...) \ 51 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0) 52 #endif 53 54 #if EXYNOS4210_FIMD_MODE_TRACE == 0 55 #define DPRINT_TRACE(fmt, args...) do { } while (0) 56 #else 57 #define DPRINT_TRACE(fmt, args...) \ 58 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 59 #endif 60 61 #define NUM_OF_WINDOWS 5 62 #define FIMD_REGS_SIZE 0x4114 63 64 /* Video main control registers */ 65 #define FIMD_VIDCON0 0x0000 66 #define FIMD_VIDCON1 0x0004 67 #define FIMD_VIDCON2 0x0008 68 #define FIMD_VIDCON3 0x000C 69 #define FIMD_VIDCON0_ENVID_F (1 << 0) 70 #define FIMD_VIDCON0_ENVID (1 << 1) 71 #define FIMD_VIDCON0_ENVID_MASK ((1 << 0) | (1 << 1)) 72 #define FIMD_VIDCON1_ROMASK 0x07FFE000 73 74 /* Video time control registers */ 75 #define FIMD_VIDTCON_START 0x10 76 #define FIMD_VIDTCON_END 0x1C 77 #define FIMD_VIDTCON2_SIZE_MASK 0x07FF 78 #define FIMD_VIDTCON2_HOR_SHIFT 0 79 #define FIMD_VIDTCON2_VER_SHIFT 11 80 81 /* Window control registers */ 82 #define FIMD_WINCON_START 0x0020 83 #define FIMD_WINCON_END 0x0030 84 #define FIMD_WINCON_ROMASK 0x82200000 85 #define FIMD_WINCON_ENWIN (1 << 0) 86 #define FIMD_WINCON_BLD_PIX (1 << 6) 87 #define FIMD_WINCON_ALPHA_MUL (1 << 7) 88 #define FIMD_WINCON_ALPHA_SEL (1 << 1) 89 #define FIMD_WINCON_SWAP 0x078000 90 #define FIMD_WINCON_SWAP_SHIFT 15 91 #define FIMD_WINCON_SWAP_WORD 0x1 92 #define FIMD_WINCON_SWAP_HWORD 0x2 93 #define FIMD_WINCON_SWAP_BYTE 0x4 94 #define FIMD_WINCON_SWAP_BITS 0x8 95 #define FIMD_WINCON_BUFSTAT_L (1 << 21) 96 #define FIMD_WINCON_BUFSTAT_H (1 << 31) 97 #define FIMD_WINCON_BUFSTATUS ((1 << 21) | (1 << 31)) 98 #define FIMD_WINCON_BUF0_STAT ((0 << 21) | (0 << 31)) 99 #define FIMD_WINCON_BUF1_STAT ((1 << 21) | (0 << 31)) 100 #define FIMD_WINCON_BUF2_STAT ((0 << 21) | (1 << 31)) 101 #define FIMD_WINCON_BUFSELECT ((1 << 20) | (1 << 30)) 102 #define FIMD_WINCON_BUF0_SEL ((0 << 20) | (0 << 30)) 103 #define FIMD_WINCON_BUF1_SEL ((1 << 20) | (0 << 30)) 104 #define FIMD_WINCON_BUF2_SEL ((0 << 20) | (1 << 30)) 105 #define FIMD_WINCON_BUFMODE (1 << 14) 106 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC) 107 #define PAL_MODE_WITH_ALPHA(x) ((x) == 7) 108 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF) 109 #define WIN_BPP_MODE_WITH_ALPHA(w) \ 110 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE) 111 112 /* Shadow control register */ 113 #define FIMD_SHADOWCON 0x0034 114 #define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w)))) 115 /* Channel mapping control register */ 116 #define FIMD_WINCHMAP 0x003C 117 118 /* Window position control registers */ 119 #define FIMD_VIDOSD_START 0x0040 120 #define FIMD_VIDOSD_END 0x0088 121 #define FIMD_VIDOSD_COORD_MASK 0x07FF 122 #define FIMD_VIDOSD_HOR_SHIFT 11 123 #define FIMD_VIDOSD_VER_SHIFT 0 124 #define FIMD_VIDOSD_ALPHA_AEN0 0xFFF000 125 #define FIMD_VIDOSD_AEN0_SHIFT 12 126 #define FIMD_VIDOSD_ALPHA_AEN1 0x000FFF 127 128 /* Frame buffer address registers */ 129 #define FIMD_VIDWADD0_START 0x00A0 130 #define FIMD_VIDWADD0_END 0x00C4 131 #define FIMD_VIDWADD0_END 0x00C4 132 #define FIMD_VIDWADD1_START 0x00D0 133 #define FIMD_VIDWADD1_END 0x00F4 134 #define FIMD_VIDWADD2_START 0x0100 135 #define FIMD_VIDWADD2_END 0x0110 136 #define FIMD_VIDWADD2_PAGEWIDTH 0x1FFF 137 #define FIMD_VIDWADD2_OFFSIZE 0x1FFF 138 #define FIMD_VIDWADD2_OFFSIZE_SHIFT 13 139 #define FIMD_VIDW0ADD0_B2 0x20A0 140 #define FIMD_VIDW4ADD0_B2 0x20C0 141 142 /* Video interrupt control registers */ 143 #define FIMD_VIDINTCON0 0x130 144 #define FIMD_VIDINTCON1 0x134 145 146 /* Window color key registers */ 147 #define FIMD_WKEYCON_START 0x140 148 #define FIMD_WKEYCON_END 0x15C 149 #define FIMD_WKEYCON0_COMPKEY 0x00FFFFFF 150 #define FIMD_WKEYCON0_CTL_SHIFT 24 151 #define FIMD_WKEYCON0_DIRCON (1 << 24) 152 #define FIMD_WKEYCON0_KEYEN (1 << 25) 153 #define FIMD_WKEYCON0_KEYBLEN (1 << 26) 154 /* Window color key alpha control register */ 155 #define FIMD_WKEYALPHA_START 0x160 156 #define FIMD_WKEYALPHA_END 0x16C 157 158 /* Dithering control register */ 159 #define FIMD_DITHMODE 0x170 160 161 /* Window alpha control registers */ 162 #define FIMD_VIDALPHA_ALPHA_LOWER 0x000F0F0F 163 #define FIMD_VIDALPHA_ALPHA_UPPER 0x00F0F0F0 164 #define FIMD_VIDWALPHA_START 0x21C 165 #define FIMD_VIDWALPHA_END 0x240 166 167 /* Window color map registers */ 168 #define FIMD_WINMAP_START 0x180 169 #define FIMD_WINMAP_END 0x190 170 #define FIMD_WINMAP_EN (1 << 24) 171 #define FIMD_WINMAP_COLOR_MASK 0x00FFFFFF 172 173 /* Window palette control registers */ 174 #define FIMD_WPALCON_HIGH 0x019C 175 #define FIMD_WPALCON_LOW 0x01A0 176 #define FIMD_WPALCON_UPDATEEN (1 << 9) 177 #define FIMD_WPAL_W0PAL_L 0x07 178 #define FIMD_WPAL_W0PAL_L_SHT 0 179 #define FIMD_WPAL_W1PAL_L 0x07 180 #define FIMD_WPAL_W1PAL_L_SHT 3 181 #define FIMD_WPAL_W2PAL_L 0x01 182 #define FIMD_WPAL_W2PAL_L_SHT 6 183 #define FIMD_WPAL_W2PAL_H 0x06 184 #define FIMD_WPAL_W2PAL_H_SHT 8 185 #define FIMD_WPAL_W3PAL_L 0x01 186 #define FIMD_WPAL_W3PAL_L_SHT 7 187 #define FIMD_WPAL_W3PAL_H 0x06 188 #define FIMD_WPAL_W3PAL_H_SHT 12 189 #define FIMD_WPAL_W4PAL_L 0x01 190 #define FIMD_WPAL_W4PAL_L_SHT 8 191 #define FIMD_WPAL_W4PAL_H 0x06 192 #define FIMD_WPAL_W4PAL_H_SHT 16 193 194 /* Trigger control registers */ 195 #define FIMD_TRIGCON 0x01A4 196 #define FIMD_TRIGCON_ROMASK 0x00000004 197 198 /* LCD I80 Interface Control */ 199 #define FIMD_I80IFCON_START 0x01B0 200 #define FIMD_I80IFCON_END 0x01BC 201 /* Color gain control register */ 202 #define FIMD_COLORGAINCON 0x01C0 203 /* LCD i80 Interface Command Control */ 204 #define FIMD_LDI_CMDCON0 0x01D0 205 #define FIMD_LDI_CMDCON1 0x01D4 206 /* I80 System Interface Manual Command Control */ 207 #define FIMD_SIFCCON0 0x01E0 208 #define FIMD_SIFCCON2 0x01E8 209 210 /* Hue Control Registers */ 211 #define FIMD_HUECOEFCR_START 0x01EC 212 #define FIMD_HUECOEFCR_END 0x01F4 213 #define FIMD_HUECOEFCB_START 0x01FC 214 #define FIMD_HUECOEFCB_END 0x0208 215 #define FIMD_HUEOFFSET 0x020C 216 217 /* Video interrupt control registers */ 218 #define FIMD_VIDINT_INTFIFOPEND (1 << 0) 219 #define FIMD_VIDINT_INTFRMPEND (1 << 1) 220 #define FIMD_VIDINT_INTI80PEND (1 << 2) 221 #define FIMD_VIDINT_INTEN (1 << 0) 222 #define FIMD_VIDINT_INTFIFOEN (1 << 1) 223 #define FIMD_VIDINT_INTFRMEN (1 << 12) 224 #define FIMD_VIDINT_I80IFDONE (1 << 17) 225 226 /* Window blend equation control registers */ 227 #define FIMD_BLENDEQ_START 0x0244 228 #define FIMD_BLENDEQ_END 0x0250 229 #define FIMD_BLENDCON 0x0260 230 #define FIMD_ALPHA_8BIT (1 << 0) 231 #define FIMD_BLENDEQ_COEF_MASK 0xF 232 233 /* Window RTQOS Control Registers */ 234 #define FIMD_WRTQOSCON_START 0x0264 235 #define FIMD_WRTQOSCON_END 0x0274 236 237 /* LCD I80 Interface Command */ 238 #define FIMD_I80IFCMD_START 0x0280 239 #define FIMD_I80IFCMD_END 0x02AC 240 241 /* Shadow windows control registers */ 242 #define FIMD_SHD_ADD0_START 0x40A0 243 #define FIMD_SHD_ADD0_END 0x40C0 244 #define FIMD_SHD_ADD1_START 0x40D0 245 #define FIMD_SHD_ADD1_END 0x40F0 246 #define FIMD_SHD_ADD2_START 0x4100 247 #define FIMD_SHD_ADD2_END 0x4110 248 249 /* Palette memory */ 250 #define FIMD_PAL_MEM_START 0x2400 251 #define FIMD_PAL_MEM_END 0x37FC 252 /* Palette memory aliases for windows 0 and 1 */ 253 #define FIMD_PALMEM_AL_START 0x0400 254 #define FIMD_PALMEM_AL_END 0x0BFC 255 256 typedef struct { 257 uint8_t r, g, b; 258 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */ 259 uint32_t a; 260 } rgba; 261 #define RGBA_SIZE 7 262 263 typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p); 264 typedef struct Exynos4210fimdWindow Exynos4210fimdWindow; 265 266 struct Exynos4210fimdWindow { 267 uint32_t wincon; /* Window control register */ 268 uint32_t buf_start[3]; /* Start address for video frame buffer */ 269 uint32_t buf_end[3]; /* End address for video frame buffer */ 270 uint32_t keycon[2]; /* Window color key registers */ 271 uint32_t keyalpha; /* Color key alpha control register */ 272 uint32_t winmap; /* Window color map register */ 273 uint32_t blendeq; /* Window blending equation control register */ 274 uint32_t rtqoscon; /* Window RTQOS Control Registers */ 275 uint32_t palette[256]; /* Palette RAM */ 276 uint32_t shadow_buf_start; /* Start address of shadow frame buffer */ 277 uint32_t shadow_buf_end; /* End address of shadow frame buffer */ 278 uint32_t shadow_buf_size; /* Virtual shadow screen width */ 279 280 pixel_to_rgb_func *pixel_to_rgb; 281 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst, 282 bool blend); 283 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a); 284 uint16_t lefttop_x, lefttop_y; /* VIDOSD0 register */ 285 uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */ 286 uint32_t osdsize; /* VIDOSD2&3 register */ 287 uint32_t alpha_val[2]; /* VIDOSD2&3, VIDWALPHA registers */ 288 uint16_t virtpage_width; /* VIDWADD2 register */ 289 uint16_t virtpage_offsize; /* VIDWADD2 register */ 290 MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */ 291 uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */ 292 hwaddr fb_len; /* Framebuffer length */ 293 }; 294 295 typedef struct { 296 SysBusDevice busdev; 297 MemoryRegion iomem; 298 QemuConsole *console; 299 qemu_irq irq[3]; 300 301 uint32_t vidcon[4]; /* Video main control registers 0-3 */ 302 uint32_t vidtcon[4]; /* Video time control registers 0-3 */ 303 uint32_t shadowcon; /* Window shadow control register */ 304 uint32_t winchmap; /* Channel mapping control register */ 305 uint32_t vidintcon[2]; /* Video interrupt control registers */ 306 uint32_t dithmode; /* Dithering control register */ 307 uint32_t wpalcon[2]; /* Window palette control registers */ 308 uint32_t trigcon; /* Trigger control register */ 309 uint32_t i80ifcon[4]; /* I80 interface control registers */ 310 uint32_t colorgaincon; /* Color gain control register */ 311 uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */ 312 uint32_t sifccon[3]; /* I80 System Interface Manual Command Control */ 313 uint32_t huecoef_cr[4]; /* Hue control registers */ 314 uint32_t huecoef_cb[4]; /* Hue control registers */ 315 uint32_t hueoffset; /* Hue offset control register */ 316 uint32_t blendcon; /* Blending control register */ 317 uint32_t i80ifcmd[12]; /* LCD I80 Interface Command */ 318 319 Exynos4210fimdWindow window[5]; /* Window-specific registers */ 320 uint8_t *ifb; /* Internal frame buffer */ 321 bool invalidate; /* Image needs to be redrawn */ 322 bool enabled; /* Display controller is enabled */ 323 } Exynos4210fimdState; 324 325 /* Perform byte/halfword/word swap of data according to WINCON */ 326 static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data) 327 { 328 int i; 329 uint64_t res; 330 uint64_t x = *data; 331 332 if (swap_ctl & FIMD_WINCON_SWAP_BITS) { 333 res = 0; 334 for (i = 0; i < 64; i++) { 335 if (x & (1ULL << (64 - i))) { 336 res |= (1ULL << i); 337 } 338 } 339 x = res; 340 } 341 342 if (swap_ctl & FIMD_WINCON_SWAP_BYTE) { 343 x = bswap64(x); 344 } 345 346 if (swap_ctl & FIMD_WINCON_SWAP_HWORD) { 347 x = ((x & 0x000000000000FFFFULL) << 48) | 348 ((x & 0x00000000FFFF0000ULL) << 16) | 349 ((x & 0x0000FFFF00000000ULL) >> 16) | 350 ((x & 0xFFFF000000000000ULL) >> 48); 351 } 352 353 if (swap_ctl & FIMD_WINCON_SWAP_WORD) { 354 x = ((x & 0x00000000FFFFFFFFULL) << 32) | 355 ((x & 0xFFFFFFFF00000000ULL) >> 32); 356 } 357 358 *data = x; 359 } 360 361 /* Conversion routines of Pixel data from frame buffer area to internal RGBA 362 * pixel representation. 363 * Every color component internally represented as 8-bit value. If original 364 * data has less than 8 bit for component, data is extended to 8 bit. For 365 * example, if blue component has only two possible values 0 and 1 it will be 366 * extended to 0 and 0xFF */ 367 368 /* One bit for alpha representation */ 369 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \ 370 static void N(uint32_t pixel, rgba *p) \ 371 { \ 372 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \ 373 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \ 374 pixel >>= (B); \ 375 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \ 376 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \ 377 pixel >>= (G); \ 378 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \ 379 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \ 380 pixel >>= (R); \ 381 p->a = (pixel & 0x1); \ 382 } 383 384 DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4) 385 DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5) 386 DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6) 387 DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5) 388 DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8) 389 DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7) 390 391 /* Alpha component is always zero */ 392 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \ 393 static void N(uint32_t pixel, rgba *p) \ 394 { \ 395 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \ 396 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \ 397 pixel >>= (B); \ 398 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \ 399 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \ 400 pixel >>= (G); \ 401 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \ 402 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \ 403 p->a = 0x0; \ 404 } 405 406 DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb, 5, 6, 5) 407 DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb, 5, 5, 5) 408 DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb, 6, 6, 6) 409 DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb, 8, 8, 8) 410 411 /* Alpha component has some meaningful value */ 412 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \ 413 static void N(uint32_t pixel, rgba *p) \ 414 { \ 415 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \ 416 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \ 417 pixel >>= (B); \ 418 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \ 419 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \ 420 pixel >>= (G); \ 421 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \ 422 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \ 423 pixel >>= (R); \ 424 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \ 425 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \ 426 p->a = p->a | (p->a << 8) | (p->a << 16); \ 427 } 428 429 DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4) 430 DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8) 431 432 /* Lookup table to extent 2-bit color component to 8 bit */ 433 static const uint8_t pixel_lutable_2b[4] = { 434 0x0, 0x55, 0xAA, 0xFF 435 }; 436 /* Lookup table to extent 3-bit color component to 8 bit */ 437 static const uint8_t pixel_lutable_3b[8] = { 438 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF 439 }; 440 /* Special case for a232 bpp mode */ 441 static void pixel_a232_to_rgb(uint32_t pixel, rgba *p) 442 { 443 p->b = pixel_lutable_2b[(pixel & 0x3)]; 444 pixel >>= 2; 445 p->g = pixel_lutable_3b[(pixel & 0x7)]; 446 pixel >>= 3; 447 p->r = pixel_lutable_2b[(pixel & 0x3)]; 448 pixel >>= 2; 449 p->a = (pixel & 0x1); 450 } 451 452 /* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB 453 * for all three color components */ 454 static void pixel_1555_to_rgb(uint32_t pixel, rgba *p) 455 { 456 uint8_t comm = (pixel >> 15) & 1; 457 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); 458 pixel >>= 5; 459 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); 460 pixel >>= 5; 461 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); 462 p->a = 0x0; 463 } 464 465 /* Put/get pixel to/from internal LCD Controller framebuffer */ 466 467 static int put_pixel_ifb(const rgba p, uint8_t *d) 468 { 469 *(uint8_t *)d++ = p.r; 470 *(uint8_t *)d++ = p.g; 471 *(uint8_t *)d++ = p.b; 472 *(uint32_t *)d = p.a; 473 return RGBA_SIZE; 474 } 475 476 static int get_pixel_ifb(const uint8_t *s, rgba *p) 477 { 478 p->r = *(uint8_t *)s++; 479 p->g = *(uint8_t *)s++; 480 p->b = *(uint8_t *)s++; 481 p->a = (*(uint32_t *)s) & 0x00FFFFFF; 482 return RGBA_SIZE; 483 } 484 485 static pixel_to_rgb_func *palette_data_format[8] = { 486 [0] = pixel_565_to_rgb, 487 [1] = pixel_a555_to_rgb, 488 [2] = pixel_666_to_rgb, 489 [3] = pixel_a665_to_rgb, 490 [4] = pixel_a666_to_rgb, 491 [5] = pixel_888_to_rgb, 492 [6] = pixel_a888_to_rgb, 493 [7] = pixel_8888_to_rgb 494 }; 495 496 /* Returns Index in palette data formats table for given window number WINDOW */ 497 static uint32_t 498 exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window) 499 { 500 uint32_t ret; 501 502 switch (window) { 503 case 0: 504 ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT) & FIMD_WPAL_W0PAL_L; 505 if (ret != 7) { 506 ret = 6 - ret; 507 } 508 break; 509 case 1: 510 ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT) & FIMD_WPAL_W1PAL_L; 511 if (ret != 7) { 512 ret = 6 - ret; 513 } 514 break; 515 case 2: 516 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT) & FIMD_WPAL_W2PAL_H) | 517 ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT) & FIMD_WPAL_W2PAL_L); 518 break; 519 case 3: 520 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT) & FIMD_WPAL_W3PAL_H) | 521 ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT) & FIMD_WPAL_W3PAL_L); 522 break; 523 case 4: 524 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT) & FIMD_WPAL_W4PAL_H) | 525 ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT) & FIMD_WPAL_W4PAL_L); 526 break; 527 default: 528 hw_error("exynos4210.fimd: incorrect window number %d\n", window); 529 ret = 0; 530 break; 531 } 532 return ret; 533 } 534 535 #define FIMD_1_MINUS_COLOR(x) \ 536 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \ 537 (0xFF0000 - ((x) & 0xFF0000))) 538 #define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0)) 539 #define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F)) 540 541 /* Multiply three lower bytes of two 32-bit words with each other. 542 * Each byte with values 0-255 is considered as a number with possible values 543 * in a range [0 - 1] */ 544 static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b) 545 { 546 uint32_t tmp; 547 uint32_t ret; 548 549 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp; 550 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 551 0xFF00 : tmp << 8; 552 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ? 553 0xFF0000 : tmp << 16; 554 return ret; 555 } 556 557 /* For each corresponding bytes of two 32-bit words: (a*b + c*d) 558 * Byte values 0-255 are mapped to a range [0 .. 1] */ 559 static inline uint32_t 560 fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d) 561 { 562 uint32_t tmp; 563 uint32_t ret; 564 565 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF)) 566 > 0xFF) ? 0xFF : tmp; 567 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) * 568 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8; 569 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) + 570 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ? 571 0xFF0000 : tmp << 16; 572 return ret; 573 } 574 575 /* These routines cover all possible sources of window's transparent factor 576 * used in blending equation. Choice of routine is affected by WPALCON 577 * registers, BLENDCON register and window's WINCON register */ 578 579 static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a) 580 { 581 return pix_a; 582 } 583 584 static uint32_t 585 fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a) 586 { 587 return EXTEND_LOWER_HALFBYTE(pix_a); 588 } 589 590 static uint32_t 591 fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a) 592 { 593 return EXTEND_UPPER_HALFBYTE(pix_a); 594 } 595 596 static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a) 597 { 598 return fimd_mult_each_byte(pix_a, w->alpha_val[0]); 599 } 600 601 static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a) 602 { 603 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a), 604 EXTEND_UPPER_HALFBYTE(w->alpha_val[0])); 605 } 606 607 static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a) 608 { 609 return w->alpha_val[pix_a]; 610 } 611 612 static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a) 613 { 614 return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a]); 615 } 616 617 static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a) 618 { 619 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL) ? 1 : 0]; 620 } 621 622 static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a) 623 { 624 return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon & 625 FIMD_WINCON_ALPHA_SEL) ? 1 : 0]); 626 } 627 628 /* Updates currently active alpha value get function for specified window */ 629 static void fimd_update_get_alpha(Exynos4210fimdState *s, int win) 630 { 631 Exynos4210fimdWindow *w = &s->window[win]; 632 const bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT; 633 634 if (w->wincon & FIMD_WINCON_BLD_PIX) { 635 if ((w->wincon & FIMD_WINCON_ALPHA_SEL) && WIN_BPP_MODE_WITH_ALPHA(w)) { 636 /* In this case, alpha component contains meaningful value */ 637 if (w->wincon & FIMD_WINCON_ALPHA_MUL) { 638 w->get_alpha = alpha_is_8bit ? 639 fimd_get_alpha_mult : fimd_get_alpha_mult_ext; 640 } else { 641 w->get_alpha = alpha_is_8bit ? 642 fimd_get_alpha_pix : fimd_get_alpha_pix_extlow; 643 } 644 } else { 645 if (IS_PALETTIZED_MODE(w) && 646 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))) { 647 /* Alpha component has 8-bit numeric value */ 648 w->get_alpha = alpha_is_8bit ? 649 fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh; 650 } else { 651 /* Alpha has only two possible values (AEN) */ 652 w->get_alpha = alpha_is_8bit ? 653 fimd_get_alpha_aen : fimd_get_alpha_aen_ext; 654 } 655 } 656 } else { 657 w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel : 658 fimd_get_alpha_sel_ext; 659 } 660 } 661 662 /* Blends current window's (w) pixel (foreground pixel *ret) with background 663 * window (w_blend) pixel p_bg according to formula: 664 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR 665 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA 666 */ 667 static void 668 exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret) 669 { 670 rgba p_fg = *ret; 671 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) | 672 (p_bg.b & 0xFF); 673 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) | 674 (p_fg.b & 0xFF); 675 uint32_t alpha_fg = p_fg.a; 676 int i; 677 /* It is possible that blending equation parameters a and b do not 678 * depend on window BLENEQ register. Account for this with first_coef */ 679 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4}; 680 uint32_t first_coef = A_COEF; 681 uint32_t blend_param[COEF_NUM]; 682 683 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN) { 684 uint32_t colorkey = (w->keycon[1] & 685 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) & FIMD_WKEYCON0_COMPKEY; 686 687 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) && 688 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) { 689 /* Foreground pixel is displayed */ 690 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) { 691 alpha_fg = w->keyalpha; 692 blend_param[A_COEF] = alpha_fg; 693 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg); 694 } else { 695 alpha_fg = 0; 696 blend_param[A_COEF] = 0xFFFFFF; 697 blend_param[B_COEF] = 0x0; 698 } 699 first_coef = P_COEF; 700 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) == 0 && 701 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) { 702 /* Background pixel is displayed */ 703 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) { 704 alpha_fg = w->keyalpha; 705 blend_param[A_COEF] = alpha_fg; 706 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg); 707 } else { 708 alpha_fg = 0; 709 blend_param[A_COEF] = 0x0; 710 blend_param[B_COEF] = 0xFFFFFF; 711 } 712 first_coef = P_COEF; 713 } 714 } 715 716 for (i = first_coef; i < COEF_NUM; i++) { 717 switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK) { 718 case 0: 719 blend_param[i] = 0; 720 break; 721 case 1: 722 blend_param[i] = 0xFFFFFF; 723 break; 724 case 2: 725 blend_param[i] = alpha_fg; 726 break; 727 case 3: 728 blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg); 729 break; 730 case 4: 731 blend_param[i] = p_bg.a; 732 break; 733 case 5: 734 blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a); 735 break; 736 case 6: 737 blend_param[i] = w->alpha_val[0]; 738 break; 739 case 10: 740 blend_param[i] = fg_color; 741 break; 742 case 11: 743 blend_param[i] = FIMD_1_MINUS_COLOR(fg_color); 744 break; 745 case 12: 746 blend_param[i] = bg_color; 747 break; 748 case 13: 749 blend_param[i] = FIMD_1_MINUS_COLOR(bg_color); 750 break; 751 default: 752 hw_error("exynos4210.fimd: blend equation coef illegal value\n"); 753 break; 754 } 755 } 756 757 fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF], 758 fg_color, blend_param[A_COEF]); 759 ret->b = fg_color & 0xFF; 760 fg_color >>= 8; 761 ret->g = fg_color & 0xFF; 762 fg_color >>= 8; 763 ret->r = fg_color & 0xFF; 764 ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF], 765 p_bg.a, blend_param[Q_COEF]); 766 } 767 768 /* These routines read data from video frame buffer in system RAM, convert 769 * this data to display controller internal representation, if necessary, 770 * perform pixel blending with data, currently presented in internal buffer. 771 * Result is stored in display controller internal frame buffer. */ 772 773 /* Draw line with index in palette table in RAM frame buffer data */ 774 #define DEF_DRAW_LINE_PALETTE(N) \ 775 static void glue(draw_line_palette_, N)(Exynos4210fimdWindow *w, uint8_t *src, \ 776 uint8_t *dst, bool blend) \ 777 { \ 778 int width = w->rightbot_x - w->lefttop_x + 1; \ 779 uint8_t *ifb = dst; \ 780 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \ 781 uint64_t data; \ 782 rgba p, p_old; \ 783 int i; \ 784 do { \ 785 memcpy(&data, src, sizeof(data)); \ 786 src += 8; \ 787 fimd_swap_data(swap, &data); \ 788 for (i = (64 / (N) - 1); i >= 0; i--) { \ 789 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \ 790 ((1ULL << (N)) - 1)], &p); \ 791 p.a = w->get_alpha(w, p.a); \ 792 if (blend) { \ 793 ifb += get_pixel_ifb(ifb, &p_old); \ 794 exynos4210_fimd_blend_pixel(w, p_old, &p); \ 795 } \ 796 dst += put_pixel_ifb(p, dst); \ 797 } \ 798 width -= (64 / (N)); \ 799 } while (width > 0); \ 800 } 801 802 /* Draw line with direct color value in RAM frame buffer data */ 803 #define DEF_DRAW_LINE_NOPALETTE(N) \ 804 static void glue(draw_line_, N)(Exynos4210fimdWindow *w, uint8_t *src, \ 805 uint8_t *dst, bool blend) \ 806 { \ 807 int width = w->rightbot_x - w->lefttop_x + 1; \ 808 uint8_t *ifb = dst; \ 809 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \ 810 uint64_t data; \ 811 rgba p, p_old; \ 812 int i; \ 813 do { \ 814 memcpy(&data, src, sizeof(data)); \ 815 src += 8; \ 816 fimd_swap_data(swap, &data); \ 817 for (i = (64 / (N) - 1); i >= 0; i--) { \ 818 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \ 819 p.a = w->get_alpha(w, p.a); \ 820 if (blend) { \ 821 ifb += get_pixel_ifb(ifb, &p_old); \ 822 exynos4210_fimd_blend_pixel(w, p_old, &p); \ 823 } \ 824 dst += put_pixel_ifb(p, dst); \ 825 } \ 826 width -= (64 / (N)); \ 827 } while (width > 0); \ 828 } 829 830 DEF_DRAW_LINE_PALETTE(1) 831 DEF_DRAW_LINE_PALETTE(2) 832 DEF_DRAW_LINE_PALETTE(4) 833 DEF_DRAW_LINE_PALETTE(8) 834 DEF_DRAW_LINE_NOPALETTE(8) /* 8bpp mode has palette and non-palette versions */ 835 DEF_DRAW_LINE_NOPALETTE(16) 836 DEF_DRAW_LINE_NOPALETTE(32) 837 838 /* Special draw line routine for window color map case */ 839 static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src, 840 uint8_t *dst, bool blend) 841 { 842 rgba p, p_old; 843 uint8_t *ifb = dst; 844 int width = w->rightbot_x - w->lefttop_x + 1; 845 uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK; 846 847 do { 848 pixel_888_to_rgb(map_color, &p); 849 p.a = w->get_alpha(w, p.a); 850 if (blend) { 851 ifb += get_pixel_ifb(ifb, &p_old); 852 exynos4210_fimd_blend_pixel(w, p_old, &p); 853 } 854 dst += put_pixel_ifb(p, dst); 855 } while (--width); 856 } 857 858 /* Write RGB to QEMU's GraphicConsole framebuffer */ 859 860 static int put_to_qemufb_pixel8(const rgba p, uint8_t *d) 861 { 862 uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b); 863 *(uint8_t *)d = pixel; 864 return 1; 865 } 866 867 static int put_to_qemufb_pixel15(const rgba p, uint8_t *d) 868 { 869 uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b); 870 *(uint16_t *)d = pixel; 871 return 2; 872 } 873 874 static int put_to_qemufb_pixel16(const rgba p, uint8_t *d) 875 { 876 uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b); 877 *(uint16_t *)d = pixel; 878 return 2; 879 } 880 881 static int put_to_qemufb_pixel24(const rgba p, uint8_t *d) 882 { 883 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b); 884 *(uint8_t *)d++ = (pixel >> 0) & 0xFF; 885 *(uint8_t *)d++ = (pixel >> 8) & 0xFF; 886 *(uint8_t *)d++ = (pixel >> 16) & 0xFF; 887 return 3; 888 } 889 890 static int put_to_qemufb_pixel32(const rgba p, uint8_t *d) 891 { 892 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b); 893 *(uint32_t *)d = pixel; 894 return 4; 895 } 896 897 /* Routine to copy pixel from internal buffer to QEMU buffer */ 898 static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel); 899 static inline void fimd_update_putpix_qemu(int bpp) 900 { 901 switch (bpp) { 902 case 8: 903 put_pixel_toqemu = put_to_qemufb_pixel8; 904 break; 905 case 15: 906 put_pixel_toqemu = put_to_qemufb_pixel15; 907 break; 908 case 16: 909 put_pixel_toqemu = put_to_qemufb_pixel16; 910 break; 911 case 24: 912 put_pixel_toqemu = put_to_qemufb_pixel24; 913 break; 914 case 32: 915 put_pixel_toqemu = put_to_qemufb_pixel32; 916 break; 917 default: 918 hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp); 919 break; 920 } 921 } 922 923 /* Routine to copy a line from internal frame buffer to QEMU display */ 924 static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst) 925 { 926 rgba p; 927 928 do { 929 src += get_pixel_ifb(src, &p); 930 dst += put_pixel_toqemu(p, dst); 931 } while (--width); 932 } 933 934 /* Parse BPPMODE_F = WINCON1[5:2] bits */ 935 static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win) 936 { 937 Exynos4210fimdWindow *w = &s->window[win]; 938 939 if (w->winmap & FIMD_WINMAP_EN) { 940 w->draw_line = draw_line_mapcolor; 941 return; 942 } 943 944 switch (WIN_BPP_MODE(w)) { 945 case 0: 946 w->draw_line = draw_line_palette_1; 947 w->pixel_to_rgb = 948 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 949 break; 950 case 1: 951 w->draw_line = draw_line_palette_2; 952 w->pixel_to_rgb = 953 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 954 break; 955 case 2: 956 w->draw_line = draw_line_palette_4; 957 w->pixel_to_rgb = 958 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 959 break; 960 case 3: 961 w->draw_line = draw_line_palette_8; 962 w->pixel_to_rgb = 963 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 964 break; 965 case 4: 966 w->draw_line = draw_line_8; 967 w->pixel_to_rgb = pixel_a232_to_rgb; 968 break; 969 case 5: 970 w->draw_line = draw_line_16; 971 w->pixel_to_rgb = pixel_565_to_rgb; 972 break; 973 case 6: 974 w->draw_line = draw_line_16; 975 w->pixel_to_rgb = pixel_a555_to_rgb; 976 break; 977 case 7: 978 w->draw_line = draw_line_16; 979 w->pixel_to_rgb = pixel_1555_to_rgb; 980 break; 981 case 8: 982 w->draw_line = draw_line_32; 983 w->pixel_to_rgb = pixel_666_to_rgb; 984 break; 985 case 9: 986 w->draw_line = draw_line_32; 987 w->pixel_to_rgb = pixel_a665_to_rgb; 988 break; 989 case 10: 990 w->draw_line = draw_line_32; 991 w->pixel_to_rgb = pixel_a666_to_rgb; 992 break; 993 case 11: 994 w->draw_line = draw_line_32; 995 w->pixel_to_rgb = pixel_888_to_rgb; 996 break; 997 case 12: 998 w->draw_line = draw_line_32; 999 w->pixel_to_rgb = pixel_a887_to_rgb; 1000 break; 1001 case 13: 1002 w->draw_line = draw_line_32; 1003 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon & 1004 FIMD_WINCON_ALPHA_SEL)) { 1005 w->pixel_to_rgb = pixel_8888_to_rgb; 1006 } else { 1007 w->pixel_to_rgb = pixel_a888_to_rgb; 1008 } 1009 break; 1010 case 14: 1011 w->draw_line = draw_line_16; 1012 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon & 1013 FIMD_WINCON_ALPHA_SEL)) { 1014 w->pixel_to_rgb = pixel_4444_to_rgb; 1015 } else { 1016 w->pixel_to_rgb = pixel_a444_to_rgb; 1017 } 1018 break; 1019 case 15: 1020 w->draw_line = draw_line_16; 1021 w->pixel_to_rgb = pixel_555_to_rgb; 1022 break; 1023 } 1024 } 1025 1026 #if EXYNOS4210_FIMD_MODE_TRACE > 0 1027 static const char *exynos4210_fimd_get_bppmode(int mode_code) 1028 { 1029 switch (mode_code) { 1030 case 0: 1031 return "1 bpp"; 1032 case 1: 1033 return "2 bpp"; 1034 case 2: 1035 return "4 bpp"; 1036 case 3: 1037 return "8 bpp (palettized)"; 1038 case 4: 1039 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)"; 1040 case 5: 1041 return "16 bpp (non-palettized, R:5-G:6-B:5)"; 1042 case 6: 1043 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)"; 1044 case 7: 1045 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)"; 1046 case 8: 1047 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)"; 1048 case 9: 1049 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)"; 1050 case 10: 1051 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)"; 1052 case 11: 1053 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)"; 1054 case 12: 1055 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)"; 1056 case 13: 1057 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)"; 1058 case 14: 1059 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)"; 1060 case 15: 1061 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)"; 1062 default: 1063 return "Non-existing bpp mode"; 1064 } 1065 } 1066 1067 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s, 1068 int win_num, uint32_t val) 1069 { 1070 Exynos4210fimdWindow *w = &s->window[win_num]; 1071 1072 if (w->winmap & FIMD_WINMAP_EN) { 1073 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n", 1074 win_num, w->winmap & 0xFFFFFF); 1075 return; 1076 } 1077 1078 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) { 1079 return; 1080 } 1081 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num, 1082 exynos4210_fimd_get_bppmode((val >> 2) & 0xF)); 1083 } 1084 #else 1085 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s, 1086 int win_num, uint32_t val) 1087 { 1088 1089 } 1090 #endif 1091 1092 static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w) 1093 { 1094 switch (w->wincon & FIMD_WINCON_BUFSTATUS) { 1095 case FIMD_WINCON_BUF0_STAT: 1096 return 0; 1097 case FIMD_WINCON_BUF1_STAT: 1098 return 1; 1099 case FIMD_WINCON_BUF2_STAT: 1100 return 2; 1101 default: 1102 DPRINT_ERROR("Non-existent buffer index\n"); 1103 return 0; 1104 } 1105 } 1106 1107 /* Updates specified window's MemorySection based on values of WINCON, 1108 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */ 1109 static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win) 1110 { 1111 Exynos4210fimdWindow *w = &s->window[win]; 1112 hwaddr fb_start_addr, fb_mapped_len; 1113 1114 if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) || 1115 FIMD_WINDOW_PROTECTED(s->shadowcon, win)) { 1116 return; 1117 } 1118 1119 if (w->host_fb_addr) { 1120 cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0); 1121 w->host_fb_addr = NULL; 1122 w->fb_len = 0; 1123 } 1124 1125 fb_start_addr = w->buf_start[fimd_get_buffer_id(w)]; 1126 /* Total number of bytes of virtual screen used by current window */ 1127 w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) * 1128 (w->rightbot_y - w->lefttop_y + 1); 1129 w->mem_section = memory_region_find(sysbus_address_space(&s->busdev), 1130 fb_start_addr, w->fb_len); 1131 assert(w->mem_section.mr); 1132 assert(w->mem_section.offset_within_address_space == fb_start_addr); 1133 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n", 1134 win, fb_start_addr, w->fb_len); 1135 1136 if (w->mem_section.size != w->fb_len || 1137 !memory_region_is_ram(w->mem_section.mr)) { 1138 DPRINT_ERROR("Failed to find window %u framebuffer region\n", win); 1139 goto error_return; 1140 } 1141 1142 w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 0); 1143 if (!w->host_fb_addr) { 1144 DPRINT_ERROR("Failed to map window %u framebuffer\n", win); 1145 goto error_return; 1146 } 1147 1148 if (fb_mapped_len != w->fb_len) { 1149 DPRINT_ERROR("Window %u mapped framebuffer length is less then " 1150 "expected\n", win); 1151 cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0); 1152 goto error_return; 1153 } 1154 return; 1155 1156 error_return: 1157 w->mem_section.mr = NULL; 1158 w->mem_section.size = 0; 1159 w->host_fb_addr = NULL; 1160 w->fb_len = 0; 1161 } 1162 1163 static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool enabled) 1164 { 1165 if (enabled && !s->enabled) { 1166 unsigned w; 1167 s->enabled = true; 1168 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1169 fimd_update_memory_section(s, w); 1170 } 1171 } 1172 s->enabled = enabled; 1173 DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled"); 1174 } 1175 1176 static inline uint32_t unpack_upper_4(uint32_t x) 1177 { 1178 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4); 1179 } 1180 1181 static inline uint32_t pack_upper_4(uint32_t x) 1182 { 1183 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) | 1184 ((x & 0xF0) >> 4)) & 0xFFF; 1185 } 1186 1187 static void exynos4210_fimd_update_irq(Exynos4210fimdState *s) 1188 { 1189 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN)) { 1190 qemu_irq_lower(s->irq[0]); 1191 qemu_irq_lower(s->irq[1]); 1192 qemu_irq_lower(s->irq[2]); 1193 return; 1194 } 1195 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN) && 1196 (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND)) { 1197 qemu_irq_raise(s->irq[0]); 1198 } else { 1199 qemu_irq_lower(s->irq[0]); 1200 } 1201 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN) && 1202 (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND)) { 1203 qemu_irq_raise(s->irq[1]); 1204 } else { 1205 qemu_irq_lower(s->irq[1]); 1206 } 1207 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE) && 1208 (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND)) { 1209 qemu_irq_raise(s->irq[2]); 1210 } else { 1211 qemu_irq_lower(s->irq[2]); 1212 } 1213 } 1214 1215 static void exynos4210_fimd_invalidate(void *opaque) 1216 { 1217 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1218 s->invalidate = true; 1219 } 1220 1221 static void exynos4210_update_resolution(Exynos4210fimdState *s) 1222 { 1223 DisplaySurface *surface = qemu_console_surface(s->console); 1224 1225 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */ 1226 uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) & 1227 FIMD_VIDTCON2_SIZE_MASK) + 1; 1228 uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) & 1229 FIMD_VIDTCON2_SIZE_MASK) + 1; 1230 1231 if (s->ifb == NULL || surface_width(surface) != width || 1232 surface_height(surface) != height) { 1233 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n", 1234 surface_width(surface), surface_height(surface), width, height); 1235 qemu_console_resize(s->console, width, height); 1236 s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1); 1237 memset(s->ifb, 0, width * height * RGBA_SIZE + 1); 1238 exynos4210_fimd_invalidate(s); 1239 } 1240 } 1241 1242 static void exynos4210_fimd_update(void *opaque) 1243 { 1244 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1245 DisplaySurface *surface = qemu_console_surface(s->console); 1246 Exynos4210fimdWindow *w; 1247 int i, line; 1248 hwaddr fb_line_addr, inc_size; 1249 int scrn_height; 1250 int first_line = -1, last_line = -1, scrn_width; 1251 bool blend = false; 1252 uint8_t *host_fb_addr; 1253 bool is_dirty = false; 1254 const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; 1255 const int global_height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) & 1256 FIMD_VIDTCON2_SIZE_MASK) + 1; 1257 1258 if (!s || !s->console || !surface_bits_per_pixel(surface) || 1259 !s->enabled) { 1260 return; 1261 } 1262 exynos4210_update_resolution(s); 1263 1264 for (i = 0; i < NUM_OF_WINDOWS; i++) { 1265 w = &s->window[i]; 1266 if ((w->wincon & FIMD_WINCON_ENWIN) && w->host_fb_addr) { 1267 scrn_height = w->rightbot_y - w->lefttop_y + 1; 1268 scrn_width = w->virtpage_width; 1269 /* Total width of virtual screen page in bytes */ 1270 inc_size = scrn_width + w->virtpage_offsize; 1271 memory_region_sync_dirty_bitmap(w->mem_section.mr); 1272 host_fb_addr = w->host_fb_addr; 1273 fb_line_addr = w->mem_section.offset_within_region; 1274 1275 for (line = 0; line < scrn_height; line++) { 1276 is_dirty = memory_region_get_dirty(w->mem_section.mr, 1277 fb_line_addr, scrn_width, DIRTY_MEMORY_VGA); 1278 1279 if (s->invalidate || is_dirty) { 1280 if (first_line == -1) { 1281 first_line = line; 1282 } 1283 last_line = line; 1284 w->draw_line(w, host_fb_addr, s->ifb + 1285 w->lefttop_x * RGBA_SIZE + (w->lefttop_y + line) * 1286 global_width * RGBA_SIZE, blend); 1287 } 1288 host_fb_addr += inc_size; 1289 fb_line_addr += inc_size; 1290 is_dirty = false; 1291 } 1292 memory_region_reset_dirty(w->mem_section.mr, 1293 w->mem_section.offset_within_region, 1294 w->fb_len, DIRTY_MEMORY_VGA); 1295 blend = true; 1296 } 1297 } 1298 1299 /* Copy resulting image to QEMU_CONSOLE. */ 1300 if (first_line >= 0) { 1301 uint8_t *d; 1302 int bpp; 1303 1304 bpp = surface_bits_per_pixel(surface); 1305 fimd_update_putpix_qemu(bpp); 1306 bpp = (bpp + 1) >> 3; 1307 d = surface_data(surface); 1308 for (line = first_line; line <= last_line; line++) { 1309 fimd_copy_line_toqemu(global_width, s->ifb + global_width * line * 1310 RGBA_SIZE, d + global_width * line * bpp); 1311 } 1312 dpy_gfx_update(s->console, 0, 0, global_width, global_height); 1313 } 1314 s->invalidate = false; 1315 s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND; 1316 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) { 1317 exynos4210_fimd_enable(s, false); 1318 } 1319 exynos4210_fimd_update_irq(s); 1320 } 1321 1322 static void exynos4210_fimd_reset(DeviceState *d) 1323 { 1324 Exynos4210fimdState *s = DO_UPCAST(Exynos4210fimdState, busdev.qdev, d); 1325 unsigned w; 1326 1327 DPRINT_TRACE("Display controller reset\n"); 1328 /* Set all display controller registers to 0 */ 1329 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon); 1330 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1331 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow)); 1332 s->window[w].blendeq = 0xC2; 1333 exynos4210_fimd_update_win_bppmode(s, w); 1334 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF); 1335 fimd_update_get_alpha(s, w); 1336 } 1337 1338 if (s->ifb != NULL) { 1339 g_free(s->ifb); 1340 } 1341 s->ifb = NULL; 1342 1343 exynos4210_fimd_invalidate(s); 1344 exynos4210_fimd_enable(s, false); 1345 /* Some registers have non-zero initial values */ 1346 s->winchmap = 0x7D517D51; 1347 s->colorgaincon = 0x10040100; 1348 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100; 1349 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100; 1350 s->hueoffset = 0x01800080; 1351 } 1352 1353 static void exynos4210_fimd_write(void *opaque, hwaddr offset, 1354 uint64_t val, unsigned size) 1355 { 1356 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1357 unsigned w, i; 1358 uint32_t old_value; 1359 1360 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset, 1361 (long long unsigned int)val, (long long unsigned int)val); 1362 1363 switch (offset) { 1364 case FIMD_VIDCON0: 1365 if ((val & FIMD_VIDCON0_ENVID_MASK) == FIMD_VIDCON0_ENVID_MASK) { 1366 exynos4210_fimd_enable(s, true); 1367 } else { 1368 if ((val & FIMD_VIDCON0_ENVID) == 0) { 1369 exynos4210_fimd_enable(s, false); 1370 } 1371 } 1372 s->vidcon[0] = val; 1373 break; 1374 case FIMD_VIDCON1: 1375 /* Leave read-only bits as is */ 1376 val = (val & (~FIMD_VIDCON1_ROMASK)) | 1377 (s->vidcon[1] & FIMD_VIDCON1_ROMASK); 1378 s->vidcon[1] = val; 1379 break; 1380 case FIMD_VIDCON2 ... FIMD_VIDCON3: 1381 s->vidcon[(offset) >> 2] = val; 1382 break; 1383 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END: 1384 s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2] = val; 1385 break; 1386 case FIMD_WINCON_START ... FIMD_WINCON_END: 1387 w = (offset - FIMD_WINCON_START) >> 2; 1388 /* Window's current buffer ID */ 1389 i = fimd_get_buffer_id(&s->window[w]); 1390 old_value = s->window[w].wincon; 1391 val = (val & ~FIMD_WINCON_ROMASK) | 1392 (s->window[w].wincon & FIMD_WINCON_ROMASK); 1393 if (w == 0) { 1394 /* Window 0 wincon ALPHA_MUL bit must always be 0 */ 1395 val &= ~FIMD_WINCON_ALPHA_MUL; 1396 } 1397 exynos4210_fimd_trace_bppmode(s, w, val); 1398 switch (val & FIMD_WINCON_BUFSELECT) { 1399 case FIMD_WINCON_BUF0_SEL: 1400 val &= ~FIMD_WINCON_BUFSTATUS; 1401 break; 1402 case FIMD_WINCON_BUF1_SEL: 1403 val = (val & ~FIMD_WINCON_BUFSTAT_H) | FIMD_WINCON_BUFSTAT_L; 1404 break; 1405 case FIMD_WINCON_BUF2_SEL: 1406 if (val & FIMD_WINCON_BUFMODE) { 1407 val = (val & ~FIMD_WINCON_BUFSTAT_L) | FIMD_WINCON_BUFSTAT_H; 1408 } 1409 break; 1410 default: 1411 break; 1412 } 1413 s->window[w].wincon = val; 1414 exynos4210_fimd_update_win_bppmode(s, w); 1415 fimd_update_get_alpha(s, w); 1416 if ((i != fimd_get_buffer_id(&s->window[w])) || 1417 (!(old_value & FIMD_WINCON_ENWIN) && (s->window[w].wincon & 1418 FIMD_WINCON_ENWIN))) { 1419 fimd_update_memory_section(s, w); 1420 } 1421 break; 1422 case FIMD_SHADOWCON: 1423 old_value = s->shadowcon; 1424 s->shadowcon = val; 1425 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1426 if (FIMD_WINDOW_PROTECTED(old_value, w) && 1427 !FIMD_WINDOW_PROTECTED(s->shadowcon, w)) { 1428 fimd_update_memory_section(s, w); 1429 } 1430 } 1431 break; 1432 case FIMD_WINCHMAP: 1433 s->winchmap = val; 1434 break; 1435 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END: 1436 w = (offset - FIMD_VIDOSD_START) >> 4; 1437 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2; 1438 switch (i) { 1439 case 0: 1440 old_value = s->window[w].lefttop_y; 1441 s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT) & 1442 FIMD_VIDOSD_COORD_MASK; 1443 s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT) & 1444 FIMD_VIDOSD_COORD_MASK; 1445 if (s->window[w].lefttop_y != old_value) { 1446 fimd_update_memory_section(s, w); 1447 } 1448 break; 1449 case 1: 1450 old_value = s->window[w].rightbot_y; 1451 s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT) & 1452 FIMD_VIDOSD_COORD_MASK; 1453 s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT) & 1454 FIMD_VIDOSD_COORD_MASK; 1455 if (s->window[w].rightbot_y != old_value) { 1456 fimd_update_memory_section(s, w); 1457 } 1458 break; 1459 case 2: 1460 if (w == 0) { 1461 s->window[w].osdsize = val; 1462 } else { 1463 s->window[w].alpha_val[0] = 1464 unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN0) >> 1465 FIMD_VIDOSD_AEN0_SHIFT) | 1466 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER); 1467 s->window[w].alpha_val[1] = 1468 unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN1) | 1469 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER); 1470 } 1471 break; 1472 case 3: 1473 if (w != 1 && w != 2) { 1474 DPRINT_ERROR("Bad write offset 0x%08x\n", offset); 1475 return; 1476 } 1477 s->window[w].osdsize = val; 1478 break; 1479 } 1480 break; 1481 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END: 1482 w = (offset - FIMD_VIDWADD0_START) >> 3; 1483 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1; 1484 if (i == fimd_get_buffer_id(&s->window[w]) && 1485 s->window[w].buf_start[i] != val) { 1486 s->window[w].buf_start[i] = val; 1487 fimd_update_memory_section(s, w); 1488 break; 1489 } 1490 s->window[w].buf_start[i] = val; 1491 break; 1492 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END: 1493 w = (offset - FIMD_VIDWADD1_START) >> 3; 1494 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1; 1495 s->window[w].buf_end[i] = val; 1496 break; 1497 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END: 1498 w = (offset - FIMD_VIDWADD2_START) >> 2; 1499 if (((val & FIMD_VIDWADD2_PAGEWIDTH) != s->window[w].virtpage_width) || 1500 (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE) != 1501 s->window[w].virtpage_offsize)) { 1502 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH; 1503 s->window[w].virtpage_offsize = 1504 (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE; 1505 fimd_update_memory_section(s, w); 1506 } 1507 break; 1508 case FIMD_VIDINTCON0: 1509 s->vidintcon[0] = val; 1510 break; 1511 case FIMD_VIDINTCON1: 1512 s->vidintcon[1] &= ~(val & 7); 1513 exynos4210_fimd_update_irq(s); 1514 break; 1515 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END: 1516 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1; 1517 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1; 1518 s->window[w].keycon[i] = val; 1519 break; 1520 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END: 1521 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1; 1522 s->window[w].keyalpha = val; 1523 break; 1524 case FIMD_DITHMODE: 1525 s->dithmode = val; 1526 break; 1527 case FIMD_WINMAP_START ... FIMD_WINMAP_END: 1528 w = (offset - FIMD_WINMAP_START) >> 2; 1529 old_value = s->window[w].winmap; 1530 s->window[w].winmap = val; 1531 if ((val & FIMD_WINMAP_EN) ^ (old_value & FIMD_WINMAP_EN)) { 1532 exynos4210_fimd_invalidate(s); 1533 exynos4210_fimd_update_win_bppmode(s, w); 1534 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF); 1535 exynos4210_fimd_update(s); 1536 } 1537 break; 1538 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW: 1539 i = (offset - FIMD_WPALCON_HIGH) >> 2; 1540 s->wpalcon[i] = val; 1541 if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN) { 1542 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1543 exynos4210_fimd_update_win_bppmode(s, w); 1544 fimd_update_get_alpha(s, w); 1545 } 1546 } 1547 break; 1548 case FIMD_TRIGCON: 1549 val = (val & ~FIMD_TRIGCON_ROMASK) | (s->trigcon & FIMD_TRIGCON_ROMASK); 1550 s->trigcon = val; 1551 break; 1552 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END: 1553 s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2] = val; 1554 break; 1555 case FIMD_COLORGAINCON: 1556 s->colorgaincon = val; 1557 break; 1558 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1: 1559 s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2] = val; 1560 break; 1561 case FIMD_SIFCCON0 ... FIMD_SIFCCON2: 1562 i = (offset - FIMD_SIFCCON0) >> 2; 1563 if (i != 2) { 1564 s->sifccon[i] = val; 1565 } 1566 break; 1567 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END: 1568 i = (offset - FIMD_HUECOEFCR_START) >> 2; 1569 s->huecoef_cr[i] = val; 1570 break; 1571 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END: 1572 i = (offset - FIMD_HUECOEFCB_START) >> 2; 1573 s->huecoef_cb[i] = val; 1574 break; 1575 case FIMD_HUEOFFSET: 1576 s->hueoffset = val; 1577 break; 1578 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END: 1579 w = ((offset - FIMD_VIDWALPHA_START) >> 3); 1580 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1; 1581 if (w == 0) { 1582 s->window[w].alpha_val[i] = val; 1583 } else { 1584 s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER) | 1585 (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER); 1586 } 1587 break; 1588 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END: 1589 s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq = val; 1590 break; 1591 case FIMD_BLENDCON: 1592 old_value = s->blendcon; 1593 s->blendcon = val; 1594 if ((s->blendcon & FIMD_ALPHA_8BIT) != (old_value & FIMD_ALPHA_8BIT)) { 1595 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1596 fimd_update_get_alpha(s, w); 1597 } 1598 } 1599 break; 1600 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END: 1601 s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon = val; 1602 break; 1603 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END: 1604 s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2] = val; 1605 break; 1606 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2: 1607 if (offset & 0x0004) { 1608 DPRINT_ERROR("bad write offset 0x%08x\n", offset); 1609 break; 1610 } 1611 w = (offset - FIMD_VIDW0ADD0_B2) >> 3; 1612 if (fimd_get_buffer_id(&s->window[w]) == 2 && 1613 s->window[w].buf_start[2] != val) { 1614 s->window[w].buf_start[2] = val; 1615 fimd_update_memory_section(s, w); 1616 break; 1617 } 1618 s->window[w].buf_start[2] = val; 1619 break; 1620 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END: 1621 if (offset & 0x0004) { 1622 DPRINT_ERROR("bad write offset 0x%08x\n", offset); 1623 break; 1624 } 1625 s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val; 1626 break; 1627 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END: 1628 if (offset & 0x0004) { 1629 DPRINT_ERROR("bad write offset 0x%08x\n", offset); 1630 break; 1631 } 1632 s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val; 1633 break; 1634 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END: 1635 s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size = val; 1636 break; 1637 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END: 1638 w = (offset - FIMD_PAL_MEM_START) >> 10; 1639 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF; 1640 s->window[w].palette[i] = val; 1641 break; 1642 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END: 1643 /* Palette memory aliases for windows 0 and 1 */ 1644 w = (offset - FIMD_PALMEM_AL_START) >> 10; 1645 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF; 1646 s->window[w].palette[i] = val; 1647 break; 1648 default: 1649 DPRINT_ERROR("bad write offset 0x%08x\n", offset); 1650 break; 1651 } 1652 } 1653 1654 static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset, 1655 unsigned size) 1656 { 1657 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1658 int w, i; 1659 uint32_t ret = 0; 1660 1661 DPRINT_L2("read offset 0x%08x\n", offset); 1662 1663 switch (offset) { 1664 case FIMD_VIDCON0 ... FIMD_VIDCON3: 1665 return s->vidcon[(offset - FIMD_VIDCON0) >> 2]; 1666 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END: 1667 return s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2]; 1668 case FIMD_WINCON_START ... FIMD_WINCON_END: 1669 return s->window[(offset - FIMD_WINCON_START) >> 2].wincon; 1670 case FIMD_SHADOWCON: 1671 return s->shadowcon; 1672 case FIMD_WINCHMAP: 1673 return s->winchmap; 1674 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END: 1675 w = (offset - FIMD_VIDOSD_START) >> 4; 1676 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2; 1677 switch (i) { 1678 case 0: 1679 ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK) << 1680 FIMD_VIDOSD_HOR_SHIFT) | 1681 (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK); 1682 break; 1683 case 1: 1684 ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK) << 1685 FIMD_VIDOSD_HOR_SHIFT) | 1686 (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK); 1687 break; 1688 case 2: 1689 if (w == 0) { 1690 ret = s->window[w].osdsize; 1691 } else { 1692 ret = (pack_upper_4(s->window[w].alpha_val[0]) << 1693 FIMD_VIDOSD_AEN0_SHIFT) | 1694 pack_upper_4(s->window[w].alpha_val[1]); 1695 } 1696 break; 1697 case 3: 1698 if (w != 1 && w != 2) { 1699 DPRINT_ERROR("bad read offset 0x%08x\n", offset); 1700 return 0xBAADBAAD; 1701 } 1702 ret = s->window[w].osdsize; 1703 break; 1704 } 1705 return ret; 1706 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END: 1707 w = (offset - FIMD_VIDWADD0_START) >> 3; 1708 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1; 1709 return s->window[w].buf_start[i]; 1710 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END: 1711 w = (offset - FIMD_VIDWADD1_START) >> 3; 1712 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1; 1713 return s->window[w].buf_end[i]; 1714 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END: 1715 w = (offset - FIMD_VIDWADD2_START) >> 2; 1716 return s->window[w].virtpage_width | (s->window[w].virtpage_offsize << 1717 FIMD_VIDWADD2_OFFSIZE_SHIFT); 1718 case FIMD_VIDINTCON0 ... FIMD_VIDINTCON1: 1719 return s->vidintcon[(offset - FIMD_VIDINTCON0) >> 2]; 1720 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END: 1721 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1; 1722 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1; 1723 return s->window[w].keycon[i]; 1724 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END: 1725 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1; 1726 return s->window[w].keyalpha; 1727 case FIMD_DITHMODE: 1728 return s->dithmode; 1729 case FIMD_WINMAP_START ... FIMD_WINMAP_END: 1730 return s->window[(offset - FIMD_WINMAP_START) >> 2].winmap; 1731 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW: 1732 return s->wpalcon[(offset - FIMD_WPALCON_HIGH) >> 2]; 1733 case FIMD_TRIGCON: 1734 return s->trigcon; 1735 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END: 1736 return s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2]; 1737 case FIMD_COLORGAINCON: 1738 return s->colorgaincon; 1739 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1: 1740 return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2]; 1741 case FIMD_SIFCCON0 ... FIMD_SIFCCON2: 1742 i = (offset - FIMD_SIFCCON0) >> 2; 1743 return s->sifccon[i]; 1744 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END: 1745 i = (offset - FIMD_HUECOEFCR_START) >> 2; 1746 return s->huecoef_cr[i]; 1747 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END: 1748 i = (offset - FIMD_HUECOEFCB_START) >> 2; 1749 return s->huecoef_cb[i]; 1750 case FIMD_HUEOFFSET: 1751 return s->hueoffset; 1752 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END: 1753 w = ((offset - FIMD_VIDWALPHA_START) >> 3); 1754 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1; 1755 return s->window[w].alpha_val[i] & 1756 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER); 1757 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END: 1758 return s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq; 1759 case FIMD_BLENDCON: 1760 return s->blendcon; 1761 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END: 1762 return s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon; 1763 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END: 1764 return s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2]; 1765 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2: 1766 if (offset & 0x0004) { 1767 break; 1768 } 1769 return s->window[(offset - FIMD_VIDW0ADD0_B2) >> 3].buf_start[2]; 1770 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END: 1771 if (offset & 0x0004) { 1772 break; 1773 } 1774 return s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start; 1775 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END: 1776 if (offset & 0x0004) { 1777 break; 1778 } 1779 return s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end; 1780 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END: 1781 return s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size; 1782 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END: 1783 w = (offset - FIMD_PAL_MEM_START) >> 10; 1784 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF; 1785 return s->window[w].palette[i]; 1786 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END: 1787 /* Palette aliases for win 0,1 */ 1788 w = (offset - FIMD_PALMEM_AL_START) >> 10; 1789 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF; 1790 return s->window[w].palette[i]; 1791 } 1792 1793 DPRINT_ERROR("bad read offset 0x%08x\n", offset); 1794 return 0xBAADBAAD; 1795 } 1796 1797 static const MemoryRegionOps exynos4210_fimd_mmio_ops = { 1798 .read = exynos4210_fimd_read, 1799 .write = exynos4210_fimd_write, 1800 .valid = { 1801 .min_access_size = 4, 1802 .max_access_size = 4, 1803 .unaligned = false 1804 }, 1805 .endianness = DEVICE_NATIVE_ENDIAN, 1806 }; 1807 1808 static int exynos4210_fimd_load(void *opaque, int version_id) 1809 { 1810 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1811 int w; 1812 1813 if (version_id != 1) { 1814 return -EINVAL; 1815 } 1816 1817 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1818 exynos4210_fimd_update_win_bppmode(s, w); 1819 fimd_update_get_alpha(s, w); 1820 fimd_update_memory_section(s, w); 1821 } 1822 1823 /* Redraw the whole screen */ 1824 exynos4210_update_resolution(s); 1825 exynos4210_fimd_invalidate(s); 1826 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) == 1827 FIMD_VIDCON0_ENVID_MASK); 1828 return 0; 1829 } 1830 1831 static const VMStateDescription exynos4210_fimd_window_vmstate = { 1832 .name = "exynos4210.fimd_window", 1833 .version_id = 1, 1834 .minimum_version_id = 1, 1835 .fields = (VMStateField[]) { 1836 VMSTATE_UINT32(wincon, Exynos4210fimdWindow), 1837 VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3), 1838 VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3), 1839 VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2), 1840 VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow), 1841 VMSTATE_UINT32(winmap, Exynos4210fimdWindow), 1842 VMSTATE_UINT32(blendeq, Exynos4210fimdWindow), 1843 VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow), 1844 VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256), 1845 VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow), 1846 VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow), 1847 VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow), 1848 VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow), 1849 VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow), 1850 VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow), 1851 VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow), 1852 VMSTATE_UINT32(osdsize, Exynos4210fimdWindow), 1853 VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2), 1854 VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow), 1855 VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow), 1856 VMSTATE_END_OF_LIST() 1857 } 1858 }; 1859 1860 static const VMStateDescription exynos4210_fimd_vmstate = { 1861 .name = "exynos4210.fimd", 1862 .version_id = 1, 1863 .minimum_version_id = 1, 1864 .post_load = exynos4210_fimd_load, 1865 .fields = (VMStateField[]) { 1866 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4), 1867 VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4), 1868 VMSTATE_UINT32(shadowcon, Exynos4210fimdState), 1869 VMSTATE_UINT32(winchmap, Exynos4210fimdState), 1870 VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2), 1871 VMSTATE_UINT32(dithmode, Exynos4210fimdState), 1872 VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2), 1873 VMSTATE_UINT32(trigcon, Exynos4210fimdState), 1874 VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4), 1875 VMSTATE_UINT32(colorgaincon, Exynos4210fimdState), 1876 VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2), 1877 VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3), 1878 VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4), 1879 VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4), 1880 VMSTATE_UINT32(hueoffset, Exynos4210fimdState), 1881 VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12), 1882 VMSTATE_UINT32(blendcon, Exynos4210fimdState), 1883 VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1, 1884 exynos4210_fimd_window_vmstate, Exynos4210fimdWindow), 1885 VMSTATE_END_OF_LIST() 1886 } 1887 }; 1888 1889 static int exynos4210_fimd_init(SysBusDevice *dev) 1890 { 1891 Exynos4210fimdState *s = FROM_SYSBUS(Exynos4210fimdState, dev); 1892 1893 s->ifb = NULL; 1894 1895 sysbus_init_irq(dev, &s->irq[0]); 1896 sysbus_init_irq(dev, &s->irq[1]); 1897 sysbus_init_irq(dev, &s->irq[2]); 1898 1899 memory_region_init_io(&s->iomem, &exynos4210_fimd_mmio_ops, s, 1900 "exynos4210.fimd", FIMD_REGS_SIZE); 1901 sysbus_init_mmio(dev, &s->iomem); 1902 s->console = graphic_console_init(exynos4210_fimd_update, 1903 exynos4210_fimd_invalidate, NULL, NULL, s); 1904 1905 return 0; 1906 } 1907 1908 static void exynos4210_fimd_class_init(ObjectClass *klass, void *data) 1909 { 1910 DeviceClass *dc = DEVICE_CLASS(klass); 1911 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1912 1913 dc->vmsd = &exynos4210_fimd_vmstate; 1914 dc->reset = exynos4210_fimd_reset; 1915 k->init = exynos4210_fimd_init; 1916 } 1917 1918 static const TypeInfo exynos4210_fimd_info = { 1919 .name = "exynos4210.fimd", 1920 .parent = TYPE_SYS_BUS_DEVICE, 1921 .instance_size = sizeof(Exynos4210fimdState), 1922 .class_init = exynos4210_fimd_class_init, 1923 }; 1924 1925 static void exynos4210_fimd_register_types(void) 1926 { 1927 type_register_static(&exynos4210_fimd_info); 1928 } 1929 1930 type_init(exynos4210_fimd_register_types) 1931