1 /* 2 * QEMU ATI SVGA emulation 3 * 4 * Copyright (c) 2019 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 */ 8 9 /* 10 * WARNING: 11 * This is very incomplete and only enough for Linux console and some 12 * unaccelerated X output at the moment. 13 * Currently it's little more than a frame buffer with minimal functions, 14 * other more advanced features of the hardware are yet to be implemented. 15 * We only aim for Rage 128 Pro (and some RV100) and 2D only at first, 16 * No 3D at all yet (maybe after 2D works, but feel free to improve it) 17 */ 18 19 #include "qemu/osdep.h" 20 #include "ati_int.h" 21 #include "ati_regs.h" 22 #include "hw/qdev-properties.h" 23 #include "vga_regs.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "ui/console.h" 29 #include "hw/display/i2c-ddc.h" 30 #include "trace.h" 31 32 #define ATI_DEBUG_HW_CURSOR 0 33 34 static const struct { 35 const char *name; 36 uint16_t dev_id; 37 } ati_model_aliases[] = { 38 { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF }, 39 { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY }, 40 }; 41 42 enum { VGA_MODE, EXT_MODE }; 43 44 static void ati_vga_switch_mode(ATIVGAState *s) 45 { 46 DPRINTF("%d -> %d\n", 47 s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN)); 48 if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) { 49 /* Extended mode enabled */ 50 s->mode = EXT_MODE; 51 if (s->regs.crtc_gen_cntl & CRTC2_EN) { 52 /* CRT controller enabled, use CRTC values */ 53 /* FIXME Should these be the same as VGA CRTC regs? */ 54 uint32_t offs = s->regs.crtc_offset & 0x07ffffff; 55 int stride = (s->regs.crtc_pitch & 0x7ff) * 8; 56 int bpp = 0; 57 int h, v; 58 59 if (s->regs.crtc_h_total_disp == 0) { 60 s->regs.crtc_h_total_disp = ((640 / 8) - 1) << 16; 61 } 62 if (s->regs.crtc_v_total_disp == 0) { 63 s->regs.crtc_v_total_disp = (480 - 1) << 16; 64 } 65 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 66 v = (s->regs.crtc_v_total_disp >> 16) + 1; 67 switch (s->regs.crtc_gen_cntl & CRTC_PIX_WIDTH_MASK) { 68 case CRTC_PIX_WIDTH_4BPP: 69 bpp = 4; 70 break; 71 case CRTC_PIX_WIDTH_8BPP: 72 bpp = 8; 73 break; 74 case CRTC_PIX_WIDTH_15BPP: 75 bpp = 15; 76 break; 77 case CRTC_PIX_WIDTH_16BPP: 78 bpp = 16; 79 break; 80 case CRTC_PIX_WIDTH_24BPP: 81 bpp = 24; 82 break; 83 case CRTC_PIX_WIDTH_32BPP: 84 bpp = 32; 85 break; 86 default: 87 qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n"); 88 } 89 assert(bpp != 0); 90 DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs); 91 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 92 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 93 s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN || 94 s->regs.config_cntl & APER_1_ENDIAN ? 95 true : false); 96 /* reset VBE regs then set up mode */ 97 s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h; 98 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v; 99 s->vga.vbe_regs[VBE_DISPI_INDEX_BPP] = bpp; 100 /* enable mode via ioport so it updates vga regs */ 101 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 102 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED | 103 VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM | 104 (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0)); 105 /* now set offset and stride after enable as that resets these */ 106 if (stride) { 107 int bypp = DIV_ROUND_UP(bpp, BITS_PER_BYTE); 108 109 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH); 110 vbe_ioport_write_data(&s->vga, 0, stride); 111 stride *= bypp; 112 if (offs % stride) { 113 DPRINTF("CRTC offset is not multiple of pitch\n"); 114 vbe_ioport_write_index(&s->vga, 0, 115 VBE_DISPI_INDEX_X_OFFSET); 116 vbe_ioport_write_data(&s->vga, 0, offs % stride / bypp); 117 } 118 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET); 119 vbe_ioport_write_data(&s->vga, 0, offs / stride); 120 DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n", 121 s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET], 122 s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET], 123 s->vga.vbe_start_addr); 124 } 125 } 126 } else { 127 /* VGA mode enabled */ 128 s->mode = VGA_MODE; 129 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 130 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 131 } 132 } 133 134 /* Used by host side hardware cursor */ 135 static void ati_cursor_define(ATIVGAState *s) 136 { 137 uint8_t data[1024]; 138 uint8_t *src; 139 int i, j, idx = 0; 140 141 if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) { 142 return; /* Do not update cursor if locked or rendered by guest */ 143 } 144 /* FIXME handle cur_hv_offs correctly */ 145 src = s->vga.vram_ptr + s->regs.cur_offset - 146 (s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0xffff) * 16; 147 for (i = 0; i < 64; i++) { 148 for (j = 0; j < 8; j++, idx++) { 149 data[idx] = src[i * 16 + j]; 150 data[512 + idx] = src[i * 16 + j + 8]; 151 } 152 } 153 if (!s->cursor) { 154 s->cursor = cursor_alloc(64, 64); 155 } 156 cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0, 157 &data[512], 1, &data[0]); 158 dpy_cursor_define(s->vga.con, s->cursor); 159 } 160 161 /* Alternatively support guest rendered hardware cursor */ 162 static void ati_cursor_invalidate(VGACommonState *vga) 163 { 164 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 165 int size = (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ? 64 : 0; 166 167 if (s->regs.cur_offset & BIT(31)) { 168 return; /* Do not update cursor if locked */ 169 } 170 if (s->cursor_size != size || 171 vga->hw_cursor_x != s->regs.cur_hv_pos >> 16 || 172 vga->hw_cursor_y != (s->regs.cur_hv_pos & 0xffff) || 173 s->cursor_offset != s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 174 (s->regs.cur_hv_offs & 0xffff) * 16) { 175 /* Remove old cursor then update and show new one if needed */ 176 vga_invalidate_scanlines(vga, vga->hw_cursor_y, vga->hw_cursor_y + 63); 177 vga->hw_cursor_x = s->regs.cur_hv_pos >> 16; 178 vga->hw_cursor_y = s->regs.cur_hv_pos & 0xffff; 179 s->cursor_offset = s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 180 (s->regs.cur_hv_offs & 0xffff) * 16; 181 s->cursor_size = size; 182 if (size) { 183 vga_invalidate_scanlines(vga, 184 vga->hw_cursor_y, vga->hw_cursor_y + 63); 185 } 186 } 187 } 188 189 static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y) 190 { 191 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 192 uint8_t *src; 193 uint32_t *dp = (uint32_t *)d; 194 int i, j, h; 195 196 if (!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) || 197 scr_y < vga->hw_cursor_y || scr_y >= vga->hw_cursor_y + 64 || 198 scr_y > s->regs.crtc_v_total_disp >> 16) { 199 return; 200 } 201 /* FIXME handle cur_hv_offs correctly */ 202 src = s->vga.vram_ptr + s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16; 203 dp = &dp[vga->hw_cursor_x]; 204 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 205 for (i = 0; i < 8; i++) { 206 uint32_t color; 207 uint8_t abits = src[i]; 208 uint8_t xbits = src[i + 8]; 209 for (j = 0; j < 8; j++, abits <<= 1, xbits <<= 1) { 210 if (abits & BIT(7)) { 211 if (xbits & BIT(7)) { 212 color = dp[i * 8 + j] ^ 0xffffffff; /* complement */ 213 } else { 214 continue; /* transparent, no change */ 215 } 216 } else { 217 color = (xbits & BIT(7) ? s->regs.cur_color1 : 218 s->regs.cur_color0) | 0xff000000; 219 } 220 if (vga->hw_cursor_x + i * 8 + j >= h) { 221 return; /* end of screen, don't span to next line */ 222 } 223 dp[i * 8 + j] = color; 224 } 225 } 226 } 227 228 static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base) 229 { 230 bool c = (data & BIT(base + 17) ? !!(data & BIT(base + 1)) : 1); 231 bool d = (data & BIT(base + 16) ? !!(data & BIT(base)) : 1); 232 233 bitbang_i2c_set(i2c, BITBANG_I2C_SCL, c); 234 d = bitbang_i2c_set(i2c, BITBANG_I2C_SDA, d); 235 236 data &= ~0xf00ULL; 237 if (c) { 238 data |= BIT(base + 9); 239 } 240 if (d) { 241 data |= BIT(base + 8); 242 } 243 return data; 244 } 245 246 static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs, 247 unsigned int size) 248 { 249 if (offs == 0 && size == 4) { 250 return reg; 251 } else { 252 return extract32(reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE); 253 } 254 } 255 256 static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) 257 { 258 ATIVGAState *s = opaque; 259 uint64_t val = 0; 260 261 switch (addr) { 262 case MM_INDEX: 263 val = s->regs.mm_index; 264 break; 265 case MM_DATA ... MM_DATA + 3: 266 /* indexed access to regs or memory */ 267 if (s->regs.mm_index & BIT(31)) { 268 uint32_t idx = s->regs.mm_index & ~BIT(31); 269 if (idx <= s->vga.vram_size - size) { 270 val = ldn_le_p(s->vga.vram_ptr + idx, size); 271 } 272 } else { 273 val = ati_mm_read(s, s->regs.mm_index + addr - MM_DATA, size); 274 } 275 break; 276 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 277 { 278 int i = (addr - BIOS_0_SCRATCH) / 4; 279 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 280 break; 281 } 282 val = ati_reg_read_offs(s->regs.bios_scratch[i], 283 addr - (BIOS_0_SCRATCH + i * 4), size); 284 break; 285 } 286 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 287 val = ati_reg_read_offs(s->regs.crtc_gen_cntl, 288 addr - CRTC_GEN_CNTL, size); 289 break; 290 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 291 val = ati_reg_read_offs(s->regs.crtc_ext_cntl, 292 addr - CRTC_EXT_CNTL, size); 293 break; 294 case DAC_CNTL: 295 val = s->regs.dac_cntl; 296 break; 297 case GPIO_VGA_DDC: 298 val = s->regs.gpio_vga_ddc; 299 break; 300 case GPIO_DVI_DDC: 301 val = s->regs.gpio_dvi_ddc; 302 break; 303 case GPIO_MONID ... GPIO_MONID + 3: 304 val = ati_reg_read_offs(s->regs.gpio_monid, 305 addr - GPIO_MONID, size); 306 break; 307 case PALETTE_INDEX: 308 /* FIXME unaligned access */ 309 val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16; 310 val |= vga_ioport_read(&s->vga, VGA_PEL_IW) & 0xff; 311 break; 312 case PALETTE_DATA: 313 val = vga_ioport_read(&s->vga, VGA_PEL_D); 314 break; 315 case CNFG_CNTL: 316 val = s->regs.config_cntl; 317 break; 318 case CNFG_MEMSIZE: 319 val = s->vga.vram_size; 320 break; 321 case CONFIG_APER_0_BASE: 322 case CONFIG_APER_1_BASE: 323 val = pci_default_read_config(&s->dev, 324 PCI_BASE_ADDRESS_0, size) & 0xfffffff0; 325 break; 326 case CONFIG_APER_SIZE: 327 val = s->vga.vram_size; 328 break; 329 case CONFIG_REG_1_BASE: 330 val = pci_default_read_config(&s->dev, 331 PCI_BASE_ADDRESS_2, size) & 0xfffffff0; 332 break; 333 case CONFIG_REG_APER_SIZE: 334 val = memory_region_size(&s->mm); 335 break; 336 case MC_STATUS: 337 val = 5; 338 break; 339 case RBBM_STATUS: 340 case GUI_STAT: 341 val = 64; /* free CMDFIFO entries */ 342 break; 343 case CRTC_H_TOTAL_DISP: 344 val = s->regs.crtc_h_total_disp; 345 break; 346 case CRTC_H_SYNC_STRT_WID: 347 val = s->regs.crtc_h_sync_strt_wid; 348 break; 349 case CRTC_V_TOTAL_DISP: 350 val = s->regs.crtc_v_total_disp; 351 break; 352 case CRTC_V_SYNC_STRT_WID: 353 val = s->regs.crtc_v_sync_strt_wid; 354 break; 355 case CRTC_OFFSET: 356 val = s->regs.crtc_offset; 357 break; 358 case CRTC_OFFSET_CNTL: 359 val = s->regs.crtc_offset_cntl; 360 break; 361 case CRTC_PITCH: 362 val = s->regs.crtc_pitch; 363 break; 364 case 0xf00 ... 0xfff: 365 val = pci_default_read_config(&s->dev, addr - 0xf00, size); 366 break; 367 case CUR_OFFSET: 368 val = s->regs.cur_offset; 369 break; 370 case CUR_HORZ_VERT_POSN: 371 val = s->regs.cur_hv_pos; 372 val |= s->regs.cur_offset & BIT(31); 373 break; 374 case CUR_HORZ_VERT_OFF: 375 val = s->regs.cur_hv_offs; 376 val |= s->regs.cur_offset & BIT(31); 377 break; 378 case CUR_CLR0: 379 val = s->regs.cur_color0; 380 break; 381 case CUR_CLR1: 382 val = s->regs.cur_color1; 383 break; 384 case DST_OFFSET: 385 val = s->regs.dst_offset; 386 break; 387 case DST_PITCH: 388 val = s->regs.dst_pitch; 389 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 390 val &= s->regs.dst_tile << 16; 391 } 392 break; 393 case DST_WIDTH: 394 val = s->regs.dst_width; 395 break; 396 case DST_HEIGHT: 397 val = s->regs.dst_height; 398 break; 399 case SRC_X: 400 val = s->regs.src_x; 401 break; 402 case SRC_Y: 403 val = s->regs.src_y; 404 break; 405 case DST_X: 406 val = s->regs.dst_x; 407 break; 408 case DST_Y: 409 val = s->regs.dst_y; 410 break; 411 case DP_GUI_MASTER_CNTL: 412 val = s->regs.dp_gui_master_cntl; 413 break; 414 case SRC_OFFSET: 415 val = s->regs.src_offset; 416 break; 417 case SRC_PITCH: 418 val = s->regs.src_pitch; 419 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 420 val &= s->regs.src_tile << 16; 421 } 422 break; 423 case DP_BRUSH_BKGD_CLR: 424 val = s->regs.dp_brush_bkgd_clr; 425 break; 426 case DP_BRUSH_FRGD_CLR: 427 val = s->regs.dp_brush_frgd_clr; 428 break; 429 case DP_SRC_FRGD_CLR: 430 val = s->regs.dp_src_frgd_clr; 431 break; 432 case DP_SRC_BKGD_CLR: 433 val = s->regs.dp_src_bkgd_clr; 434 break; 435 case DP_CNTL: 436 val = s->regs.dp_cntl; 437 break; 438 case DP_DATATYPE: 439 val = s->regs.dp_datatype; 440 break; 441 case DP_MIX: 442 val = s->regs.dp_mix; 443 break; 444 case DP_WRITE_MASK: 445 val = s->regs.dp_write_mask; 446 break; 447 case DEFAULT_OFFSET: 448 val = s->regs.default_offset; 449 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 450 val >>= 10; 451 val |= s->regs.default_pitch << 16; 452 val |= s->regs.default_tile << 30; 453 } 454 break; 455 case DEFAULT_PITCH: 456 val = s->regs.default_pitch; 457 val |= s->regs.default_tile << 16; 458 break; 459 case DEFAULT_SC_BOTTOM_RIGHT: 460 val = s->regs.default_sc_bottom_right; 461 break; 462 default: 463 break; 464 } 465 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 466 trace_ati_mm_read(size, addr, ati_reg_name(addr & ~3ULL), val); 467 } 468 return val; 469 } 470 471 static inline void ati_reg_write_offs(uint32_t *reg, int offs, 472 uint64_t data, unsigned int size) 473 { 474 if (offs == 0 && size == 4) { 475 *reg = data; 476 } else { 477 *reg = deposit32(*reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE, 478 data); 479 } 480 } 481 482 static void ati_mm_write(void *opaque, hwaddr addr, 483 uint64_t data, unsigned int size) 484 { 485 ATIVGAState *s = opaque; 486 487 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 488 trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data); 489 } 490 switch (addr) { 491 case MM_INDEX: 492 s->regs.mm_index = data; 493 break; 494 case MM_DATA ... MM_DATA + 3: 495 /* indexed access to regs or memory */ 496 if (s->regs.mm_index & BIT(31)) { 497 uint32_t idx = s->regs.mm_index & ~BIT(31); 498 if (idx <= s->vga.vram_size - size) { 499 stn_le_p(s->vga.vram_ptr + idx, size, data); 500 } 501 } else { 502 ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size); 503 } 504 break; 505 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 506 { 507 int i = (addr - BIOS_0_SCRATCH) / 4; 508 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 509 break; 510 } 511 ati_reg_write_offs(&s->regs.bios_scratch[i], 512 addr - (BIOS_0_SCRATCH + i * 4), data, size); 513 break; 514 } 515 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 516 { 517 uint32_t val = s->regs.crtc_gen_cntl; 518 ati_reg_write_offs(&s->regs.crtc_gen_cntl, 519 addr - CRTC_GEN_CNTL, data, size); 520 if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) { 521 if (s->cursor_guest_mode) { 522 s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN); 523 } else { 524 if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) { 525 ati_cursor_define(s); 526 } 527 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 528 s->regs.cur_hv_pos & 0xffff, 529 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0); 530 } 531 } 532 if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) != 533 (s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) { 534 ati_vga_switch_mode(s); 535 } 536 break; 537 } 538 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 539 { 540 uint32_t val = s->regs.crtc_ext_cntl; 541 ati_reg_write_offs(&s->regs.crtc_ext_cntl, 542 addr - CRTC_EXT_CNTL, data, size); 543 if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) { 544 DPRINTF("Display disabled\n"); 545 s->vga.ar_index &= ~BIT(5); 546 } else { 547 DPRINTF("Display enabled\n"); 548 s->vga.ar_index |= BIT(5); 549 ati_vga_switch_mode(s); 550 } 551 if ((val & CRT_CRTC_DISPLAY_DIS) != 552 (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) { 553 ati_vga_switch_mode(s); 554 } 555 break; 556 } 557 case DAC_CNTL: 558 s->regs.dac_cntl = data & 0xffffe3ff; 559 s->vga.dac_8bit = !!(data & DAC_8BIT_EN); 560 break; 561 case GPIO_VGA_DDC: 562 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 563 /* FIXME: Maybe add a property to select VGA or DVI port? */ 564 } 565 break; 566 case GPIO_DVI_DDC: 567 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 568 s->regs.gpio_dvi_ddc = ati_i2c(&s->bbi2c, data, 0); 569 } 570 break; 571 case GPIO_MONID ... GPIO_MONID + 3: 572 /* FIXME What does Radeon have here? */ 573 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 574 ati_reg_write_offs(&s->regs.gpio_monid, 575 addr - GPIO_MONID, data, size); 576 /* 577 * Rage128p accesses DDC used to get EDID via these bits. 578 * Because some drivers access this via multiple byte writes 579 * we have to be careful when we send bits to avoid spurious 580 * changes in bitbang_i2c state. So only do it when mask is set 581 * and either the enable bits are changed or output bits changed 582 * while enabled. 583 */ 584 if ((s->regs.gpio_monid & BIT(25)) && 585 ((addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) || 586 (addr == GPIO_MONID && (s->regs.gpio_monid & 0x60000)))) { 587 s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1); 588 } 589 } 590 break; 591 case PALETTE_INDEX ... PALETTE_INDEX + 3: 592 if (size == 4) { 593 vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff); 594 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 595 } else { 596 if (addr == PALETTE_INDEX) { 597 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 598 } else { 599 vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff); 600 } 601 } 602 break; 603 case PALETTE_DATA ... PALETTE_DATA + 3: 604 data <<= addr - PALETTE_DATA; 605 data = bswap32(data) >> 8; 606 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 607 data >>= 8; 608 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 609 data >>= 8; 610 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 611 break; 612 case CNFG_CNTL: 613 s->regs.config_cntl = data; 614 break; 615 case CRTC_H_TOTAL_DISP: 616 s->regs.crtc_h_total_disp = data & 0x07ff07ff; 617 break; 618 case CRTC_H_SYNC_STRT_WID: 619 s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff; 620 break; 621 case CRTC_V_TOTAL_DISP: 622 s->regs.crtc_v_total_disp = data & 0x0fff0fff; 623 break; 624 case CRTC_V_SYNC_STRT_WID: 625 s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff; 626 break; 627 case CRTC_OFFSET: 628 s->regs.crtc_offset = data & 0xc7ffffff; 629 break; 630 case CRTC_OFFSET_CNTL: 631 s->regs.crtc_offset_cntl = data; /* FIXME */ 632 break; 633 case CRTC_PITCH: 634 s->regs.crtc_pitch = data & 0x07ff07ff; 635 break; 636 case 0xf00 ... 0xfff: 637 /* read-only copy of PCI config space so ignore writes */ 638 break; 639 case CUR_OFFSET: 640 if (s->regs.cur_offset != (data & 0x87fffff0)) { 641 s->regs.cur_offset = data & 0x87fffff0; 642 ati_cursor_define(s); 643 } 644 break; 645 case CUR_HORZ_VERT_POSN: 646 s->regs.cur_hv_pos = data & 0x3fff0fff; 647 if (data & BIT(31)) { 648 s->regs.cur_offset |= data & BIT(31); 649 } else if (s->regs.cur_offset & BIT(31)) { 650 s->regs.cur_offset &= ~BIT(31); 651 ati_cursor_define(s); 652 } 653 if (!s->cursor_guest_mode && 654 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(data & BIT(31))) { 655 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 656 s->regs.cur_hv_pos & 0xffff, 1); 657 } 658 break; 659 case CUR_HORZ_VERT_OFF: 660 s->regs.cur_hv_offs = data & 0x3f003f; 661 if (data & BIT(31)) { 662 s->regs.cur_offset |= data & BIT(31); 663 } else if (s->regs.cur_offset & BIT(31)) { 664 s->regs.cur_offset &= ~BIT(31); 665 ati_cursor_define(s); 666 } 667 break; 668 case CUR_CLR0: 669 if (s->regs.cur_color0 != (data & 0xffffff)) { 670 s->regs.cur_color0 = data & 0xffffff; 671 ati_cursor_define(s); 672 } 673 break; 674 case CUR_CLR1: 675 /* 676 * Update cursor unconditionally here because some clients set up 677 * other registers before actually writing cursor data to memory at 678 * offset so we would miss cursor change unless always updating here 679 */ 680 s->regs.cur_color1 = data & 0xffffff; 681 ati_cursor_define(s); 682 break; 683 case DST_OFFSET: 684 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 685 s->regs.dst_offset = data & 0xfffffff0; 686 } else { 687 s->regs.dst_offset = data & 0xfffffc00; 688 } 689 break; 690 case DST_PITCH: 691 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 692 s->regs.dst_pitch = data & 0x3fff; 693 s->regs.dst_tile = (data >> 16) & 1; 694 } else { 695 s->regs.dst_pitch = data & 0x3ff0; 696 } 697 break; 698 case DST_TILE: 699 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) { 700 s->regs.dst_tile = data & 3; 701 } 702 break; 703 case DST_WIDTH: 704 s->regs.dst_width = data & 0x3fff; 705 ati_2d_blt(s); 706 break; 707 case DST_HEIGHT: 708 s->regs.dst_height = data & 0x3fff; 709 break; 710 case SRC_X: 711 s->regs.src_x = data & 0x3fff; 712 break; 713 case SRC_Y: 714 s->regs.src_y = data & 0x3fff; 715 break; 716 case DST_X: 717 s->regs.dst_x = data & 0x3fff; 718 break; 719 case DST_Y: 720 s->regs.dst_y = data & 0x3fff; 721 break; 722 case SRC_PITCH_OFFSET: 723 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 724 s->regs.src_offset = (data & 0x1fffff) << 5; 725 s->regs.src_pitch = (data & 0x7fe00000) >> 21; 726 s->regs.src_tile = data >> 31; 727 } else { 728 s->regs.src_offset = (data & 0x3fffff) << 10; 729 s->regs.src_pitch = (data & 0x3fc00000) >> 16; 730 s->regs.src_tile = (data >> 30) & 1; 731 } 732 break; 733 case DST_PITCH_OFFSET: 734 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 735 s->regs.dst_offset = (data & 0x1fffff) << 5; 736 s->regs.dst_pitch = (data & 0x7fe00000) >> 21; 737 s->regs.dst_tile = data >> 31; 738 } else { 739 s->regs.dst_offset = (data & 0x3fffff) << 10; 740 s->regs.dst_pitch = (data & 0x3fc00000) >> 16; 741 s->regs.dst_tile = data >> 30; 742 } 743 break; 744 case SRC_Y_X: 745 s->regs.src_x = data & 0x3fff; 746 s->regs.src_y = (data >> 16) & 0x3fff; 747 break; 748 case DST_Y_X: 749 s->regs.dst_x = data & 0x3fff; 750 s->regs.dst_y = (data >> 16) & 0x3fff; 751 break; 752 case DST_HEIGHT_WIDTH: 753 s->regs.dst_width = data & 0x3fff; 754 s->regs.dst_height = (data >> 16) & 0x3fff; 755 ati_2d_blt(s); 756 break; 757 case DP_GUI_MASTER_CNTL: 758 s->regs.dp_gui_master_cntl = data & 0xf800000f; 759 s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 | 760 (data & 0x4000) << 16; 761 s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16; 762 break; 763 case DST_WIDTH_X: 764 s->regs.dst_x = data & 0x3fff; 765 s->regs.dst_width = (data >> 16) & 0x3fff; 766 ati_2d_blt(s); 767 break; 768 case SRC_X_Y: 769 s->regs.src_y = data & 0x3fff; 770 s->regs.src_x = (data >> 16) & 0x3fff; 771 break; 772 case DST_X_Y: 773 s->regs.dst_y = data & 0x3fff; 774 s->regs.dst_x = (data >> 16) & 0x3fff; 775 break; 776 case DST_WIDTH_HEIGHT: 777 s->regs.dst_height = data & 0x3fff; 778 s->regs.dst_width = (data >> 16) & 0x3fff; 779 ati_2d_blt(s); 780 break; 781 case DST_HEIGHT_Y: 782 s->regs.dst_y = data & 0x3fff; 783 s->regs.dst_height = (data >> 16) & 0x3fff; 784 break; 785 case SRC_OFFSET: 786 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 787 s->regs.src_offset = data & 0xfffffff0; 788 } else { 789 s->regs.src_offset = data & 0xfffffc00; 790 } 791 break; 792 case SRC_PITCH: 793 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 794 s->regs.src_pitch = data & 0x3fff; 795 s->regs.src_tile = (data >> 16) & 1; 796 } else { 797 s->regs.src_pitch = data & 0x3ff0; 798 } 799 break; 800 case DP_BRUSH_BKGD_CLR: 801 s->regs.dp_brush_bkgd_clr = data; 802 break; 803 case DP_BRUSH_FRGD_CLR: 804 s->regs.dp_brush_frgd_clr = data; 805 break; 806 case DP_CNTL: 807 s->regs.dp_cntl = data; 808 break; 809 case DP_DATATYPE: 810 s->regs.dp_datatype = data & 0xe0070f0f; 811 break; 812 case DP_MIX: 813 s->regs.dp_mix = data & 0x00ff0700; 814 break; 815 case DP_WRITE_MASK: 816 s->regs.dp_write_mask = data; 817 break; 818 case DEFAULT_OFFSET: 819 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 820 s->regs.default_offset = data & 0xfffffff0; 821 } else { 822 /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */ 823 s->regs.default_offset = (data & 0x3fffff) << 10; 824 s->regs.default_pitch = (data & 0x3fc00000) >> 16; 825 s->regs.default_tile = data >> 30; 826 } 827 break; 828 case DEFAULT_PITCH: 829 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 830 s->regs.default_pitch = data & 0x3fff; 831 s->regs.default_tile = (data >> 16) & 1; 832 } 833 break; 834 case DEFAULT_SC_BOTTOM_RIGHT: 835 s->regs.default_sc_bottom_right = data & 0x3fff3fff; 836 break; 837 default: 838 break; 839 } 840 } 841 842 static const MemoryRegionOps ati_mm_ops = { 843 .read = ati_mm_read, 844 .write = ati_mm_write, 845 .endianness = DEVICE_LITTLE_ENDIAN, 846 }; 847 848 static void ati_vga_realize(PCIDevice *dev, Error **errp) 849 { 850 ATIVGAState *s = ATI_VGA(dev); 851 VGACommonState *vga = &s->vga; 852 853 if (s->model) { 854 int i; 855 for (i = 0; i < ARRAY_SIZE(ati_model_aliases); i++) { 856 if (!strcmp(s->model, ati_model_aliases[i].name)) { 857 s->dev_id = ati_model_aliases[i].dev_id; 858 break; 859 } 860 } 861 if (i >= ARRAY_SIZE(ati_model_aliases)) { 862 warn_report("Unknown ATI VGA model name, " 863 "using default rage128p"); 864 } 865 } 866 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF && 867 s->dev_id != PCI_DEVICE_ID_ATI_RADEON_QY) { 868 error_setg(errp, "Unknown ATI VGA device id, " 869 "only 0x5046 and 0x5159 are supported"); 870 return; 871 } 872 pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id); 873 874 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY && 875 s->vga.vram_size_mb < 16) { 876 warn_report("Too small video memory for device id"); 877 s->vga.vram_size_mb = 16; 878 } 879 880 /* init vga bits */ 881 vga_common_init(vga, OBJECT(s)); 882 vga_init(vga, OBJECT(s), pci_address_space(dev), 883 pci_address_space_io(dev), true); 884 vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga); 885 if (s->cursor_guest_mode) { 886 vga->cursor_invalidate = ati_cursor_invalidate; 887 vga->cursor_draw_line = ati_cursor_draw_line; 888 } 889 890 /* ddc, edid */ 891 I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc"); 892 bitbang_i2c_init(&s->bbi2c, i2cbus); 893 I2CSlave *i2cddc = I2C_SLAVE(qdev_create(BUS(i2cbus), TYPE_I2CDDC)); 894 i2c_set_slave_address(i2cddc, 0x50); 895 896 /* mmio register space */ 897 memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s, 898 "ati.mmregs", 0x4000); 899 /* io space is alias to beginning of mmregs */ 900 memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100); 901 902 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); 903 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io); 904 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm); 905 } 906 907 static void ati_vga_reset(DeviceState *dev) 908 { 909 ATIVGAState *s = ATI_VGA(dev); 910 911 /* reset vga */ 912 vga_common_reset(&s->vga); 913 s->mode = VGA_MODE; 914 } 915 916 static void ati_vga_exit(PCIDevice *dev) 917 { 918 ATIVGAState *s = ATI_VGA(dev); 919 920 graphic_console_close(s->vga.con); 921 } 922 923 static Property ati_vga_properties[] = { 924 DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState, vga.vram_size_mb, 16), 925 DEFINE_PROP_STRING("model", ATIVGAState, model), 926 DEFINE_PROP_UINT16("x-device-id", ATIVGAState, dev_id, 927 PCI_DEVICE_ID_ATI_RAGE128_PF), 928 DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState, cursor_guest_mode, false), 929 DEFINE_PROP_END_OF_LIST() 930 }; 931 932 static void ati_vga_class_init(ObjectClass *klass, void *data) 933 { 934 DeviceClass *dc = DEVICE_CLASS(klass); 935 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 936 937 dc->reset = ati_vga_reset; 938 dc->props = ati_vga_properties; 939 dc->hotpluggable = false; 940 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 941 942 k->class_id = PCI_CLASS_DISPLAY_VGA; 943 k->vendor_id = PCI_VENDOR_ID_ATI; 944 k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF; 945 k->romfile = "vgabios-ati.bin"; 946 k->realize = ati_vga_realize; 947 k->exit = ati_vga_exit; 948 } 949 950 static const TypeInfo ati_vga_info = { 951 .name = TYPE_ATI_VGA, 952 .parent = TYPE_PCI_DEVICE, 953 .instance_size = sizeof(ATIVGAState), 954 .class_init = ati_vga_class_init, 955 .interfaces = (InterfaceInfo[]) { 956 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 957 { }, 958 }, 959 }; 960 961 static void ati_vga_register_types(void) 962 { 963 type_register_static(&ati_vga_info); 964 } 965 966 type_init(ati_vga_register_types) 967