1 /* 2 * CXL Utility library for components 3 * 4 * Copyright(C) 2020 Intel Corporation. 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "hw/pci/pci.h" 14 #include "hw/cxl/cxl.h" 15 16 int cxl_decoder_count_enc(int count) 17 { 18 switch (count) { 19 case 1: return 0; 20 case 2: return 1; 21 case 4: return 2; 22 case 6: return 3; 23 case 8: return 4; 24 case 10: return 5; 25 } 26 return 0; 27 } 28 29 hwaddr cxl_decode_ig(int ig) 30 { 31 return 1ULL << (ig + 8); 32 } 33 34 static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset, 35 unsigned size) 36 { 37 CXLComponentState *cxl_cstate = opaque; 38 ComponentRegisters *cregs = &cxl_cstate->crb; 39 40 if (size == 8) { 41 qemu_log_mask(LOG_UNIMP, 42 "CXL 8 byte cache mem registers not implemented\n"); 43 return 0; 44 } 45 46 if (cregs->special_ops && cregs->special_ops->read) { 47 return cregs->special_ops->read(cxl_cstate, offset, size); 48 } else { 49 return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)]; 50 } 51 } 52 53 static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, 54 uint32_t value) 55 { 56 ComponentRegisters *cregs = &cxl_cstate->crb; 57 uint32_t *cache_mem = cregs->cache_mem_registers; 58 bool should_commit = false; 59 bool should_uncommit = false; 60 61 switch (offset) { 62 case A_CXL_HDM_DECODER0_CTRL: 63 should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT); 64 should_uncommit = !should_commit; 65 break; 66 default: 67 break; 68 } 69 70 if (should_commit) { 71 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); 72 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); 73 } else if (should_uncommit) { 74 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); 75 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0); 76 } 77 stl_le_p((uint8_t *)cache_mem + offset, value); 78 } 79 80 static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value, 81 unsigned size) 82 { 83 CXLComponentState *cxl_cstate = opaque; 84 ComponentRegisters *cregs = &cxl_cstate->crb; 85 uint32_t mask; 86 87 if (size == 8) { 88 qemu_log_mask(LOG_UNIMP, 89 "CXL 8 byte cache mem registers not implemented\n"); 90 return; 91 } 92 mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)]; 93 value &= mask; 94 /* RO bits should remain constant. Done by reading existing value */ 95 value |= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)]; 96 if (cregs->special_ops && cregs->special_ops->write) { 97 cregs->special_ops->write(cxl_cstate, offset, value, size); 98 return; 99 } 100 101 if (offset >= A_CXL_HDM_DECODER_CAPABILITY && 102 offset <= A_CXL_HDM_DECODER0_TARGET_LIST_HI) { 103 dumb_hdm_handler(cxl_cstate, offset, value); 104 } else { 105 cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value; 106 } 107 } 108 109 /* 110 * 8.2.3 111 * The access restrictions specified in Section 8.2.2 also apply to CXL 2.0 112 * Component Registers. 113 * 114 * 8.2.2 115 * • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial 116 * reads are not permitted. 117 * • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial 118 * reads are not permitted. 119 * 120 * As of the spec defined today, only 4 byte registers exist. 121 */ 122 static const MemoryRegionOps cache_mem_ops = { 123 .read = cxl_cache_mem_read_reg, 124 .write = cxl_cache_mem_write_reg, 125 .endianness = DEVICE_LITTLE_ENDIAN, 126 .valid = { 127 .min_access_size = 4, 128 .max_access_size = 8, 129 .unaligned = false, 130 }, 131 .impl = { 132 .min_access_size = 4, 133 .max_access_size = 8, 134 }, 135 }; 136 137 void cxl_component_register_block_init(Object *obj, 138 CXLComponentState *cxl_cstate, 139 const char *type) 140 { 141 ComponentRegisters *cregs = &cxl_cstate->crb; 142 143 memory_region_init(&cregs->component_registers, obj, type, 144 CXL2_COMPONENT_BLOCK_SIZE); 145 146 /* io registers controls link which we don't care about in QEMU */ 147 memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io", 148 CXL2_COMPONENT_IO_REGION_SIZE); 149 memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, 150 ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); 151 152 memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io); 153 memory_region_add_subregion(&cregs->component_registers, 154 CXL2_COMPONENT_IO_REGION_SIZE, 155 &cregs->cache_mem); 156 } 157 158 static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) 159 { 160 /* 161 * Error status is RW1C but given bits are not yet set, it can 162 * be handled as RO. 163 */ 164 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); 165 stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff); 166 /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ 167 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); 168 stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); 169 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); 170 stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); 171 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); 172 stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f); 173 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); 174 stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); 175 /* CXL switches and devices must set */ 176 stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200); 177 } 178 179 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, 180 enum reg_type type) 181 { 182 int decoder_count = 1; 183 int i; 184 185 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 186 cxl_decoder_count_enc(decoder_count)); 187 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1); 188 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1); 189 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1); 190 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0); 191 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, 192 HDM_DECODER_ENABLE, 0); 193 write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3; 194 for (i = 0; i < decoder_count; i++) { 195 write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * 0x20] = 0xf0000000; 196 write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * 0x20] = 0xffffffff; 197 write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000; 198 write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff; 199 write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; 200 if (type == CXL2_DEVICE || 201 type == CXL2_TYPE3_DEVICE || 202 type == CXL2_LOGICAL_DEVICE) { 203 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000; 204 } else { 205 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff; 206 } 207 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff; 208 } 209 } 210 211 void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk, 212 enum reg_type type) 213 { 214 int caps = 0; 215 216 /* 217 * In CXL 2.0 the capabilities required for each CXL component are such that, 218 * with the ordering chosen here, a single number can be used to define 219 * which capabilities should be provided. 220 */ 221 switch (type) { 222 case CXL2_DOWNSTREAM_PORT: 223 case CXL2_DEVICE: 224 /* RAS, Link */ 225 caps = 2; 226 break; 227 case CXL2_UPSTREAM_PORT: 228 case CXL2_TYPE3_DEVICE: 229 case CXL2_LOGICAL_DEVICE: 230 /* + HDM */ 231 caps = 3; 232 break; 233 case CXL2_ROOT_PORT: 234 /* + Extended Security, + Snoop */ 235 caps = 5; 236 break; 237 default: 238 abort(); 239 } 240 241 memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE); 242 243 /* CXL Capability Header Register */ 244 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1); 245 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1); 246 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1); 247 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); 248 249 #define init_cap_reg(reg, id, version) \ 250 QEMU_BUILD_BUG_ON(CXL_##reg##_REGISTERS_OFFSET == 0); \ 251 do { \ 252 int which = R_CXL_##reg##_CAPABILITY_HEADER; \ 253 reg_state[which] = FIELD_DP32(reg_state[which], \ 254 CXL_##reg##_CAPABILITY_HEADER, ID, id); \ 255 reg_state[which] = \ 256 FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, \ 257 VERSION, version); \ 258 reg_state[which] = \ 259 FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR, \ 260 CXL_##reg##_REGISTERS_OFFSET); \ 261 } while (0) 262 263 init_cap_reg(RAS, 2, 2); 264 ras_init_common(reg_state, write_msk); 265 266 init_cap_reg(LINK, 4, 2); 267 268 if (caps < 3) { 269 return; 270 } 271 272 init_cap_reg(HDM, 5, 1); 273 hdm_init_common(reg_state, write_msk, type); 274 275 if (caps < 5) { 276 return; 277 } 278 279 init_cap_reg(EXTSEC, 6, 1); 280 init_cap_reg(SNOOP, 8, 1); 281 282 #undef init_cap_reg 283 } 284 285 /* 286 * Helper to creates a DVSEC header for a CXL entity. The caller is responsible 287 * for tracking the valid offset. 288 * 289 * This function will build the DVSEC header on behalf of the caller and then 290 * copy in the remaining data for the vendor specific bits. 291 * It will also set up appropriate write masks. 292 */ 293 void cxl_component_create_dvsec(CXLComponentState *cxl, 294 enum reg_type cxl_dev_type, uint16_t length, 295 uint16_t type, uint8_t rev, uint8_t *body) 296 { 297 PCIDevice *pdev = cxl->pdev; 298 uint16_t offset = cxl->dvsec_offset; 299 uint8_t *wmask = pdev->wmask; 300 301 assert(offset >= PCI_CFG_SPACE_SIZE && 302 ((offset + length) < PCI_CFG_SPACE_EXP_SIZE)); 303 assert((length & 0xf000) == 0); 304 assert((rev & ~0xf) == 0); 305 306 /* Create the DVSEC in the MCFG space */ 307 pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length); 308 pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET, 309 (length << 20) | (rev << 16) | CXL_VENDOR_ID); 310 pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type); 311 memcpy(pdev->config + offset + sizeof(DVSECHeader), 312 body + sizeof(DVSECHeader), 313 length - sizeof(DVSECHeader)); 314 315 /* Configure write masks */ 316 switch (type) { 317 case PCIE_CXL_DEVICE_DVSEC: 318 /* Cntrl RW Lock - so needs explicit blocking when lock is set */ 319 wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD; 320 wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F; 321 /* Status is RW1CS */ 322 wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F; 323 /* Lock is RW Once */ 324 wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01; 325 /* range1/2_base_high/low is RW Lock */ 326 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF; 327 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF; 328 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF; 329 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF; 330 wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0; 331 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF; 332 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF; 333 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF; 334 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF; 335 wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0; 336 break; 337 case NON_CXL_FUNCTION_MAP_DVSEC: 338 break; /* Not yet implemented */ 339 case EXTENSIONS_PORT_DVSEC: 340 wmask[offset + offsetof(CXLDVSECPortExtensions, control)] = 0x0F; 341 wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] = 0x40; 342 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] = 0xFF; 343 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = 0xFF; 344 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = 0xF0; 345 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) + 1] = 0xFF; 346 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)] = 0xF0; 347 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) + 1] = 0xFF; 348 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)] = 0xF0; 349 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base) + 1] = 0xFF; 350 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit)] = 0xF0; 351 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit) + 1] = 0xFF; 352 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high)] = 0xFF; 353 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 1] = 0xFF; 354 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 2] = 0xFF; 355 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 3] = 0xFF; 356 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high)] = 0xFF; 357 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 1] = 0xFF; 358 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 2] = 0xFF; 359 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 3] = 0xFF; 360 break; 361 case GPF_PORT_DVSEC: 362 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F; 363 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F; 364 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F; 365 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F; 366 break; 367 case GPF_DEVICE_DVSEC: 368 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F; 369 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F; 370 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF; 371 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF; 372 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF; 373 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF; 374 break; 375 case PCIE_FLEXBUS_PORT_DVSEC: 376 switch (cxl_dev_type) { 377 case CXL2_ROOT_PORT: 378 /* No MLD */ 379 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd; 380 break; 381 case CXL2_DOWNSTREAM_PORT: 382 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd; 383 break; 384 default: /* Registers are RO for other component types */ 385 break; 386 } 387 /* There are rw1cs bits in the status register but never set currently */ 388 break; 389 } 390 391 /* Update state for future DVSEC additions */ 392 range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length); 393 cxl->dvsec_offset += length; 394 } 395 396 uint8_t cxl_interleave_ways_enc(int iw, Error **errp) 397 { 398 switch (iw) { 399 case 1: return 0x0; 400 case 2: return 0x1; 401 case 4: return 0x2; 402 case 8: return 0x3; 403 case 16: return 0x4; 404 case 3: return 0x8; 405 case 6: return 0x9; 406 case 12: return 0xa; 407 default: 408 error_setg(errp, "Interleave ways: %d not supported", iw); 409 return 0; 410 } 411 } 412 413 uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp) 414 { 415 switch (gran) { 416 case 256: return 0; 417 case 512: return 1; 418 case 1024: return 2; 419 case 2048: return 3; 420 case 4096: return 4; 421 case 8192: return 5; 422 case 16384: return 6; 423 default: 424 error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran); 425 return 0; 426 } 427 } 428