1 /* 2 * CXL Utility library for components 3 * 4 * Copyright(C) 2020 Intel Corporation. 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "hw/pci/pci.h" 14 #include "hw/cxl/cxl.h" 15 16 /* CXL r3.0 Section 8.2.4.19.1 CXL HDM Decoder Capability Register */ 17 int cxl_decoder_count_enc(int count) 18 { 19 switch (count) { 20 case 1: return 0x0; 21 case 2: return 0x1; 22 case 4: return 0x2; 23 case 6: return 0x3; 24 case 8: return 0x4; 25 case 10: return 0x5; 26 /* Switches and Host Bridges may have more than 10 decoders */ 27 case 12: return 0x6; 28 case 14: return 0x7; 29 case 16: return 0x8; 30 case 20: return 0x9; 31 case 24: return 0xa; 32 case 28: return 0xb; 33 case 32: return 0xc; 34 } 35 return 0; 36 } 37 38 int cxl_decoder_count_dec(int enc_cnt) 39 { 40 switch (enc_cnt) { 41 case 0x0: return 1; 42 case 0x1: return 2; 43 case 0x2: return 4; 44 case 0x3: return 6; 45 case 0x4: return 8; 46 case 0x5: return 10; 47 /* Switches and Host Bridges may have more than 10 decoders */ 48 case 0x6: return 12; 49 case 0x7: return 14; 50 case 0x8: return 16; 51 case 0x9: return 20; 52 case 0xa: return 24; 53 case 0xb: return 28; 54 case 0xc: return 32; 55 } 56 return 0; 57 } 58 59 hwaddr cxl_decode_ig(int ig) 60 { 61 return 1ULL << (ig + 8); 62 } 63 64 static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset, 65 unsigned size) 66 { 67 CXLComponentState *cxl_cstate = opaque; 68 ComponentRegisters *cregs = &cxl_cstate->crb; 69 70 if (size == 8) { 71 qemu_log_mask(LOG_UNIMP, 72 "CXL 8 byte cache mem registers not implemented\n"); 73 return 0; 74 } 75 76 if (cregs->special_ops && cregs->special_ops->read) { 77 return cregs->special_ops->read(cxl_cstate, offset, size); 78 } else { 79 return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)]; 80 } 81 } 82 83 static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, 84 uint32_t value) 85 { 86 ComponentRegisters *cregs = &cxl_cstate->crb; 87 uint32_t *cache_mem = cregs->cache_mem_registers; 88 bool should_commit = false; 89 bool should_uncommit = false; 90 91 switch (offset) { 92 case A_CXL_HDM_DECODER0_CTRL: 93 should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT); 94 should_uncommit = !should_commit; 95 break; 96 default: 97 break; 98 } 99 100 if (should_commit) { 101 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); 102 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); 103 } else if (should_uncommit) { 104 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); 105 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0); 106 } 107 stl_le_p((uint8_t *)cache_mem + offset, value); 108 } 109 110 static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value, 111 unsigned size) 112 { 113 CXLComponentState *cxl_cstate = opaque; 114 ComponentRegisters *cregs = &cxl_cstate->crb; 115 uint32_t mask; 116 117 if (size == 8) { 118 qemu_log_mask(LOG_UNIMP, 119 "CXL 8 byte cache mem registers not implemented\n"); 120 return; 121 } 122 mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)]; 123 value &= mask; 124 /* RO bits should remain constant. Done by reading existing value */ 125 value |= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)]; 126 if (cregs->special_ops && cregs->special_ops->write) { 127 cregs->special_ops->write(cxl_cstate, offset, value, size); 128 return; 129 } 130 131 if (offset >= A_CXL_HDM_DECODER_CAPABILITY && 132 offset <= A_CXL_HDM_DECODER0_TARGET_LIST_HI) { 133 dumb_hdm_handler(cxl_cstate, offset, value); 134 } else { 135 cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value; 136 } 137 } 138 139 /* 140 * 8.2.3 141 * The access restrictions specified in Section 8.2.2 also apply to CXL 2.0 142 * Component Registers. 143 * 144 * 8.2.2 145 * • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial 146 * reads are not permitted. 147 * • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial 148 * reads are not permitted. 149 * 150 * As of the spec defined today, only 4 byte registers exist. 151 */ 152 static const MemoryRegionOps cache_mem_ops = { 153 .read = cxl_cache_mem_read_reg, 154 .write = cxl_cache_mem_write_reg, 155 .endianness = DEVICE_LITTLE_ENDIAN, 156 .valid = { 157 .min_access_size = 4, 158 .max_access_size = 8, 159 .unaligned = false, 160 }, 161 .impl = { 162 .min_access_size = 4, 163 .max_access_size = 8, 164 }, 165 }; 166 167 void cxl_component_register_block_init(Object *obj, 168 CXLComponentState *cxl_cstate, 169 const char *type) 170 { 171 ComponentRegisters *cregs = &cxl_cstate->crb; 172 173 memory_region_init(&cregs->component_registers, obj, type, 174 CXL2_COMPONENT_BLOCK_SIZE); 175 176 /* io registers controls link which we don't care about in QEMU */ 177 memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io", 178 CXL2_COMPONENT_IO_REGION_SIZE); 179 memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, 180 ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); 181 182 memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io); 183 memory_region_add_subregion(&cregs->component_registers, 184 CXL2_COMPONENT_IO_REGION_SIZE, 185 &cregs->cache_mem); 186 } 187 188 static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) 189 { 190 /* 191 * Error status is RW1C but given bits are not yet set, it can 192 * be handled as RO. 193 */ 194 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); 195 stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff); 196 /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ 197 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); 198 stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); 199 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); 200 stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); 201 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); 202 stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f); 203 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); 204 stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); 205 /* CXL switches and devices must set */ 206 stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200); 207 } 208 209 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, 210 enum reg_type type) 211 { 212 int decoder_count = 1; 213 int i; 214 215 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 216 cxl_decoder_count_enc(decoder_count)); 217 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1); 218 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1); 219 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1); 220 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0); 221 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, 222 HDM_DECODER_ENABLE, 0); 223 write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3; 224 for (i = 0; i < decoder_count; i++) { 225 write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * 0x20] = 0xf0000000; 226 write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * 0x20] = 0xffffffff; 227 write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000; 228 write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff; 229 write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; 230 if (type == CXL2_DEVICE || 231 type == CXL2_TYPE3_DEVICE || 232 type == CXL2_LOGICAL_DEVICE) { 233 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000; 234 } else { 235 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff; 236 } 237 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff; 238 } 239 } 240 241 void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk, 242 enum reg_type type) 243 { 244 int caps = 0; 245 246 /* 247 * In CXL 2.0 the capabilities required for each CXL component are such that, 248 * with the ordering chosen here, a single number can be used to define 249 * which capabilities should be provided. 250 */ 251 switch (type) { 252 case CXL2_DOWNSTREAM_PORT: 253 case CXL2_DEVICE: 254 /* RAS, Link */ 255 caps = 2; 256 break; 257 case CXL2_UPSTREAM_PORT: 258 case CXL2_TYPE3_DEVICE: 259 case CXL2_LOGICAL_DEVICE: 260 /* + HDM */ 261 caps = 3; 262 break; 263 case CXL2_ROOT_PORT: 264 /* + Extended Security, + Snoop */ 265 caps = 5; 266 break; 267 default: 268 abort(); 269 } 270 271 memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE); 272 273 /* CXL Capability Header Register */ 274 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1); 275 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1); 276 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1); 277 ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); 278 279 #define init_cap_reg(reg, id, version) \ 280 QEMU_BUILD_BUG_ON(CXL_##reg##_REGISTERS_OFFSET == 0); \ 281 do { \ 282 int which = R_CXL_##reg##_CAPABILITY_HEADER; \ 283 reg_state[which] = FIELD_DP32(reg_state[which], \ 284 CXL_##reg##_CAPABILITY_HEADER, ID, id); \ 285 reg_state[which] = \ 286 FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, \ 287 VERSION, version); \ 288 reg_state[which] = \ 289 FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR, \ 290 CXL_##reg##_REGISTERS_OFFSET); \ 291 } while (0) 292 293 init_cap_reg(RAS, 2, 2); 294 ras_init_common(reg_state, write_msk); 295 296 init_cap_reg(LINK, 4, 2); 297 298 if (caps < 3) { 299 return; 300 } 301 302 init_cap_reg(HDM, 5, 1); 303 hdm_init_common(reg_state, write_msk, type); 304 305 if (caps < 5) { 306 return; 307 } 308 309 init_cap_reg(EXTSEC, 6, 1); 310 init_cap_reg(SNOOP, 8, 1); 311 312 #undef init_cap_reg 313 } 314 315 /* 316 * Helper to creates a DVSEC header for a CXL entity. The caller is responsible 317 * for tracking the valid offset. 318 * 319 * This function will build the DVSEC header on behalf of the caller and then 320 * copy in the remaining data for the vendor specific bits. 321 * It will also set up appropriate write masks. 322 */ 323 void cxl_component_create_dvsec(CXLComponentState *cxl, 324 enum reg_type cxl_dev_type, uint16_t length, 325 uint16_t type, uint8_t rev, uint8_t *body) 326 { 327 PCIDevice *pdev = cxl->pdev; 328 uint16_t offset = cxl->dvsec_offset; 329 uint8_t *wmask = pdev->wmask; 330 331 assert(offset >= PCI_CFG_SPACE_SIZE && 332 ((offset + length) < PCI_CFG_SPACE_EXP_SIZE)); 333 assert((length & 0xf000) == 0); 334 assert((rev & ~0xf) == 0); 335 336 /* Create the DVSEC in the MCFG space */ 337 pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length); 338 pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET, 339 (length << 20) | (rev << 16) | CXL_VENDOR_ID); 340 pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type); 341 memcpy(pdev->config + offset + sizeof(DVSECHeader), 342 body + sizeof(DVSECHeader), 343 length - sizeof(DVSECHeader)); 344 345 /* Configure write masks */ 346 switch (type) { 347 case PCIE_CXL_DEVICE_DVSEC: 348 /* Cntrl RW Lock - so needs explicit blocking when lock is set */ 349 wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD; 350 wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F; 351 /* Status is RW1CS */ 352 wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F; 353 /* Lock is RW Once */ 354 wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01; 355 /* range1/2_base_high/low is RW Lock */ 356 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF; 357 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF; 358 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF; 359 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF; 360 wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0; 361 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF; 362 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF; 363 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF; 364 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF; 365 wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0; 366 break; 367 case NON_CXL_FUNCTION_MAP_DVSEC: 368 break; /* Not yet implemented */ 369 case EXTENSIONS_PORT_DVSEC: 370 wmask[offset + offsetof(CXLDVSECPortExtensions, control)] = 0x0F; 371 wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] = 0x40; 372 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] = 0xFF; 373 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = 0xFF; 374 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = 0xF0; 375 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) + 1] = 0xFF; 376 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)] = 0xF0; 377 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) + 1] = 0xFF; 378 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)] = 0xF0; 379 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base) + 1] = 0xFF; 380 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit)] = 0xF0; 381 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit) + 1] = 0xFF; 382 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high)] = 0xFF; 383 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 1] = 0xFF; 384 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 2] = 0xFF; 385 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 3] = 0xFF; 386 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high)] = 0xFF; 387 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 1] = 0xFF; 388 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 2] = 0xFF; 389 wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 3] = 0xFF; 390 break; 391 case GPF_PORT_DVSEC: 392 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F; 393 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F; 394 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F; 395 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F; 396 break; 397 case GPF_DEVICE_DVSEC: 398 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F; 399 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F; 400 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF; 401 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF; 402 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF; 403 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF; 404 break; 405 case PCIE_FLEXBUS_PORT_DVSEC: 406 switch (cxl_dev_type) { 407 case CXL2_ROOT_PORT: 408 /* No MLD */ 409 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd; 410 break; 411 case CXL2_DOWNSTREAM_PORT: 412 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd; 413 break; 414 default: /* Registers are RO for other component types */ 415 break; 416 } 417 /* There are rw1cs bits in the status register but never set currently */ 418 break; 419 } 420 421 /* Update state for future DVSEC additions */ 422 range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length); 423 cxl->dvsec_offset += length; 424 } 425 426 /* CXL r3.0 Section 8.2.4.19.7 CXL HDM Decoder n Control Register */ 427 uint8_t cxl_interleave_ways_enc(int iw, Error **errp) 428 { 429 switch (iw) { 430 case 1: return 0x0; 431 case 2: return 0x1; 432 case 4: return 0x2; 433 case 8: return 0x3; 434 case 16: return 0x4; 435 case 3: return 0x8; 436 case 6: return 0x9; 437 case 12: return 0xa; 438 default: 439 error_setg(errp, "Interleave ways: %d not supported", iw); 440 return 0; 441 } 442 } 443 444 int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp) 445 { 446 switch (iw_enc) { 447 case 0x0: return 1; 448 case 0x1: return 2; 449 case 0x2: return 4; 450 case 0x3: return 8; 451 case 0x4: return 16; 452 case 0x8: return 3; 453 case 0x9: return 6; 454 case 0xa: return 12; 455 default: 456 error_setg(errp, "Encoded interleave ways: %d not supported", iw_enc); 457 return 0; 458 } 459 } 460 461 uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp) 462 { 463 switch (gran) { 464 case 256: return 0; 465 case 512: return 1; 466 case 1024: return 2; 467 case 2048: return 3; 468 case 4096: return 4; 469 case 8192: return 5; 470 case 16384: return 6; 471 default: 472 error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran); 473 return 0; 474 } 475 } 476