xref: /qemu/hw/core/machine.c (revision da7e13c00b5962016b9c72079bef5e0a5398db0d)
1 /*
2  * QEMU Machine
3  *
4  * Copyright (C) 2014 Red Hat Inc
5  *
6  * Authors:
7  *   Marcel Apfelbaum <marcel.a@redhat.com>
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  */
12 
13 #include "qemu/osdep.h"
14 #include "qemu/option.h"
15 #include "qapi/qmp/qerror.h"
16 #include "sysemu/replay.h"
17 #include "qemu/units.h"
18 #include "hw/boards.h"
19 #include "hw/loader.h"
20 #include "qapi/error.h"
21 #include "qapi/qapi-visit-common.h"
22 #include "qapi/visitor.h"
23 #include "hw/sysbus.h"
24 #include "sysemu/cpus.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/numa.h"
29 #include "qemu/error-report.h"
30 #include "sysemu/qtest.h"
31 #include "hw/pci/pci.h"
32 #include "hw/mem/nvdimm.h"
33 #include "migration/global_state.h"
34 #include "migration/vmstate.h"
35 #include "exec/confidential-guest-support.h"
36 #include "hw/virtio/virtio.h"
37 #include "hw/virtio/virtio-pci.h"
38 
39 GlobalProperty hw_compat_6_0[] = {};
40 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0);
41 
42 GlobalProperty hw_compat_5_2[] = {
43     { "ICH9-LPC", "smm-compat", "on"},
44     { "PIIX4_PM", "smm-compat", "on"},
45     { "virtio-blk-device", "report-discard-granularity", "off" },
46     { "virtio-net-pci", "vectors", "3"},
47 };
48 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2);
49 
50 GlobalProperty hw_compat_5_1[] = {
51     { "vhost-scsi", "num_queues", "1"},
52     { "vhost-user-blk", "num-queues", "1"},
53     { "vhost-user-scsi", "num_queues", "1"},
54     { "virtio-blk-device", "num-queues", "1"},
55     { "virtio-scsi-device", "num_queues", "1"},
56     { "nvme", "use-intel-id", "on"},
57     { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
58     { "pl011", "migrate-clk", "off" },
59     { "virtio-pci", "x-ats-page-aligned", "off"},
60 };
61 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
62 
63 GlobalProperty hw_compat_5_0[] = {
64     { "pci-host-bridge", "x-config-reg-migration-enabled", "off" },
65     { "virtio-balloon-device", "page-poison", "false" },
66     { "vmport", "x-read-set-eax", "off" },
67     { "vmport", "x-signal-unsupported-cmd", "off" },
68     { "vmport", "x-report-vmx-type", "off" },
69     { "vmport", "x-cmds-v2", "off" },
70     { "virtio-device", "x-disable-legacy-check", "true" },
71 };
72 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0);
73 
74 GlobalProperty hw_compat_4_2[] = {
75     { "virtio-blk-device", "queue-size", "128"},
76     { "virtio-scsi-device", "virtqueue_size", "128"},
77     { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" },
78     { "virtio-blk-device", "seg-max-adjust", "off"},
79     { "virtio-scsi-device", "seg_max_adjust", "off"},
80     { "vhost-blk-device", "seg_max_adjust", "off"},
81     { "usb-host", "suppress-remote-wake", "off" },
82     { "usb-redir", "suppress-remote-wake", "off" },
83     { "qxl", "revision", "4" },
84     { "qxl-vga", "revision", "4" },
85     { "fw_cfg", "acpi-mr-restore", "false" },
86     { "virtio-device", "use-disabled-flag", "false" },
87 };
88 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2);
89 
90 GlobalProperty hw_compat_4_1[] = {
91     { "virtio-pci", "x-pcie-flr-init", "off" },
92 };
93 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1);
94 
95 GlobalProperty hw_compat_4_0[] = {
96     { "VGA",            "edid", "false" },
97     { "secondary-vga",  "edid", "false" },
98     { "bochs-display",  "edid", "false" },
99     { "virtio-vga",     "edid", "false" },
100     { "virtio-gpu-device", "edid", "false" },
101     { "virtio-device", "use-started", "false" },
102     { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
103     { "pl031", "migrate-tick-offset", "false" },
104 };
105 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
106 
107 GlobalProperty hw_compat_3_1[] = {
108     { "pcie-root-port", "x-speed", "2_5" },
109     { "pcie-root-port", "x-width", "1" },
110     { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
111     { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
112     { "tpm-crb", "ppi", "false" },
113     { "tpm-tis", "ppi", "false" },
114     { "usb-kbd", "serial", "42" },
115     { "usb-mouse", "serial", "42" },
116     { "usb-tablet", "serial", "42" },
117     { "virtio-blk-device", "discard", "false" },
118     { "virtio-blk-device", "write-zeroes", "false" },
119     { "virtio-balloon-device", "qemu-4-0-config-size", "false" },
120     { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */
121 };
122 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1);
123 
124 GlobalProperty hw_compat_3_0[] = {};
125 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0);
126 
127 GlobalProperty hw_compat_2_12[] = {
128     { "migration", "decompress-error-check", "off" },
129     { "hda-audio", "use-timer", "false" },
130     { "cirrus-vga", "global-vmstate", "true" },
131     { "VGA", "global-vmstate", "true" },
132     { "vmware-svga", "global-vmstate", "true" },
133     { "qxl-vga", "global-vmstate", "true" },
134 };
135 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12);
136 
137 GlobalProperty hw_compat_2_11[] = {
138     { "hpet", "hpet-offset-saved", "false" },
139     { "virtio-blk-pci", "vectors", "2" },
140     { "vhost-user-blk-pci", "vectors", "2" },
141     { "e1000", "migrate_tso_props", "off" },
142 };
143 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11);
144 
145 GlobalProperty hw_compat_2_10[] = {
146     { "virtio-mouse-device", "wheel-axis", "false" },
147     { "virtio-tablet-device", "wheel-axis", "false" },
148 };
149 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10);
150 
151 GlobalProperty hw_compat_2_9[] = {
152     { "pci-bridge", "shpc", "off" },
153     { "intel-iommu", "pt", "off" },
154     { "virtio-net-device", "x-mtu-bypass-backend", "off" },
155     { "pcie-root-port", "x-migrate-msix", "false" },
156 };
157 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9);
158 
159 GlobalProperty hw_compat_2_8[] = {
160     { "fw_cfg_mem", "x-file-slots", "0x10" },
161     { "fw_cfg_io", "x-file-slots", "0x10" },
162     { "pflash_cfi01", "old-multiple-chip-handling", "on" },
163     { "pci-bridge", "shpc", "on" },
164     { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" },
165     { "virtio-pci", "x-pcie-deverr-init", "off" },
166     { "virtio-pci", "x-pcie-lnkctl-init", "off" },
167     { "virtio-pci", "x-pcie-pm-init", "off" },
168     { "cirrus-vga", "vgamem_mb", "8" },
169     { "isa-cirrus-vga", "vgamem_mb", "8" },
170 };
171 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8);
172 
173 GlobalProperty hw_compat_2_7[] = {
174     { "virtio-pci", "page-per-vq", "on" },
175     { "virtio-serial-device", "emergency-write", "off" },
176     { "ioapic", "version", "0x11" },
177     { "intel-iommu", "x-buggy-eim", "true" },
178     { "virtio-pci", "x-ignore-backend-features", "on" },
179 };
180 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7);
181 
182 GlobalProperty hw_compat_2_6[] = {
183     { "virtio-mmio", "format_transport_address", "off" },
184     /* Optional because not all virtio-pci devices support legacy mode */
185     { "virtio-pci", "disable-modern", "on",  .optional = true },
186     { "virtio-pci", "disable-legacy", "off", .optional = true },
187 };
188 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
189 
190 GlobalProperty hw_compat_2_5[] = {
191     { "isa-fdc", "fallback", "144" },
192     { "pvscsi", "x-old-pci-configuration", "on" },
193     { "pvscsi", "x-disable-pcie", "on" },
194     { "vmxnet3", "x-old-msi-offsets", "on" },
195     { "vmxnet3", "x-disable-pcie", "on" },
196 };
197 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
198 
199 GlobalProperty hw_compat_2_4[] = {
200     /* Optional because the 'scsi' property is Linux-only */
201     { "virtio-blk-device", "scsi", "true", .optional = true },
202     { "e1000", "extra_mac_registers", "off" },
203     { "virtio-pci", "x-disable-pcie", "on" },
204     { "virtio-pci", "migrate-extra", "off" },
205     { "fw_cfg_mem", "dma_enabled", "off" },
206     { "fw_cfg_io", "dma_enabled", "off" }
207 };
208 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
209 
210 GlobalProperty hw_compat_2_3[] = {
211     { "virtio-blk-pci", "any_layout", "off" },
212     { "virtio-balloon-pci", "any_layout", "off" },
213     { "virtio-serial-pci", "any_layout", "off" },
214     { "virtio-9p-pci", "any_layout", "off" },
215     { "virtio-rng-pci", "any_layout", "off" },
216     { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" },
217     { "migration", "send-configuration", "off" },
218     { "migration", "send-section-footer", "off" },
219     { "migration", "store-global-state", "off" },
220 };
221 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3);
222 
223 GlobalProperty hw_compat_2_2[] = {};
224 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
225 
226 GlobalProperty hw_compat_2_1[] = {
227     { "intel-hda", "old_msi_addr", "on" },
228     { "VGA", "qemu-extended-regs", "off" },
229     { "secondary-vga", "qemu-extended-regs", "off" },
230     { "virtio-scsi-pci", "any_layout", "off" },
231     { "usb-mouse", "usb_version", "1" },
232     { "usb-kbd", "usb_version", "1" },
233     { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" },
234 };
235 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1);
236 
237 MachineState *current_machine;
238 
239 static char *machine_get_kernel(Object *obj, Error **errp)
240 {
241     MachineState *ms = MACHINE(obj);
242 
243     return g_strdup(ms->kernel_filename);
244 }
245 
246 static void machine_set_kernel(Object *obj, const char *value, Error **errp)
247 {
248     MachineState *ms = MACHINE(obj);
249 
250     g_free(ms->kernel_filename);
251     ms->kernel_filename = g_strdup(value);
252 }
253 
254 static char *machine_get_initrd(Object *obj, Error **errp)
255 {
256     MachineState *ms = MACHINE(obj);
257 
258     return g_strdup(ms->initrd_filename);
259 }
260 
261 static void machine_set_initrd(Object *obj, const char *value, Error **errp)
262 {
263     MachineState *ms = MACHINE(obj);
264 
265     g_free(ms->initrd_filename);
266     ms->initrd_filename = g_strdup(value);
267 }
268 
269 static char *machine_get_append(Object *obj, Error **errp)
270 {
271     MachineState *ms = MACHINE(obj);
272 
273     return g_strdup(ms->kernel_cmdline);
274 }
275 
276 static void machine_set_append(Object *obj, const char *value, Error **errp)
277 {
278     MachineState *ms = MACHINE(obj);
279 
280     g_free(ms->kernel_cmdline);
281     ms->kernel_cmdline = g_strdup(value);
282 }
283 
284 static char *machine_get_dtb(Object *obj, Error **errp)
285 {
286     MachineState *ms = MACHINE(obj);
287 
288     return g_strdup(ms->dtb);
289 }
290 
291 static void machine_set_dtb(Object *obj, const char *value, Error **errp)
292 {
293     MachineState *ms = MACHINE(obj);
294 
295     g_free(ms->dtb);
296     ms->dtb = g_strdup(value);
297 }
298 
299 static char *machine_get_dumpdtb(Object *obj, Error **errp)
300 {
301     MachineState *ms = MACHINE(obj);
302 
303     return g_strdup(ms->dumpdtb);
304 }
305 
306 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp)
307 {
308     MachineState *ms = MACHINE(obj);
309 
310     g_free(ms->dumpdtb);
311     ms->dumpdtb = g_strdup(value);
312 }
313 
314 static void machine_get_phandle_start(Object *obj, Visitor *v,
315                                       const char *name, void *opaque,
316                                       Error **errp)
317 {
318     MachineState *ms = MACHINE(obj);
319     int64_t value = ms->phandle_start;
320 
321     visit_type_int(v, name, &value, errp);
322 }
323 
324 static void machine_set_phandle_start(Object *obj, Visitor *v,
325                                       const char *name, void *opaque,
326                                       Error **errp)
327 {
328     MachineState *ms = MACHINE(obj);
329     int64_t value;
330 
331     if (!visit_type_int(v, name, &value, errp)) {
332         return;
333     }
334 
335     ms->phandle_start = value;
336 }
337 
338 static char *machine_get_dt_compatible(Object *obj, Error **errp)
339 {
340     MachineState *ms = MACHINE(obj);
341 
342     return g_strdup(ms->dt_compatible);
343 }
344 
345 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp)
346 {
347     MachineState *ms = MACHINE(obj);
348 
349     g_free(ms->dt_compatible);
350     ms->dt_compatible = g_strdup(value);
351 }
352 
353 static bool machine_get_dump_guest_core(Object *obj, Error **errp)
354 {
355     MachineState *ms = MACHINE(obj);
356 
357     return ms->dump_guest_core;
358 }
359 
360 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp)
361 {
362     MachineState *ms = MACHINE(obj);
363 
364     ms->dump_guest_core = value;
365 }
366 
367 static bool machine_get_mem_merge(Object *obj, Error **errp)
368 {
369     MachineState *ms = MACHINE(obj);
370 
371     return ms->mem_merge;
372 }
373 
374 static void machine_set_mem_merge(Object *obj, bool value, Error **errp)
375 {
376     MachineState *ms = MACHINE(obj);
377 
378     ms->mem_merge = value;
379 }
380 
381 static bool machine_get_usb(Object *obj, Error **errp)
382 {
383     MachineState *ms = MACHINE(obj);
384 
385     return ms->usb;
386 }
387 
388 static void machine_set_usb(Object *obj, bool value, Error **errp)
389 {
390     MachineState *ms = MACHINE(obj);
391 
392     ms->usb = value;
393     ms->usb_disabled = !value;
394 }
395 
396 static bool machine_get_graphics(Object *obj, Error **errp)
397 {
398     MachineState *ms = MACHINE(obj);
399 
400     return ms->enable_graphics;
401 }
402 
403 static void machine_set_graphics(Object *obj, bool value, Error **errp)
404 {
405     MachineState *ms = MACHINE(obj);
406 
407     ms->enable_graphics = value;
408 }
409 
410 static char *machine_get_firmware(Object *obj, Error **errp)
411 {
412     MachineState *ms = MACHINE(obj);
413 
414     return g_strdup(ms->firmware);
415 }
416 
417 static void machine_set_firmware(Object *obj, const char *value, Error **errp)
418 {
419     MachineState *ms = MACHINE(obj);
420 
421     g_free(ms->firmware);
422     ms->firmware = g_strdup(value);
423 }
424 
425 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp)
426 {
427     MachineState *ms = MACHINE(obj);
428 
429     ms->suppress_vmdesc = value;
430 }
431 
432 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp)
433 {
434     MachineState *ms = MACHINE(obj);
435 
436     return ms->suppress_vmdesc;
437 }
438 
439 static char *machine_get_memory_encryption(Object *obj, Error **errp)
440 {
441     MachineState *ms = MACHINE(obj);
442 
443     if (ms->cgs) {
444         return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs)));
445     }
446 
447     return NULL;
448 }
449 
450 static void machine_set_memory_encryption(Object *obj, const char *value,
451                                         Error **errp)
452 {
453     Object *cgs =
454         object_resolve_path_component(object_get_objects_root(), value);
455 
456     if (!cgs) {
457         error_setg(errp, "No such memory encryption object '%s'", value);
458         return;
459     }
460 
461     object_property_set_link(obj, "confidential-guest-support", cgs, errp);
462 }
463 
464 static void machine_check_confidential_guest_support(const Object *obj,
465                                                      const char *name,
466                                                      Object *new_target,
467                                                      Error **errp)
468 {
469     /*
470      * So far the only constraint is that the target has the
471      * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked
472      * by the QOM core
473      */
474 }
475 
476 static bool machine_get_nvdimm(Object *obj, Error **errp)
477 {
478     MachineState *ms = MACHINE(obj);
479 
480     return ms->nvdimms_state->is_enabled;
481 }
482 
483 static void machine_set_nvdimm(Object *obj, bool value, Error **errp)
484 {
485     MachineState *ms = MACHINE(obj);
486 
487     ms->nvdimms_state->is_enabled = value;
488 }
489 
490 static bool machine_get_hmat(Object *obj, Error **errp)
491 {
492     MachineState *ms = MACHINE(obj);
493 
494     return ms->numa_state->hmat_enabled;
495 }
496 
497 static void machine_set_hmat(Object *obj, bool value, Error **errp)
498 {
499     MachineState *ms = MACHINE(obj);
500 
501     ms->numa_state->hmat_enabled = value;
502 }
503 
504 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp)
505 {
506     MachineState *ms = MACHINE(obj);
507 
508     return g_strdup(ms->nvdimms_state->persistence_string);
509 }
510 
511 static void machine_set_nvdimm_persistence(Object *obj, const char *value,
512                                            Error **errp)
513 {
514     MachineState *ms = MACHINE(obj);
515     NVDIMMState *nvdimms_state = ms->nvdimms_state;
516 
517     if (strcmp(value, "cpu") == 0) {
518         nvdimms_state->persistence = 3;
519     } else if (strcmp(value, "mem-ctrl") == 0) {
520         nvdimms_state->persistence = 2;
521     } else {
522         error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
523                    value);
524         return;
525     }
526 
527     g_free(nvdimms_state->persistence_string);
528     nvdimms_state->persistence_string = g_strdup(value);
529 }
530 
531 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
532 {
533     QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
534 }
535 
536 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev)
537 {
538     bool allowed = false;
539     strList *wl;
540     Object *obj = OBJECT(dev);
541 
542     if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) {
543         return false;
544     }
545 
546     for (wl = mc->allowed_dynamic_sysbus_devices;
547          !allowed && wl;
548          wl = wl->next) {
549         allowed |= !!object_dynamic_cast(obj, wl->value);
550     }
551 
552     return allowed;
553 }
554 
555 static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque)
556 {
557     MachineState *machine = opaque;
558     MachineClass *mc = MACHINE_GET_CLASS(machine);
559 
560     if (!device_is_dynamic_sysbus(mc, DEVICE(sbdev))) {
561         error_report("Option '-device %s' cannot be handled by this machine",
562                      object_class_get_name(object_get_class(OBJECT(sbdev))));
563         exit(1);
564     }
565 }
566 
567 static char *machine_get_memdev(Object *obj, Error **errp)
568 {
569     MachineState *ms = MACHINE(obj);
570 
571     return g_strdup(ms->ram_memdev_id);
572 }
573 
574 static void machine_set_memdev(Object *obj, const char *value, Error **errp)
575 {
576     MachineState *ms = MACHINE(obj);
577 
578     g_free(ms->ram_memdev_id);
579     ms->ram_memdev_id = g_strdup(value);
580 }
581 
582 
583 static void machine_init_notify(Notifier *notifier, void *data)
584 {
585     MachineState *machine = MACHINE(qdev_get_machine());
586 
587     /*
588      * Loop through all dynamically created sysbus devices and check if they are
589      * all allowed.  If a device is not allowed, error out.
590      */
591     foreach_dynamic_sysbus_device(validate_sysbus_device, machine);
592 }
593 
594 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
595 {
596     int i;
597     HotpluggableCPUList *head = NULL;
598     MachineClass *mc = MACHINE_GET_CLASS(machine);
599 
600     /* force board to initialize possible_cpus if it hasn't been done yet */
601     mc->possible_cpu_arch_ids(machine);
602 
603     for (i = 0; i < machine->possible_cpus->len; i++) {
604         Object *cpu;
605         HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
606 
607         cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type);
608         cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
609         cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
610                                    sizeof(*cpu_item->props));
611 
612         cpu = machine->possible_cpus->cpus[i].cpu;
613         if (cpu) {
614             cpu_item->has_qom_path = true;
615             cpu_item->qom_path = object_get_canonical_path(cpu);
616         }
617         QAPI_LIST_PREPEND(head, cpu_item);
618     }
619     return head;
620 }
621 
622 /**
623  * machine_set_cpu_numa_node:
624  * @machine: machine object to modify
625  * @props: specifies which cpu objects to assign to
626  *         numa node specified by @props.node_id
627  * @errp: if an error occurs, a pointer to an area to store the error
628  *
629  * Associate NUMA node specified by @props.node_id with cpu slots that
630  * match socket/core/thread-ids specified by @props. It's recommended to use
631  * query-hotpluggable-cpus.props values to specify affected cpu slots,
632  * which would lead to exact 1:1 mapping of cpu slots to NUMA node.
633  *
634  * However for CLI convenience it's possible to pass in subset of properties,
635  * which would affect all cpu slots that match it.
636  * Ex for pc machine:
637  *    -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \
638  *    -numa cpu,node-id=0,socket_id=0 \
639  *    -numa cpu,node-id=1,socket_id=1
640  * will assign all child cores of socket 0 to node 0 and
641  * of socket 1 to node 1.
642  *
643  * On attempt of reassigning (already assigned) cpu slot to another NUMA node,
644  * return error.
645  * Empty subset is disallowed and function will return with error in this case.
646  */
647 void machine_set_cpu_numa_node(MachineState *machine,
648                                const CpuInstanceProperties *props, Error **errp)
649 {
650     MachineClass *mc = MACHINE_GET_CLASS(machine);
651     NodeInfo *numa_info = machine->numa_state->nodes;
652     bool match = false;
653     int i;
654 
655     if (!mc->possible_cpu_arch_ids) {
656         error_setg(errp, "mapping of CPUs to NUMA node is not supported");
657         return;
658     }
659 
660     /* disabling node mapping is not supported, forbid it */
661     assert(props->has_node_id);
662 
663     /* force board to initialize possible_cpus if it hasn't been done yet */
664     mc->possible_cpu_arch_ids(machine);
665 
666     for (i = 0; i < machine->possible_cpus->len; i++) {
667         CPUArchId *slot = &machine->possible_cpus->cpus[i];
668 
669         /* reject unsupported by board properties */
670         if (props->has_thread_id && !slot->props.has_thread_id) {
671             error_setg(errp, "thread-id is not supported");
672             return;
673         }
674 
675         if (props->has_core_id && !slot->props.has_core_id) {
676             error_setg(errp, "core-id is not supported");
677             return;
678         }
679 
680         if (props->has_socket_id && !slot->props.has_socket_id) {
681             error_setg(errp, "socket-id is not supported");
682             return;
683         }
684 
685         if (props->has_die_id && !slot->props.has_die_id) {
686             error_setg(errp, "die-id is not supported");
687             return;
688         }
689 
690         /* skip slots with explicit mismatch */
691         if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
692                 continue;
693         }
694 
695         if (props->has_core_id && props->core_id != slot->props.core_id) {
696                 continue;
697         }
698 
699         if (props->has_die_id && props->die_id != slot->props.die_id) {
700                 continue;
701         }
702 
703         if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
704                 continue;
705         }
706 
707         /* reject assignment if slot is already assigned, for compatibility
708          * of legacy cpu_index mapping with SPAPR core based mapping do not
709          * error out if cpu thread and matched core have the same node-id */
710         if (slot->props.has_node_id &&
711             slot->props.node_id != props->node_id) {
712             error_setg(errp, "CPU is already assigned to node-id: %" PRId64,
713                        slot->props.node_id);
714             return;
715         }
716 
717         /* assign slot to node as it's matched '-numa cpu' key */
718         match = true;
719         slot->props.node_id = props->node_id;
720         slot->props.has_node_id = props->has_node_id;
721 
722         if (machine->numa_state->hmat_enabled) {
723             if ((numa_info[props->node_id].initiator < MAX_NODES) &&
724                 (props->node_id != numa_info[props->node_id].initiator)) {
725                 error_setg(errp, "The initiator of CPU NUMA node %" PRId64
726                         " should be itself", props->node_id);
727                 return;
728             }
729             numa_info[props->node_id].has_cpu = true;
730             numa_info[props->node_id].initiator = props->node_id;
731         }
732     }
733 
734     if (!match) {
735         error_setg(errp, "no match found");
736     }
737 }
738 
739 static void smp_parse(MachineState *ms, QemuOpts *opts)
740 {
741     if (opts) {
742         unsigned cpus    = qemu_opt_get_number(opts, "cpus", 0);
743         unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
744         unsigned cores   = qemu_opt_get_number(opts, "cores", 0);
745         unsigned threads = qemu_opt_get_number(opts, "threads", 0);
746 
747         /* compute missing values, prefer sockets over cores over threads */
748         if (cpus == 0 || sockets == 0) {
749             cores = cores > 0 ? cores : 1;
750             threads = threads > 0 ? threads : 1;
751             if (cpus == 0) {
752                 sockets = sockets > 0 ? sockets : 1;
753                 cpus = cores * threads * sockets;
754             } else {
755                 ms->smp.max_cpus =
756                         qemu_opt_get_number(opts, "maxcpus", cpus);
757                 sockets = ms->smp.max_cpus / (cores * threads);
758             }
759         } else if (cores == 0) {
760             threads = threads > 0 ? threads : 1;
761             cores = cpus / (sockets * threads);
762             cores = cores > 0 ? cores : 1;
763         } else if (threads == 0) {
764             threads = cpus / (cores * sockets);
765             threads = threads > 0 ? threads : 1;
766         } else if (sockets * cores * threads < cpus) {
767             error_report("cpu topology: "
768                          "sockets (%u) * cores (%u) * threads (%u) < "
769                          "smp_cpus (%u)",
770                          sockets, cores, threads, cpus);
771             exit(1);
772         }
773 
774         ms->smp.max_cpus =
775                 qemu_opt_get_number(opts, "maxcpus", cpus);
776 
777         if (ms->smp.max_cpus < cpus) {
778             error_report("maxcpus must be equal to or greater than smp");
779             exit(1);
780         }
781 
782         if (sockets * cores * threads != ms->smp.max_cpus) {
783             error_report("Invalid CPU topology: "
784                          "sockets (%u) * cores (%u) * threads (%u) "
785                          "!= maxcpus (%u)",
786                          sockets, cores, threads,
787                          ms->smp.max_cpus);
788             exit(1);
789         }
790 
791         ms->smp.cpus = cpus;
792         ms->smp.cores = cores;
793         ms->smp.threads = threads;
794         ms->smp.sockets = sockets;
795     }
796 
797     if (ms->smp.cpus > 1) {
798         Error *blocker = NULL;
799         error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
800         replay_add_blocker(blocker);
801     }
802 }
803 
804 static void machine_class_init(ObjectClass *oc, void *data)
805 {
806     MachineClass *mc = MACHINE_CLASS(oc);
807 
808     /* Default 128 MB as guest ram size */
809     mc->default_ram_size = 128 * MiB;
810     mc->rom_file_has_mr = true;
811     mc->smp_parse = smp_parse;
812 
813     /* numa node memory size aligned on 8MB by default.
814      * On Linux, each node's border has to be 8MB aligned
815      */
816     mc->numa_mem_align_shift = 23;
817 
818     object_class_property_add_str(oc, "kernel",
819         machine_get_kernel, machine_set_kernel);
820     object_class_property_set_description(oc, "kernel",
821         "Linux kernel image file");
822 
823     object_class_property_add_str(oc, "initrd",
824         machine_get_initrd, machine_set_initrd);
825     object_class_property_set_description(oc, "initrd",
826         "Linux initial ramdisk file");
827 
828     object_class_property_add_str(oc, "append",
829         machine_get_append, machine_set_append);
830     object_class_property_set_description(oc, "append",
831         "Linux kernel command line");
832 
833     object_class_property_add_str(oc, "dtb",
834         machine_get_dtb, machine_set_dtb);
835     object_class_property_set_description(oc, "dtb",
836         "Linux kernel device tree file");
837 
838     object_class_property_add_str(oc, "dumpdtb",
839         machine_get_dumpdtb, machine_set_dumpdtb);
840     object_class_property_set_description(oc, "dumpdtb",
841         "Dump current dtb to a file and quit");
842 
843     object_class_property_add(oc, "phandle-start", "int",
844         machine_get_phandle_start, machine_set_phandle_start,
845         NULL, NULL);
846     object_class_property_set_description(oc, "phandle-start",
847         "The first phandle ID we may generate dynamically");
848 
849     object_class_property_add_str(oc, "dt-compatible",
850         machine_get_dt_compatible, machine_set_dt_compatible);
851     object_class_property_set_description(oc, "dt-compatible",
852         "Overrides the \"compatible\" property of the dt root node");
853 
854     object_class_property_add_bool(oc, "dump-guest-core",
855         machine_get_dump_guest_core, machine_set_dump_guest_core);
856     object_class_property_set_description(oc, "dump-guest-core",
857         "Include guest memory in a core dump");
858 
859     object_class_property_add_bool(oc, "mem-merge",
860         machine_get_mem_merge, machine_set_mem_merge);
861     object_class_property_set_description(oc, "mem-merge",
862         "Enable/disable memory merge support");
863 
864     object_class_property_add_bool(oc, "usb",
865         machine_get_usb, machine_set_usb);
866     object_class_property_set_description(oc, "usb",
867         "Set on/off to enable/disable usb");
868 
869     object_class_property_add_bool(oc, "graphics",
870         machine_get_graphics, machine_set_graphics);
871     object_class_property_set_description(oc, "graphics",
872         "Set on/off to enable/disable graphics emulation");
873 
874     object_class_property_add_str(oc, "firmware",
875         machine_get_firmware, machine_set_firmware);
876     object_class_property_set_description(oc, "firmware",
877         "Firmware image");
878 
879     object_class_property_add_bool(oc, "suppress-vmdesc",
880         machine_get_suppress_vmdesc, machine_set_suppress_vmdesc);
881     object_class_property_set_description(oc, "suppress-vmdesc",
882         "Set on to disable self-describing migration");
883 
884     object_class_property_add_link(oc, "confidential-guest-support",
885                                    TYPE_CONFIDENTIAL_GUEST_SUPPORT,
886                                    offsetof(MachineState, cgs),
887                                    machine_check_confidential_guest_support,
888                                    OBJ_PROP_LINK_STRONG);
889     object_class_property_set_description(oc, "confidential-guest-support",
890                                           "Set confidential guest scheme to support");
891 
892     /* For compatibility */
893     object_class_property_add_str(oc, "memory-encryption",
894         machine_get_memory_encryption, machine_set_memory_encryption);
895     object_class_property_set_description(oc, "memory-encryption",
896         "Set memory encryption object to use");
897 
898     object_class_property_add_str(oc, "memory-backend",
899                                   machine_get_memdev, machine_set_memdev);
900     object_class_property_set_description(oc, "memory-backend",
901                                           "Set RAM backend"
902                                           "Valid value is ID of hostmem based backend");
903 }
904 
905 static void machine_class_base_init(ObjectClass *oc, void *data)
906 {
907     MachineClass *mc = MACHINE_CLASS(oc);
908     mc->max_cpus = mc->max_cpus ?: 1;
909     mc->min_cpus = mc->min_cpus ?: 1;
910     mc->default_cpus = mc->default_cpus ?: 1;
911 
912     if (!object_class_is_abstract(oc)) {
913         const char *cname = object_class_get_name(oc);
914         assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
915         mc->name = g_strndup(cname,
916                             strlen(cname) - strlen(TYPE_MACHINE_SUFFIX));
917         mc->compat_props = g_ptr_array_new();
918     }
919 }
920 
921 static void machine_initfn(Object *obj)
922 {
923     MachineState *ms = MACHINE(obj);
924     MachineClass *mc = MACHINE_GET_CLASS(obj);
925 
926     container_get(obj, "/peripheral");
927     container_get(obj, "/peripheral-anon");
928 
929     ms->dump_guest_core = true;
930     ms->mem_merge = true;
931     ms->enable_graphics = true;
932     ms->kernel_cmdline = g_strdup("");
933 
934     if (mc->nvdimm_supported) {
935         Object *obj = OBJECT(ms);
936 
937         ms->nvdimms_state = g_new0(NVDIMMState, 1);
938         object_property_add_bool(obj, "nvdimm",
939                                  machine_get_nvdimm, machine_set_nvdimm);
940         object_property_set_description(obj, "nvdimm",
941                                         "Set on/off to enable/disable "
942                                         "NVDIMM instantiation");
943 
944         object_property_add_str(obj, "nvdimm-persistence",
945                                 machine_get_nvdimm_persistence,
946                                 machine_set_nvdimm_persistence);
947         object_property_set_description(obj, "nvdimm-persistence",
948                                         "Set NVDIMM persistence"
949                                         "Valid values are cpu, mem-ctrl");
950     }
951 
952     if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
953         ms->numa_state = g_new0(NumaState, 1);
954         object_property_add_bool(obj, "hmat",
955                                  machine_get_hmat, machine_set_hmat);
956         object_property_set_description(obj, "hmat",
957                                         "Set on/off to enable/disable "
958                                         "ACPI Heterogeneous Memory Attribute "
959                                         "Table (HMAT)");
960     }
961 
962     /* Register notifier when init is done for sysbus sanity checks */
963     ms->sysbus_notifier.notify = machine_init_notify;
964     qemu_add_machine_init_done_notifier(&ms->sysbus_notifier);
965 
966     /* default to mc->default_cpus */
967     ms->smp.cpus = mc->default_cpus;
968     ms->smp.max_cpus = mc->default_cpus;
969     ms->smp.cores = 1;
970     ms->smp.threads = 1;
971     ms->smp.sockets = 1;
972 }
973 
974 static void machine_finalize(Object *obj)
975 {
976     MachineState *ms = MACHINE(obj);
977 
978     g_free(ms->kernel_filename);
979     g_free(ms->initrd_filename);
980     g_free(ms->kernel_cmdline);
981     g_free(ms->dtb);
982     g_free(ms->dumpdtb);
983     g_free(ms->dt_compatible);
984     g_free(ms->firmware);
985     g_free(ms->device_memory);
986     g_free(ms->nvdimms_state);
987     g_free(ms->numa_state);
988 }
989 
990 bool machine_usb(MachineState *machine)
991 {
992     return machine->usb;
993 }
994 
995 int machine_phandle_start(MachineState *machine)
996 {
997     return machine->phandle_start;
998 }
999 
1000 bool machine_dump_guest_core(MachineState *machine)
1001 {
1002     return machine->dump_guest_core;
1003 }
1004 
1005 bool machine_mem_merge(MachineState *machine)
1006 {
1007     return machine->mem_merge;
1008 }
1009 
1010 static char *cpu_slot_to_string(const CPUArchId *cpu)
1011 {
1012     GString *s = g_string_new(NULL);
1013     if (cpu->props.has_socket_id) {
1014         g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
1015     }
1016     if (cpu->props.has_die_id) {
1017         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
1018     }
1019     if (cpu->props.has_core_id) {
1020         if (s->len) {
1021             g_string_append_printf(s, ", ");
1022         }
1023         g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id);
1024     }
1025     if (cpu->props.has_thread_id) {
1026         if (s->len) {
1027             g_string_append_printf(s, ", ");
1028         }
1029         g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id);
1030     }
1031     return g_string_free(s, false);
1032 }
1033 
1034 static void numa_validate_initiator(NumaState *numa_state)
1035 {
1036     int i;
1037     NodeInfo *numa_info = numa_state->nodes;
1038 
1039     for (i = 0; i < numa_state->num_nodes; i++) {
1040         if (numa_info[i].initiator == MAX_NODES) {
1041             error_report("The initiator of NUMA node %d is missing, use "
1042                          "'-numa node,initiator' option to declare it", i);
1043             exit(1);
1044         }
1045 
1046         if (!numa_info[numa_info[i].initiator].present) {
1047             error_report("NUMA node %" PRIu16 " is missing, use "
1048                          "'-numa node' option to declare it first",
1049                          numa_info[i].initiator);
1050             exit(1);
1051         }
1052 
1053         if (!numa_info[numa_info[i].initiator].has_cpu) {
1054             error_report("The initiator of NUMA node %d is invalid", i);
1055             exit(1);
1056         }
1057     }
1058 }
1059 
1060 static void machine_numa_finish_cpu_init(MachineState *machine)
1061 {
1062     int i;
1063     bool default_mapping;
1064     GString *s = g_string_new(NULL);
1065     MachineClass *mc = MACHINE_GET_CLASS(machine);
1066     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
1067 
1068     assert(machine->numa_state->num_nodes);
1069     for (i = 0; i < possible_cpus->len; i++) {
1070         if (possible_cpus->cpus[i].props.has_node_id) {
1071             break;
1072         }
1073     }
1074     default_mapping = (i == possible_cpus->len);
1075 
1076     for (i = 0; i < possible_cpus->len; i++) {
1077         const CPUArchId *cpu_slot = &possible_cpus->cpus[i];
1078 
1079         if (!cpu_slot->props.has_node_id) {
1080             /* fetch default mapping from board and enable it */
1081             CpuInstanceProperties props = cpu_slot->props;
1082 
1083             props.node_id = mc->get_default_cpu_node_id(machine, i);
1084             if (!default_mapping) {
1085                 /* record slots with not set mapping,
1086                  * TODO: make it hard error in future */
1087                 char *cpu_str = cpu_slot_to_string(cpu_slot);
1088                 g_string_append_printf(s, "%sCPU %d [%s]",
1089                                        s->len ? ", " : "", i, cpu_str);
1090                 g_free(cpu_str);
1091 
1092                 /* non mapped cpus used to fallback to node 0 */
1093                 props.node_id = 0;
1094             }
1095 
1096             props.has_node_id = true;
1097             machine_set_cpu_numa_node(machine, &props, &error_fatal);
1098         }
1099     }
1100 
1101     if (machine->numa_state->hmat_enabled) {
1102         numa_validate_initiator(machine->numa_state);
1103     }
1104 
1105     if (s->len && !qtest_enabled()) {
1106         warn_report("CPU(s) not present in any NUMA nodes: %s",
1107                     s->str);
1108         warn_report("All CPU(s) up to maxcpus should be described "
1109                     "in NUMA config, ability to start up with partial NUMA "
1110                     "mappings is obsoleted and will be removed in future");
1111     }
1112     g_string_free(s, true);
1113 }
1114 
1115 MemoryRegion *machine_consume_memdev(MachineState *machine,
1116                                      HostMemoryBackend *backend)
1117 {
1118     MemoryRegion *ret = host_memory_backend_get_memory(backend);
1119 
1120     if (memory_region_is_mapped(ret)) {
1121         error_report("memory backend %s can't be used multiple times.",
1122                      object_get_canonical_path_component(OBJECT(backend)));
1123         exit(EXIT_FAILURE);
1124     }
1125     host_memory_backend_set_mapped(backend, true);
1126     vmstate_register_ram_global(ret);
1127     return ret;
1128 }
1129 
1130 bool machine_smp_parse(MachineState *ms, QemuOpts *opts, Error **errp)
1131 {
1132     MachineClass *mc = MACHINE_GET_CLASS(ms);
1133 
1134     mc->smp_parse(ms, opts);
1135 
1136     /* sanity-check smp_cpus and max_cpus against mc */
1137     if (ms->smp.cpus < mc->min_cpus) {
1138         error_setg(errp, "Invalid SMP CPUs %d. The min CPUs "
1139                    "supported by machine '%s' is %d",
1140                    ms->smp.cpus,
1141                    mc->name, mc->min_cpus);
1142         return false;
1143     } else if (ms->smp.max_cpus > mc->max_cpus) {
1144         error_setg(errp, "Invalid SMP CPUs %d. The max CPUs "
1145                    "supported by machine '%s' is %d",
1146                    current_machine->smp.max_cpus,
1147                    mc->name, mc->max_cpus);
1148         return false;
1149     }
1150     return true;
1151 }
1152 
1153 void machine_run_board_init(MachineState *machine)
1154 {
1155     MachineClass *machine_class = MACHINE_GET_CLASS(machine);
1156     ObjectClass *oc = object_class_by_name(machine->cpu_type);
1157     CPUClass *cc;
1158 
1159     /* This checkpoint is required by replay to separate prior clock
1160        reading from the other reads, because timer polling functions query
1161        clock values from the log. */
1162     replay_checkpoint(CHECKPOINT_INIT);
1163 
1164     if (machine->ram_memdev_id) {
1165         Object *o;
1166         o = object_resolve_path_type(machine->ram_memdev_id,
1167                                      TYPE_MEMORY_BACKEND, NULL);
1168         machine->ram = machine_consume_memdev(machine, MEMORY_BACKEND(o));
1169     }
1170 
1171     if (machine->numa_state) {
1172         numa_complete_configuration(machine);
1173         if (machine->numa_state->num_nodes) {
1174             machine_numa_finish_cpu_init(machine);
1175         }
1176     }
1177 
1178     /* If the machine supports the valid_cpu_types check and the user
1179      * specified a CPU with -cpu check here that the user CPU is supported.
1180      */
1181     if (machine_class->valid_cpu_types && machine->cpu_type) {
1182         int i;
1183 
1184         for (i = 0; machine_class->valid_cpu_types[i]; i++) {
1185             if (object_class_dynamic_cast(oc,
1186                                           machine_class->valid_cpu_types[i])) {
1187                 /* The user specificed CPU is in the valid field, we are
1188                  * good to go.
1189                  */
1190                 break;
1191             }
1192         }
1193 
1194         if (!machine_class->valid_cpu_types[i]) {
1195             /* The user specified CPU is not valid */
1196             error_report("Invalid CPU type: %s", machine->cpu_type);
1197             error_printf("The valid types are: %s",
1198                          machine_class->valid_cpu_types[0]);
1199             for (i = 1; machine_class->valid_cpu_types[i]; i++) {
1200                 error_printf(", %s", machine_class->valid_cpu_types[i]);
1201             }
1202             error_printf("\n");
1203 
1204             exit(1);
1205         }
1206     }
1207 
1208     /* Check if CPU type is deprecated and warn if so */
1209     cc = CPU_CLASS(oc);
1210     if (cc && cc->deprecation_note) {
1211         warn_report("CPU model %s is deprecated -- %s", machine->cpu_type,
1212                     cc->deprecation_note);
1213     }
1214 
1215     if (machine->cgs) {
1216         /*
1217          * With confidential guests, the host can't see the real
1218          * contents of RAM, so there's no point in it trying to merge
1219          * areas.
1220          */
1221         machine_set_mem_merge(OBJECT(machine), false, &error_abort);
1222 
1223         /*
1224          * Virtio devices can't count on directly accessing guest
1225          * memory, so they need iommu_platform=on to use normal DMA
1226          * mechanisms.  That requires also disabling legacy virtio
1227          * support for those virtio pci devices which allow it.
1228          */
1229         object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy",
1230                                    "on", true);
1231         object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform",
1232                                    "on", false);
1233     }
1234 
1235     machine_class->init(machine);
1236     phase_advance(PHASE_MACHINE_INITIALIZED);
1237 }
1238 
1239 static NotifierList machine_init_done_notifiers =
1240     NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
1241 
1242 void qemu_add_machine_init_done_notifier(Notifier *notify)
1243 {
1244     notifier_list_add(&machine_init_done_notifiers, notify);
1245     if (phase_check(PHASE_MACHINE_READY)) {
1246         notify->notify(notify, NULL);
1247     }
1248 }
1249 
1250 void qemu_remove_machine_init_done_notifier(Notifier *notify)
1251 {
1252     notifier_remove(notify);
1253 }
1254 
1255 void qdev_machine_creation_done(void)
1256 {
1257     cpu_synchronize_all_post_init();
1258 
1259     if (current_machine->boot_once) {
1260         qemu_boot_set(current_machine->boot_once, &error_fatal);
1261         qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_order));
1262     }
1263 
1264     /*
1265      * ok, initial machine setup is done, starting from now we can
1266      * only create hotpluggable devices
1267      */
1268     phase_advance(PHASE_MACHINE_READY);
1269     qdev_assert_realized_properly();
1270 
1271     /* TODO: once all bus devices are qdevified, this should be done
1272      * when bus is created by qdev.c */
1273     /*
1274      * TODO: If we had a main 'reset container' that the whole system
1275      * lived in, we could reset that using the multi-phase reset
1276      * APIs. For the moment, we just reset the sysbus, which will cause
1277      * all devices hanging off it (and all their child buses, recursively)
1278      * to be reset. Note that this will *not* reset any Device objects
1279      * which are not attached to some part of the qbus tree!
1280      */
1281     qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default());
1282 
1283     notifier_list_notify(&machine_init_done_notifiers, NULL);
1284 
1285     if (rom_check_and_register_reset() != 0) {
1286         exit(1);
1287     }
1288 
1289     replay_start();
1290 
1291     /* This checkpoint is required by replay to separate prior clock
1292        reading from the other reads, because timer polling functions query
1293        clock values from the log. */
1294     replay_checkpoint(CHECKPOINT_RESET);
1295     qemu_system_reset(SHUTDOWN_CAUSE_NONE);
1296     register_global_state();
1297 }
1298 
1299 static const TypeInfo machine_info = {
1300     .name = TYPE_MACHINE,
1301     .parent = TYPE_OBJECT,
1302     .abstract = true,
1303     .class_size = sizeof(MachineClass),
1304     .class_init    = machine_class_init,
1305     .class_base_init = machine_class_base_init,
1306     .instance_size = sizeof(MachineState),
1307     .instance_init = machine_initfn,
1308     .instance_finalize = machine_finalize,
1309 };
1310 
1311 static void machine_register_types(void)
1312 {
1313     type_register_static(&machine_info);
1314 }
1315 
1316 type_init(machine_register_types)
1317