1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qemu/accel.h" 16 #include "sysemu/replay.h" 17 #include "hw/boards.h" 18 #include "hw/loader.h" 19 #include "qemu/error-report.h" 20 #include "qapi/error.h" 21 #include "qapi/qapi-visit-machine.h" 22 #include "qemu/madvise.h" 23 #include "qom/object_interfaces.h" 24 #include "sysemu/cpus.h" 25 #include "sysemu/sysemu.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/xen.h" 29 #include "sysemu/qtest.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/mem/nvdimm.h" 32 #include "migration/global_state.h" 33 #include "exec/confidential-guest-support.h" 34 #include "hw/virtio/virtio-pci.h" 35 #include "hw/virtio/virtio-net.h" 36 #include "hw/virtio/virtio-iommu.h" 37 #include "audio/audio.h" 38 39 GlobalProperty hw_compat_9_2[] = {}; 40 const size_t hw_compat_9_2_len = G_N_ELEMENTS(hw_compat_9_2); 41 42 GlobalProperty hw_compat_9_1[] = { 43 { TYPE_PCI_DEVICE, "x-pcie-ext-tag", "false" }, 44 }; 45 const size_t hw_compat_9_1_len = G_N_ELEMENTS(hw_compat_9_1); 46 47 GlobalProperty hw_compat_9_0[] = { 48 {"arm-cpu", "backcompat-cntfrq", "true" }, 49 { "scsi-hd", "migrate-emulated-scsi-request", "false" }, 50 { "scsi-cd", "migrate-emulated-scsi-request", "false" }, 51 {"vfio-pci", "skip-vsc-check", "false" }, 52 { "virtio-pci", "x-pcie-pm-no-soft-reset", "off" }, 53 {"sd-card", "spec_version", "2" }, 54 }; 55 const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0); 56 57 GlobalProperty hw_compat_8_2[] = { 58 { "migration", "zero-page-detection", "legacy"}, 59 { TYPE_VIRTIO_IOMMU_PCI, "granule", "4k" }, 60 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "64" }, 61 { "virtio-gpu-device", "x-scanout-vmstate-version", "1" }, 62 }; 63 const size_t hw_compat_8_2_len = G_N_ELEMENTS(hw_compat_8_2); 64 65 GlobalProperty hw_compat_8_1[] = { 66 { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" }, 67 { "ramfb", "x-migrate", "off" }, 68 { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" }, 69 { "igb", "x-pcie-flr-init", "off" }, 70 { TYPE_VIRTIO_NET, "host_uso", "off"}, 71 { TYPE_VIRTIO_NET, "guest_uso4", "off"}, 72 { TYPE_VIRTIO_NET, "guest_uso6", "off"}, 73 }; 74 const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1); 75 76 GlobalProperty hw_compat_8_0[] = { 77 { "migration", "multifd-flush-after-each-section", "on"}, 78 { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, 79 }; 80 const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); 81 82 GlobalProperty hw_compat_7_2[] = { 83 { "e1000e", "migrate-timadj", "off" }, 84 { "virtio-mem", "x-early-migration", "false" }, 85 { "migration", "x-preempt-pre-7-2", "true" }, 86 { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" }, 87 }; 88 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); 89 90 GlobalProperty hw_compat_7_1[] = { 91 { "virtio-device", "queue_reset", "false" }, 92 { "virtio-rng-pci", "vectors", "0" }, 93 { "virtio-rng-pci-transitional", "vectors", "0" }, 94 { "virtio-rng-pci-non-transitional", "vectors", "0" }, 95 }; 96 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); 97 98 GlobalProperty hw_compat_7_0[] = { 99 { "arm-gicv3-common", "force-8-bit-prio", "on" }, 100 { "nvme-ns", "eui64-default", "on"}, 101 }; 102 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); 103 104 GlobalProperty hw_compat_6_2[] = { 105 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, 106 }; 107 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); 108 109 GlobalProperty hw_compat_6_1[] = { 110 { "vhost-user-vsock-device", "seqpacket", "off" }, 111 { "nvme-ns", "shared", "off" }, 112 }; 113 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); 114 115 GlobalProperty hw_compat_6_0[] = { 116 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 117 { "i8042", "extended-state", "false"}, 118 { "nvme-ns", "eui64-default", "off"}, 119 { "e1000", "init-vet", "off" }, 120 { "e1000e", "init-vet", "off" }, 121 { "vhost-vsock-device", "seqpacket", "off" }, 122 }; 123 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 124 125 GlobalProperty hw_compat_5_2[] = { 126 { "ICH9-LPC", "smm-compat", "on"}, 127 { "PIIX4_PM", "smm-compat", "on"}, 128 { "virtio-blk-device", "report-discard-granularity", "off" }, 129 { "virtio-net-pci-base", "vectors", "3"}, 130 { "nvme", "msix-exclusive-bar", "on"}, 131 }; 132 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 133 134 GlobalProperty hw_compat_5_1[] = { 135 { "vhost-scsi", "num_queues", "1"}, 136 { "vhost-user-blk", "num-queues", "1"}, 137 { "vhost-user-scsi", "num_queues", "1"}, 138 { "virtio-blk-device", "num-queues", "1"}, 139 { "virtio-scsi-device", "num_queues", "1"}, 140 { "nvme", "use-intel-id", "on"}, 141 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 142 { "pl011", "migrate-clk", "off" }, 143 { "virtio-pci", "x-ats-page-aligned", "off"}, 144 }; 145 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 146 147 GlobalProperty hw_compat_5_0[] = { 148 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 149 { "virtio-balloon-device", "page-poison", "false" }, 150 { "vmport", "x-read-set-eax", "off" }, 151 { "vmport", "x-signal-unsupported-cmd", "off" }, 152 { "vmport", "x-report-vmx-type", "off" }, 153 { "vmport", "x-cmds-v2", "off" }, 154 { "virtio-device", "x-disable-legacy-check", "true" }, 155 }; 156 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 157 158 GlobalProperty hw_compat_4_2[] = { 159 { "virtio-blk-device", "queue-size", "128"}, 160 { "virtio-scsi-device", "virtqueue_size", "128"}, 161 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 162 { "virtio-blk-device", "seg-max-adjust", "off"}, 163 { "virtio-scsi-device", "seg_max_adjust", "off"}, 164 { "vhost-blk-device", "seg_max_adjust", "off"}, 165 { "usb-host", "suppress-remote-wake", "off" }, 166 { "usb-redir", "suppress-remote-wake", "off" }, 167 { "qxl", "revision", "4" }, 168 { "qxl-vga", "revision", "4" }, 169 { "fw_cfg", "acpi-mr-restore", "false" }, 170 { "virtio-device", "use-disabled-flag", "false" }, 171 }; 172 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 173 174 GlobalProperty hw_compat_4_1[] = { 175 { "virtio-pci", "x-pcie-flr-init", "off" }, 176 }; 177 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 178 179 GlobalProperty hw_compat_4_0[] = { 180 { "VGA", "edid", "false" }, 181 { "secondary-vga", "edid", "false" }, 182 { "bochs-display", "edid", "false" }, 183 { "virtio-vga", "edid", "false" }, 184 { "virtio-gpu-device", "edid", "false" }, 185 { "virtio-device", "use-started", "false" }, 186 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 187 { "pl031", "migrate-tick-offset", "false" }, 188 }; 189 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 190 191 GlobalProperty hw_compat_3_1[] = { 192 { "pcie-root-port", "x-speed", "2_5" }, 193 { "pcie-root-port", "x-width", "1" }, 194 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 195 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 196 { "tpm-crb", "ppi", "false" }, 197 { "tpm-tis", "ppi", "false" }, 198 { "usb-kbd", "serial", "42" }, 199 { "usb-mouse", "serial", "42" }, 200 { "usb-tablet", "serial", "42" }, 201 { "virtio-blk-device", "discard", "false" }, 202 { "virtio-blk-device", "write-zeroes", "false" }, 203 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 204 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 205 }; 206 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 207 208 GlobalProperty hw_compat_3_0[] = {}; 209 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 210 211 GlobalProperty hw_compat_2_12[] = { 212 { "hda-audio", "use-timer", "false" }, 213 { "cirrus-vga", "global-vmstate", "true" }, 214 { "VGA", "global-vmstate", "true" }, 215 { "vmware-svga", "global-vmstate", "true" }, 216 { "qxl-vga", "global-vmstate", "true" }, 217 }; 218 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 219 220 GlobalProperty hw_compat_2_11[] = { 221 { "hpet", "hpet-offset-saved", "false" }, 222 { "virtio-blk-pci", "vectors", "2" }, 223 { "vhost-user-blk-pci", "vectors", "2" }, 224 { "e1000", "migrate_tso_props", "off" }, 225 }; 226 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 227 228 GlobalProperty hw_compat_2_10[] = { 229 { "virtio-mouse-device", "wheel-axis", "false" }, 230 { "virtio-tablet-device", "wheel-axis", "false" }, 231 }; 232 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 233 234 GlobalProperty hw_compat_2_9[] = { 235 { "pci-bridge", "shpc", "off" }, 236 { "intel-iommu", "pt", "off" }, 237 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 238 { "pcie-root-port", "x-migrate-msix", "false" }, 239 }; 240 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 241 242 GlobalProperty hw_compat_2_8[] = { 243 { "fw_cfg_mem", "x-file-slots", "0x10" }, 244 { "fw_cfg_io", "x-file-slots", "0x10" }, 245 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 246 { "pci-bridge", "shpc", "on" }, 247 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 248 { "virtio-pci", "x-pcie-deverr-init", "off" }, 249 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 250 { "virtio-pci", "x-pcie-pm-init", "off" }, 251 { "cirrus-vga", "vgamem_mb", "8" }, 252 { "isa-cirrus-vga", "vgamem_mb", "8" }, 253 }; 254 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 255 256 GlobalProperty hw_compat_2_7[] = { 257 { "virtio-pci", "page-per-vq", "on" }, 258 { "virtio-serial-device", "emergency-write", "off" }, 259 { "ioapic", "version", "0x11" }, 260 { "intel-iommu", "x-buggy-eim", "true" }, 261 { "virtio-pci", "x-ignore-backend-features", "on" }, 262 }; 263 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 264 265 GlobalProperty hw_compat_2_6[] = { 266 { "virtio-mmio", "format_transport_address", "off" }, 267 /* Optional because not all virtio-pci devices support legacy mode */ 268 { "virtio-pci", "disable-modern", "on", .optional = true }, 269 { "virtio-pci", "disable-legacy", "off", .optional = true }, 270 }; 271 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 272 273 GlobalProperty hw_compat_2_5[] = { 274 { "isa-fdc", "fallback", "144" }, 275 { "pvscsi", "x-old-pci-configuration", "on" }, 276 { "pvscsi", "x-disable-pcie", "on" }, 277 { "vmxnet3", "x-old-msi-offsets", "on" }, 278 { "vmxnet3", "x-disable-pcie", "on" }, 279 }; 280 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 281 282 GlobalProperty hw_compat_2_4[] = { 283 { "e1000", "extra_mac_registers", "off" }, 284 { "virtio-pci", "x-disable-pcie", "on" }, 285 { "virtio-pci", "migrate-extra", "off" }, 286 { "fw_cfg_mem", "dma_enabled", "off" }, 287 { "fw_cfg_io", "dma_enabled", "off" } 288 }; 289 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 290 291 MachineState *current_machine; 292 293 static char *machine_get_kernel(Object *obj, Error **errp) 294 { 295 MachineState *ms = MACHINE(obj); 296 297 return g_strdup(ms->kernel_filename); 298 } 299 300 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 301 { 302 MachineState *ms = MACHINE(obj); 303 304 g_free(ms->kernel_filename); 305 ms->kernel_filename = g_strdup(value); 306 } 307 308 static char *machine_get_initrd(Object *obj, Error **errp) 309 { 310 MachineState *ms = MACHINE(obj); 311 312 return g_strdup(ms->initrd_filename); 313 } 314 315 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 316 { 317 MachineState *ms = MACHINE(obj); 318 319 g_free(ms->initrd_filename); 320 ms->initrd_filename = g_strdup(value); 321 } 322 323 static char *machine_get_append(Object *obj, Error **errp) 324 { 325 MachineState *ms = MACHINE(obj); 326 327 return g_strdup(ms->kernel_cmdline); 328 } 329 330 static void machine_set_append(Object *obj, const char *value, Error **errp) 331 { 332 MachineState *ms = MACHINE(obj); 333 334 g_free(ms->kernel_cmdline); 335 ms->kernel_cmdline = g_strdup(value); 336 } 337 338 static char *machine_get_dtb(Object *obj, Error **errp) 339 { 340 MachineState *ms = MACHINE(obj); 341 342 return g_strdup(ms->dtb); 343 } 344 345 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 346 { 347 MachineState *ms = MACHINE(obj); 348 349 g_free(ms->dtb); 350 ms->dtb = g_strdup(value); 351 } 352 353 static char *machine_get_dumpdtb(Object *obj, Error **errp) 354 { 355 MachineState *ms = MACHINE(obj); 356 357 return g_strdup(ms->dumpdtb); 358 } 359 360 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 361 { 362 MachineState *ms = MACHINE(obj); 363 364 g_free(ms->dumpdtb); 365 ms->dumpdtb = g_strdup(value); 366 } 367 368 static void machine_get_phandle_start(Object *obj, Visitor *v, 369 const char *name, void *opaque, 370 Error **errp) 371 { 372 MachineState *ms = MACHINE(obj); 373 int64_t value = ms->phandle_start; 374 375 visit_type_int(v, name, &value, errp); 376 } 377 378 static void machine_set_phandle_start(Object *obj, Visitor *v, 379 const char *name, void *opaque, 380 Error **errp) 381 { 382 MachineState *ms = MACHINE(obj); 383 int64_t value; 384 385 if (!visit_type_int(v, name, &value, errp)) { 386 return; 387 } 388 389 ms->phandle_start = value; 390 } 391 392 static char *machine_get_dt_compatible(Object *obj, Error **errp) 393 { 394 MachineState *ms = MACHINE(obj); 395 396 return g_strdup(ms->dt_compatible); 397 } 398 399 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 400 { 401 MachineState *ms = MACHINE(obj); 402 403 g_free(ms->dt_compatible); 404 ms->dt_compatible = g_strdup(value); 405 } 406 407 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 408 { 409 MachineState *ms = MACHINE(obj); 410 411 return ms->dump_guest_core; 412 } 413 414 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 415 { 416 MachineState *ms = MACHINE(obj); 417 418 if (!value && QEMU_MADV_DONTDUMP == QEMU_MADV_INVALID) { 419 error_setg(errp, "Dumping guest memory cannot be disabled on this host"); 420 return; 421 } 422 ms->dump_guest_core = value; 423 } 424 425 static bool machine_get_mem_merge(Object *obj, Error **errp) 426 { 427 MachineState *ms = MACHINE(obj); 428 429 return ms->mem_merge; 430 } 431 432 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 433 { 434 MachineState *ms = MACHINE(obj); 435 436 if (value && QEMU_MADV_MERGEABLE == QEMU_MADV_INVALID) { 437 error_setg(errp, "Memory merging is not supported on this host"); 438 return; 439 } 440 ms->mem_merge = value; 441 } 442 443 static bool machine_get_usb(Object *obj, Error **errp) 444 { 445 MachineState *ms = MACHINE(obj); 446 447 return ms->usb; 448 } 449 450 static void machine_set_usb(Object *obj, bool value, Error **errp) 451 { 452 MachineState *ms = MACHINE(obj); 453 454 ms->usb = value; 455 ms->usb_disabled = !value; 456 } 457 458 static bool machine_get_graphics(Object *obj, Error **errp) 459 { 460 MachineState *ms = MACHINE(obj); 461 462 return ms->enable_graphics; 463 } 464 465 static void machine_set_graphics(Object *obj, bool value, Error **errp) 466 { 467 MachineState *ms = MACHINE(obj); 468 469 ms->enable_graphics = value; 470 } 471 472 static char *machine_get_firmware(Object *obj, Error **errp) 473 { 474 MachineState *ms = MACHINE(obj); 475 476 return g_strdup(ms->firmware); 477 } 478 479 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 480 { 481 MachineState *ms = MACHINE(obj); 482 483 g_free(ms->firmware); 484 ms->firmware = g_strdup(value); 485 } 486 487 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 488 { 489 MachineState *ms = MACHINE(obj); 490 491 ms->suppress_vmdesc = value; 492 } 493 494 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 495 { 496 MachineState *ms = MACHINE(obj); 497 498 return ms->suppress_vmdesc; 499 } 500 501 static char *machine_get_memory_encryption(Object *obj, Error **errp) 502 { 503 MachineState *ms = MACHINE(obj); 504 505 if (ms->cgs) { 506 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 507 } 508 509 return NULL; 510 } 511 512 static void machine_set_memory_encryption(Object *obj, const char *value, 513 Error **errp) 514 { 515 Object *cgs = 516 object_resolve_path_component(object_get_objects_root(), value); 517 518 if (!cgs) { 519 error_setg(errp, "No such memory encryption object '%s'", value); 520 return; 521 } 522 523 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 524 } 525 526 static void machine_check_confidential_guest_support(const Object *obj, 527 const char *name, 528 Object *new_target, 529 Error **errp) 530 { 531 /* 532 * So far the only constraint is that the target has the 533 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 534 * by the QOM core 535 */ 536 } 537 538 static bool machine_get_nvdimm(Object *obj, Error **errp) 539 { 540 MachineState *ms = MACHINE(obj); 541 542 return ms->nvdimms_state->is_enabled; 543 } 544 545 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 546 { 547 MachineState *ms = MACHINE(obj); 548 549 ms->nvdimms_state->is_enabled = value; 550 } 551 552 static bool machine_get_hmat(Object *obj, Error **errp) 553 { 554 MachineState *ms = MACHINE(obj); 555 556 return ms->numa_state->hmat_enabled; 557 } 558 559 static void machine_set_hmat(Object *obj, bool value, Error **errp) 560 { 561 MachineState *ms = MACHINE(obj); 562 563 ms->numa_state->hmat_enabled = value; 564 } 565 566 static void machine_get_mem(Object *obj, Visitor *v, const char *name, 567 void *opaque, Error **errp) 568 { 569 MachineState *ms = MACHINE(obj); 570 MemorySizeConfiguration mem = { 571 .has_size = true, 572 .size = ms->ram_size, 573 .has_max_size = !!ms->ram_slots, 574 .max_size = ms->maxram_size, 575 .has_slots = !!ms->ram_slots, 576 .slots = ms->ram_slots, 577 }; 578 MemorySizeConfiguration *p_mem = &mem; 579 580 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); 581 } 582 583 static void machine_set_mem(Object *obj, Visitor *v, const char *name, 584 void *opaque, Error **errp) 585 { 586 ERRP_GUARD(); 587 MachineState *ms = MACHINE(obj); 588 MachineClass *mc = MACHINE_GET_CLASS(obj); 589 MemorySizeConfiguration *mem; 590 591 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { 592 return; 593 } 594 595 if (!mem->has_size) { 596 mem->has_size = true; 597 mem->size = mc->default_ram_size; 598 } 599 mem->size = QEMU_ALIGN_UP(mem->size, 8192); 600 if (mc->fixup_ram_size) { 601 mem->size = mc->fixup_ram_size(mem->size); 602 } 603 if ((ram_addr_t)mem->size != mem->size) { 604 error_setg(errp, "ram size %llu exceeds permitted maximum %llu", 605 (unsigned long long)mem->size, 606 (unsigned long long)RAM_ADDR_MAX); 607 goto out_free; 608 } 609 610 if (mem->has_max_size) { 611 if ((ram_addr_t)mem->max_size != mem->max_size) { 612 error_setg(errp, "ram size %llu exceeds permitted maximum %llu", 613 (unsigned long long)mem->max_size, 614 (unsigned long long)RAM_ADDR_MAX); 615 goto out_free; 616 } 617 if (mem->max_size < mem->size) { 618 error_setg(errp, "invalid value of maxmem: " 619 "maximum memory size (0x%" PRIx64 ") must be at least " 620 "the initial memory size (0x%" PRIx64 ")", 621 mem->max_size, mem->size); 622 goto out_free; 623 } 624 if (mem->has_slots && mem->slots && mem->max_size == mem->size) { 625 error_setg(errp, "invalid value of maxmem: " 626 "memory slots were specified but maximum memory size " 627 "(0x%" PRIx64 ") is equal to the initial memory size " 628 "(0x%" PRIx64 ")", mem->max_size, mem->size); 629 goto out_free; 630 } 631 ms->maxram_size = mem->max_size; 632 } else { 633 if (mem->has_slots) { 634 error_setg(errp, "slots specified but no max-size"); 635 goto out_free; 636 } 637 ms->maxram_size = mem->size; 638 } 639 ms->ram_size = mem->size; 640 ms->ram_slots = mem->has_slots ? mem->slots : 0; 641 out_free: 642 qapi_free_MemorySizeConfiguration(mem); 643 } 644 645 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 646 { 647 MachineState *ms = MACHINE(obj); 648 649 return g_strdup(ms->nvdimms_state->persistence_string); 650 } 651 652 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 653 Error **errp) 654 { 655 MachineState *ms = MACHINE(obj); 656 NVDIMMState *nvdimms_state = ms->nvdimms_state; 657 658 if (strcmp(value, "cpu") == 0) { 659 nvdimms_state->persistence = 3; 660 } else if (strcmp(value, "mem-ctrl") == 0) { 661 nvdimms_state->persistence = 2; 662 } else { 663 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 664 value); 665 return; 666 } 667 668 g_free(nvdimms_state->persistence_string); 669 nvdimms_state->persistence_string = g_strdup(value); 670 } 671 672 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 673 { 674 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 675 } 676 677 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 678 { 679 Object *obj = OBJECT(dev); 680 681 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 682 return false; 683 } 684 685 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); 686 } 687 688 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) 689 { 690 bool allowed = false; 691 strList *wl; 692 ObjectClass *klass = object_class_by_name(type); 693 694 for (wl = mc->allowed_dynamic_sysbus_devices; 695 !allowed && wl; 696 wl = wl->next) { 697 allowed |= !!object_class_dynamic_cast(klass, wl->value); 698 } 699 700 return allowed; 701 } 702 703 static char *machine_get_audiodev(Object *obj, Error **errp) 704 { 705 MachineState *ms = MACHINE(obj); 706 707 return g_strdup(ms->audiodev); 708 } 709 710 static void machine_set_audiodev(Object *obj, const char *value, 711 Error **errp) 712 { 713 MachineState *ms = MACHINE(obj); 714 715 if (!audio_state_by_name(value, errp)) { 716 return; 717 } 718 719 g_free(ms->audiodev); 720 ms->audiodev = g_strdup(value); 721 } 722 723 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 724 { 725 int i; 726 HotpluggableCPUList *head = NULL; 727 MachineClass *mc = MACHINE_GET_CLASS(machine); 728 729 /* force board to initialize possible_cpus if it hasn't been done yet */ 730 mc->possible_cpu_arch_ids(machine); 731 732 for (i = 0; i < machine->possible_cpus->len; i++) { 733 CPUState *cpu; 734 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 735 736 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 737 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 738 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 739 sizeof(*cpu_item->props)); 740 741 cpu = machine->possible_cpus->cpus[i].cpu; 742 if (cpu) { 743 cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); 744 } 745 QAPI_LIST_PREPEND(head, cpu_item); 746 } 747 return head; 748 } 749 750 /** 751 * machine_set_cpu_numa_node: 752 * @machine: machine object to modify 753 * @props: specifies which cpu objects to assign to 754 * numa node specified by @props.node_id 755 * @errp: if an error occurs, a pointer to an area to store the error 756 * 757 * Associate NUMA node specified by @props.node_id with cpu slots that 758 * match socket/core/thread-ids specified by @props. It's recommended to use 759 * query-hotpluggable-cpus.props values to specify affected cpu slots, 760 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 761 * 762 * However for CLI convenience it's possible to pass in subset of properties, 763 * which would affect all cpu slots that match it. 764 * Ex for pc machine: 765 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 766 * -numa cpu,node-id=0,socket_id=0 \ 767 * -numa cpu,node-id=1,socket_id=1 768 * will assign all child cores of socket 0 to node 0 and 769 * of socket 1 to node 1. 770 * 771 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 772 * return error. 773 * Empty subset is disallowed and function will return with error in this case. 774 */ 775 void machine_set_cpu_numa_node(MachineState *machine, 776 const CpuInstanceProperties *props, Error **errp) 777 { 778 MachineClass *mc = MACHINE_GET_CLASS(machine); 779 NodeInfo *numa_info = machine->numa_state->nodes; 780 bool match = false; 781 int i; 782 783 if (!mc->possible_cpu_arch_ids) { 784 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 785 return; 786 } 787 788 /* disabling node mapping is not supported, forbid it */ 789 assert(props->has_node_id); 790 791 /* force board to initialize possible_cpus if it hasn't been done yet */ 792 mc->possible_cpu_arch_ids(machine); 793 794 for (i = 0; i < machine->possible_cpus->len; i++) { 795 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 796 797 /* reject unsupported by board properties */ 798 if (props->has_thread_id && !slot->props.has_thread_id) { 799 error_setg(errp, "thread-id is not supported"); 800 return; 801 } 802 803 if (props->has_core_id && !slot->props.has_core_id) { 804 error_setg(errp, "core-id is not supported"); 805 return; 806 } 807 808 if (props->has_module_id && !slot->props.has_module_id) { 809 error_setg(errp, "module-id is not supported"); 810 return; 811 } 812 813 if (props->has_cluster_id && !slot->props.has_cluster_id) { 814 error_setg(errp, "cluster-id is not supported"); 815 return; 816 } 817 818 if (props->has_socket_id && !slot->props.has_socket_id) { 819 error_setg(errp, "socket-id is not supported"); 820 return; 821 } 822 823 if (props->has_die_id && !slot->props.has_die_id) { 824 error_setg(errp, "die-id is not supported"); 825 return; 826 } 827 828 /* skip slots with explicit mismatch */ 829 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 830 continue; 831 } 832 833 if (props->has_core_id && props->core_id != slot->props.core_id) { 834 continue; 835 } 836 837 if (props->has_module_id && 838 props->module_id != slot->props.module_id) { 839 continue; 840 } 841 842 if (props->has_cluster_id && 843 props->cluster_id != slot->props.cluster_id) { 844 continue; 845 } 846 847 if (props->has_die_id && props->die_id != slot->props.die_id) { 848 continue; 849 } 850 851 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 852 continue; 853 } 854 855 /* reject assignment if slot is already assigned, for compatibility 856 * of legacy cpu_index mapping with SPAPR core based mapping do not 857 * error out if cpu thread and matched core have the same node-id */ 858 if (slot->props.has_node_id && 859 slot->props.node_id != props->node_id) { 860 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 861 slot->props.node_id); 862 return; 863 } 864 865 /* assign slot to node as it's matched '-numa cpu' key */ 866 match = true; 867 slot->props.node_id = props->node_id; 868 slot->props.has_node_id = props->has_node_id; 869 870 if (machine->numa_state->hmat_enabled) { 871 if ((numa_info[props->node_id].initiator < MAX_NODES) && 872 (props->node_id != numa_info[props->node_id].initiator)) { 873 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 874 " should be itself (got %" PRIu16 ")", 875 props->node_id, numa_info[props->node_id].initiator); 876 return; 877 } 878 numa_info[props->node_id].has_cpu = true; 879 numa_info[props->node_id].initiator = props->node_id; 880 } 881 } 882 883 if (!match) { 884 error_setg(errp, "no match found"); 885 } 886 } 887 888 static void machine_get_smp(Object *obj, Visitor *v, const char *name, 889 void *opaque, Error **errp) 890 { 891 MachineState *ms = MACHINE(obj); 892 SMPConfiguration *config = &(SMPConfiguration){ 893 .has_cpus = true, .cpus = ms->smp.cpus, 894 .has_drawers = true, .drawers = ms->smp.drawers, 895 .has_books = true, .books = ms->smp.books, 896 .has_sockets = true, .sockets = ms->smp.sockets, 897 .has_dies = true, .dies = ms->smp.dies, 898 .has_clusters = true, .clusters = ms->smp.clusters, 899 .has_modules = true, .modules = ms->smp.modules, 900 .has_cores = true, .cores = ms->smp.cores, 901 .has_threads = true, .threads = ms->smp.threads, 902 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, 903 }; 904 905 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { 906 return; 907 } 908 } 909 910 static void machine_set_smp(Object *obj, Visitor *v, const char *name, 911 void *opaque, Error **errp) 912 { 913 MachineState *ms = MACHINE(obj); 914 g_autoptr(SMPConfiguration) config = NULL; 915 916 if (!visit_type_SMPConfiguration(v, name, &config, errp)) { 917 return; 918 } 919 920 machine_parse_smp_config(ms, config, errp); 921 } 922 923 static void machine_get_smp_cache(Object *obj, Visitor *v, const char *name, 924 void *opaque, Error **errp) 925 { 926 MachineState *ms = MACHINE(obj); 927 SmpCache *cache = &ms->smp_cache; 928 SmpCachePropertiesList *head = NULL; 929 SmpCachePropertiesList **tail = &head; 930 931 for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { 932 SmpCacheProperties *node = g_new(SmpCacheProperties, 1); 933 934 node->cache = cache->props[i].cache; 935 node->topology = cache->props[i].topology; 936 QAPI_LIST_APPEND(tail, node); 937 } 938 939 visit_type_SmpCachePropertiesList(v, name, &head, errp); 940 qapi_free_SmpCachePropertiesList(head); 941 } 942 943 static void machine_set_smp_cache(Object *obj, Visitor *v, const char *name, 944 void *opaque, Error **errp) 945 { 946 MachineState *ms = MACHINE(obj); 947 SmpCachePropertiesList *caches; 948 949 if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) { 950 return; 951 } 952 953 machine_parse_smp_cache(ms, caches, errp); 954 qapi_free_SmpCachePropertiesList(caches); 955 } 956 957 static void machine_get_boot(Object *obj, Visitor *v, const char *name, 958 void *opaque, Error **errp) 959 { 960 MachineState *ms = MACHINE(obj); 961 BootConfiguration *config = &ms->boot_config; 962 visit_type_BootConfiguration(v, name, &config, &error_abort); 963 } 964 965 static void machine_free_boot_config(MachineState *ms) 966 { 967 g_free(ms->boot_config.order); 968 g_free(ms->boot_config.once); 969 g_free(ms->boot_config.splash); 970 } 971 972 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) 973 { 974 MachineClass *machine_class = MACHINE_GET_CLASS(ms); 975 976 machine_free_boot_config(ms); 977 ms->boot_config = *config; 978 if (!config->order) { 979 ms->boot_config.order = g_strdup(machine_class->default_boot_order); 980 } 981 } 982 983 static void machine_set_boot(Object *obj, Visitor *v, const char *name, 984 void *opaque, Error **errp) 985 { 986 ERRP_GUARD(); 987 MachineState *ms = MACHINE(obj); 988 BootConfiguration *config = NULL; 989 990 if (!visit_type_BootConfiguration(v, name, &config, errp)) { 991 return; 992 } 993 if (config->order) { 994 validate_bootdevices(config->order, errp); 995 if (*errp) { 996 goto out_free; 997 } 998 } 999 if (config->once) { 1000 validate_bootdevices(config->once, errp); 1001 if (*errp) { 1002 goto out_free; 1003 } 1004 } 1005 1006 machine_copy_boot_config(ms, config); 1007 /* Strings live in ms->boot_config. */ 1008 free(config); 1009 return; 1010 1011 out_free: 1012 qapi_free_BootConfiguration(config); 1013 } 1014 1015 void machine_add_audiodev_property(MachineClass *mc) 1016 { 1017 ObjectClass *oc = OBJECT_CLASS(mc); 1018 1019 object_class_property_add_str(oc, "audiodev", 1020 machine_get_audiodev, 1021 machine_set_audiodev); 1022 object_class_property_set_description(oc, "audiodev", 1023 "Audiodev to use for default machine devices"); 1024 } 1025 1026 static bool create_default_memdev(MachineState *ms, const char *path, 1027 Error **errp) 1028 { 1029 Object *obj; 1030 MachineClass *mc = MACHINE_GET_CLASS(ms); 1031 bool r = false; 1032 1033 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 1034 if (path) { 1035 if (!object_property_set_str(obj, "mem-path", path, errp)) { 1036 goto out; 1037 } 1038 } 1039 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { 1040 goto out; 1041 } 1042 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 1043 obj); 1044 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 1045 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 1046 false, errp)) { 1047 goto out; 1048 } 1049 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { 1050 goto out; 1051 } 1052 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); 1053 1054 out: 1055 object_unref(obj); 1056 return r; 1057 } 1058 1059 static void machine_class_init(ObjectClass *oc, void *data) 1060 { 1061 MachineClass *mc = MACHINE_CLASS(oc); 1062 1063 /* Default 128 MB as guest ram size */ 1064 mc->default_ram_size = 128 * MiB; 1065 mc->rom_file_has_mr = true; 1066 /* 1067 * SMBIOS 3.1.0 7.18.5 Memory Device — Extended Size 1068 * use max possible value that could be encoded into 1069 * 'Extended Size' field (2047Tb). 1070 */ 1071 mc->smbios_memory_device_size = 2047 * TiB; 1072 1073 /* numa node memory size aligned on 8MB by default. 1074 * On Linux, each node's border has to be 8MB aligned 1075 */ 1076 mc->numa_mem_align_shift = 23; 1077 1078 mc->create_default_memdev = create_default_memdev; 1079 1080 object_class_property_add_str(oc, "kernel", 1081 machine_get_kernel, machine_set_kernel); 1082 object_class_property_set_description(oc, "kernel", 1083 "Linux kernel image file"); 1084 1085 object_class_property_add_str(oc, "initrd", 1086 machine_get_initrd, machine_set_initrd); 1087 object_class_property_set_description(oc, "initrd", 1088 "Linux initial ramdisk file"); 1089 1090 object_class_property_add_str(oc, "append", 1091 machine_get_append, machine_set_append); 1092 object_class_property_set_description(oc, "append", 1093 "Linux kernel command line"); 1094 1095 object_class_property_add_str(oc, "dtb", 1096 machine_get_dtb, machine_set_dtb); 1097 object_class_property_set_description(oc, "dtb", 1098 "Linux kernel device tree file"); 1099 1100 object_class_property_add_str(oc, "dumpdtb", 1101 machine_get_dumpdtb, machine_set_dumpdtb); 1102 object_class_property_set_description(oc, "dumpdtb", 1103 "Dump current dtb to a file and quit"); 1104 1105 object_class_property_add(oc, "boot", "BootConfiguration", 1106 machine_get_boot, machine_set_boot, 1107 NULL, NULL); 1108 object_class_property_set_description(oc, "boot", 1109 "Boot configuration"); 1110 1111 object_class_property_add(oc, "smp", "SMPConfiguration", 1112 machine_get_smp, machine_set_smp, 1113 NULL, NULL); 1114 object_class_property_set_description(oc, "smp", 1115 "CPU topology"); 1116 1117 object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper", 1118 machine_get_smp_cache, machine_set_smp_cache, NULL, NULL); 1119 object_class_property_set_description(oc, "smp-cache", 1120 "Cache properties list for SMP machine"); 1121 1122 object_class_property_add(oc, "phandle-start", "int", 1123 machine_get_phandle_start, machine_set_phandle_start, 1124 NULL, NULL); 1125 object_class_property_set_description(oc, "phandle-start", 1126 "The first phandle ID we may generate dynamically"); 1127 1128 object_class_property_add_str(oc, "dt-compatible", 1129 machine_get_dt_compatible, machine_set_dt_compatible); 1130 object_class_property_set_description(oc, "dt-compatible", 1131 "Overrides the \"compatible\" property of the dt root node"); 1132 1133 object_class_property_add_bool(oc, "dump-guest-core", 1134 machine_get_dump_guest_core, machine_set_dump_guest_core); 1135 object_class_property_set_description(oc, "dump-guest-core", 1136 "Include guest memory in a core dump"); 1137 1138 object_class_property_add_bool(oc, "mem-merge", 1139 machine_get_mem_merge, machine_set_mem_merge); 1140 object_class_property_set_description(oc, "mem-merge", 1141 "Enable/disable memory merge support"); 1142 1143 object_class_property_add_bool(oc, "usb", 1144 machine_get_usb, machine_set_usb); 1145 object_class_property_set_description(oc, "usb", 1146 "Set on/off to enable/disable usb"); 1147 1148 object_class_property_add_bool(oc, "graphics", 1149 machine_get_graphics, machine_set_graphics); 1150 object_class_property_set_description(oc, "graphics", 1151 "Set on/off to enable/disable graphics emulation"); 1152 1153 object_class_property_add_str(oc, "firmware", 1154 machine_get_firmware, machine_set_firmware); 1155 object_class_property_set_description(oc, "firmware", 1156 "Firmware image"); 1157 1158 object_class_property_add_bool(oc, "suppress-vmdesc", 1159 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 1160 object_class_property_set_description(oc, "suppress-vmdesc", 1161 "Set on to disable self-describing migration"); 1162 1163 object_class_property_add_link(oc, "confidential-guest-support", 1164 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 1165 offsetof(MachineState, cgs), 1166 machine_check_confidential_guest_support, 1167 OBJ_PROP_LINK_STRONG); 1168 object_class_property_set_description(oc, "confidential-guest-support", 1169 "Set confidential guest scheme to support"); 1170 1171 /* For compatibility */ 1172 object_class_property_add_str(oc, "memory-encryption", 1173 machine_get_memory_encryption, machine_set_memory_encryption); 1174 object_class_property_set_description(oc, "memory-encryption", 1175 "Set memory encryption object to use"); 1176 1177 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, 1178 offsetof(MachineState, memdev), object_property_allow_set_link, 1179 OBJ_PROP_LINK_STRONG); 1180 object_class_property_set_description(oc, "memory-backend", 1181 "Set RAM backend" 1182 "Valid value is ID of hostmem based backend"); 1183 1184 object_class_property_add(oc, "memory", "MemorySizeConfiguration", 1185 machine_get_mem, machine_set_mem, 1186 NULL, NULL); 1187 object_class_property_set_description(oc, "memory", 1188 "Memory size configuration"); 1189 } 1190 1191 static void machine_class_base_init(ObjectClass *oc, void *data) 1192 { 1193 MachineClass *mc = MACHINE_CLASS(oc); 1194 mc->max_cpus = mc->max_cpus ?: 1; 1195 mc->min_cpus = mc->min_cpus ?: 1; 1196 mc->default_cpus = mc->default_cpus ?: 1; 1197 1198 if (!object_class_is_abstract(oc)) { 1199 const char *cname = object_class_get_name(oc); 1200 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 1201 mc->name = g_strndup(cname, 1202 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 1203 mc->compat_props = g_ptr_array_new(); 1204 } 1205 } 1206 1207 static void machine_initfn(Object *obj) 1208 { 1209 MachineState *ms = MACHINE(obj); 1210 MachineClass *mc = MACHINE_GET_CLASS(obj); 1211 1212 container_get(obj, "/peripheral"); 1213 container_get(obj, "/peripheral-anon"); 1214 1215 ms->dump_guest_core = true; 1216 ms->mem_merge = (QEMU_MADV_MERGEABLE != QEMU_MADV_INVALID); 1217 ms->enable_graphics = true; 1218 ms->kernel_cmdline = g_strdup(""); 1219 ms->ram_size = mc->default_ram_size; 1220 ms->maxram_size = mc->default_ram_size; 1221 1222 if (mc->nvdimm_supported) { 1223 ms->nvdimms_state = g_new0(NVDIMMState, 1); 1224 object_property_add_bool(obj, "nvdimm", 1225 machine_get_nvdimm, machine_set_nvdimm); 1226 object_property_set_description(obj, "nvdimm", 1227 "Set on/off to enable/disable " 1228 "NVDIMM instantiation"); 1229 1230 object_property_add_str(obj, "nvdimm-persistence", 1231 machine_get_nvdimm_persistence, 1232 machine_set_nvdimm_persistence); 1233 object_property_set_description(obj, "nvdimm-persistence", 1234 "Set NVDIMM persistence" 1235 "Valid values are cpu, mem-ctrl"); 1236 } 1237 1238 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 1239 ms->numa_state = g_new0(NumaState, 1); 1240 object_property_add_bool(obj, "hmat", 1241 machine_get_hmat, machine_set_hmat); 1242 object_property_set_description(obj, "hmat", 1243 "Set on/off to enable/disable " 1244 "ACPI Heterogeneous Memory Attribute " 1245 "Table (HMAT)"); 1246 } 1247 1248 /* default to mc->default_cpus */ 1249 ms->smp.cpus = mc->default_cpus; 1250 ms->smp.max_cpus = mc->default_cpus; 1251 ms->smp.drawers = 1; 1252 ms->smp.books = 1; 1253 ms->smp.sockets = 1; 1254 ms->smp.dies = 1; 1255 ms->smp.clusters = 1; 1256 ms->smp.modules = 1; 1257 ms->smp.cores = 1; 1258 ms->smp.threads = 1; 1259 1260 for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { 1261 ms->smp_cache.props[i].cache = (CacheLevelAndType)i; 1262 ms->smp_cache.props[i].topology = CPU_TOPOLOGY_LEVEL_DEFAULT; 1263 } 1264 1265 machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); 1266 } 1267 1268 static void machine_finalize(Object *obj) 1269 { 1270 MachineState *ms = MACHINE(obj); 1271 1272 machine_free_boot_config(ms); 1273 g_free(ms->kernel_filename); 1274 g_free(ms->initrd_filename); 1275 g_free(ms->kernel_cmdline); 1276 g_free(ms->dtb); 1277 g_free(ms->dumpdtb); 1278 g_free(ms->dt_compatible); 1279 g_free(ms->firmware); 1280 g_free(ms->device_memory); 1281 g_free(ms->nvdimms_state); 1282 g_free(ms->numa_state); 1283 g_free(ms->audiodev); 1284 } 1285 1286 bool machine_usb(MachineState *machine) 1287 { 1288 return machine->usb; 1289 } 1290 1291 int machine_phandle_start(MachineState *machine) 1292 { 1293 return machine->phandle_start; 1294 } 1295 1296 bool machine_dump_guest_core(MachineState *machine) 1297 { 1298 return machine->dump_guest_core; 1299 } 1300 1301 bool machine_mem_merge(MachineState *machine) 1302 { 1303 return machine->mem_merge; 1304 } 1305 1306 bool machine_require_guest_memfd(MachineState *machine) 1307 { 1308 return machine->cgs && machine->cgs->require_guest_memfd; 1309 } 1310 1311 static char *cpu_slot_to_string(const CPUArchId *cpu) 1312 { 1313 GString *s = g_string_new(NULL); 1314 if (cpu->props.has_socket_id) { 1315 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1316 } 1317 if (cpu->props.has_die_id) { 1318 if (s->len) { 1319 g_string_append_printf(s, ", "); 1320 } 1321 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1322 } 1323 if (cpu->props.has_cluster_id) { 1324 if (s->len) { 1325 g_string_append_printf(s, ", "); 1326 } 1327 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); 1328 } 1329 if (cpu->props.has_module_id) { 1330 if (s->len) { 1331 g_string_append_printf(s, ", "); 1332 } 1333 g_string_append_printf(s, "module-id: %"PRId64, cpu->props.module_id); 1334 } 1335 if (cpu->props.has_core_id) { 1336 if (s->len) { 1337 g_string_append_printf(s, ", "); 1338 } 1339 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1340 } 1341 if (cpu->props.has_thread_id) { 1342 if (s->len) { 1343 g_string_append_printf(s, ", "); 1344 } 1345 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1346 } 1347 return g_string_free(s, false); 1348 } 1349 1350 static void numa_validate_initiator(NumaState *numa_state) 1351 { 1352 int i; 1353 NodeInfo *numa_info = numa_state->nodes; 1354 1355 for (i = 0; i < numa_state->num_nodes; i++) { 1356 if (numa_info[i].initiator == MAX_NODES) { 1357 continue; 1358 } 1359 1360 if (!numa_info[numa_info[i].initiator].present) { 1361 error_report("NUMA node %" PRIu16 " is missing, use " 1362 "'-numa node' option to declare it first", 1363 numa_info[i].initiator); 1364 exit(1); 1365 } 1366 1367 if (!numa_info[numa_info[i].initiator].has_cpu) { 1368 error_report("The initiator of NUMA node %d is invalid", i); 1369 exit(1); 1370 } 1371 } 1372 } 1373 1374 static void machine_numa_finish_cpu_init(MachineState *machine) 1375 { 1376 int i; 1377 bool default_mapping; 1378 GString *s = g_string_new(NULL); 1379 MachineClass *mc = MACHINE_GET_CLASS(machine); 1380 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1381 1382 assert(machine->numa_state->num_nodes); 1383 for (i = 0; i < possible_cpus->len; i++) { 1384 if (possible_cpus->cpus[i].props.has_node_id) { 1385 break; 1386 } 1387 } 1388 default_mapping = (i == possible_cpus->len); 1389 1390 for (i = 0; i < possible_cpus->len; i++) { 1391 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1392 1393 if (!cpu_slot->props.has_node_id) { 1394 /* fetch default mapping from board and enable it */ 1395 CpuInstanceProperties props = cpu_slot->props; 1396 1397 props.node_id = mc->get_default_cpu_node_id(machine, i); 1398 if (!default_mapping) { 1399 /* record slots with not set mapping, 1400 * TODO: make it hard error in future */ 1401 char *cpu_str = cpu_slot_to_string(cpu_slot); 1402 g_string_append_printf(s, "%sCPU %d [%s]", 1403 s->len ? ", " : "", i, cpu_str); 1404 g_free(cpu_str); 1405 1406 /* non mapped cpus used to fallback to node 0 */ 1407 props.node_id = 0; 1408 } 1409 1410 props.has_node_id = true; 1411 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1412 } 1413 } 1414 1415 if (machine->numa_state->hmat_enabled) { 1416 numa_validate_initiator(machine->numa_state); 1417 } 1418 1419 if (s->len && !qtest_enabled()) { 1420 warn_report("CPU(s) not present in any NUMA nodes: %s", 1421 s->str); 1422 warn_report("All CPU(s) up to maxcpus should be described " 1423 "in NUMA config, ability to start up with partial NUMA " 1424 "mappings is obsoleted and will be removed in future"); 1425 } 1426 g_string_free(s, true); 1427 } 1428 1429 static void validate_cpu_cluster_to_numa_boundary(MachineState *ms) 1430 { 1431 MachineClass *mc = MACHINE_GET_CLASS(ms); 1432 NumaState *state = ms->numa_state; 1433 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1434 const CPUArchId *cpus = possible_cpus->cpus; 1435 int i, j; 1436 1437 if (qtest_enabled() || state->num_nodes <= 1 || possible_cpus->len <= 1) { 1438 return; 1439 } 1440 1441 /* 1442 * The Linux scheduling domain can't be parsed when the multiple CPUs 1443 * in one cluster have been associated with different NUMA nodes. However, 1444 * it's fine to associate one NUMA node with CPUs in different clusters. 1445 */ 1446 for (i = 0; i < possible_cpus->len; i++) { 1447 for (j = i + 1; j < possible_cpus->len; j++) { 1448 if (cpus[i].props.has_socket_id && 1449 cpus[i].props.has_cluster_id && 1450 cpus[i].props.has_node_id && 1451 cpus[j].props.has_socket_id && 1452 cpus[j].props.has_cluster_id && 1453 cpus[j].props.has_node_id && 1454 cpus[i].props.socket_id == cpus[j].props.socket_id && 1455 cpus[i].props.cluster_id == cpus[j].props.cluster_id && 1456 cpus[i].props.node_id != cpus[j].props.node_id) { 1457 warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64 1458 " have been associated with node-%" PRId64 " and node-%" PRId64 1459 " respectively. It can cause OSes like Linux to" 1460 " misbehave", i, j, cpus[i].props.socket_id, 1461 cpus[i].props.cluster_id, cpus[i].props.node_id, 1462 cpus[j].props.node_id); 1463 } 1464 } 1465 } 1466 } 1467 1468 MemoryRegion *machine_consume_memdev(MachineState *machine, 1469 HostMemoryBackend *backend) 1470 { 1471 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1472 1473 if (host_memory_backend_is_mapped(backend)) { 1474 error_report("memory backend %s can't be used multiple times.", 1475 object_get_canonical_path_component(OBJECT(backend))); 1476 exit(EXIT_FAILURE); 1477 } 1478 host_memory_backend_set_mapped(backend, true); 1479 vmstate_register_ram_global(ret); 1480 return ret; 1481 } 1482 1483 const char *machine_class_default_cpu_type(MachineClass *mc) 1484 { 1485 if (mc->valid_cpu_types && !mc->valid_cpu_types[1]) { 1486 /* Only a single CPU type allowed: use it as default. */ 1487 return mc->valid_cpu_types[0]; 1488 } 1489 return mc->default_cpu_type; 1490 } 1491 1492 static bool is_cpu_type_supported(const MachineState *machine, Error **errp) 1493 { 1494 MachineClass *mc = MACHINE_GET_CLASS(machine); 1495 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1496 CPUClass *cc; 1497 int i; 1498 1499 /* 1500 * Check if the user specified CPU type is supported when the valid 1501 * CPU types have been determined. Note that the user specified CPU 1502 * type is provided through '-cpu' option. 1503 */ 1504 if (mc->valid_cpu_types) { 1505 assert(mc->valid_cpu_types[0] != NULL); 1506 for (i = 0; mc->valid_cpu_types[i]; i++) { 1507 if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) { 1508 break; 1509 } 1510 } 1511 1512 /* The user specified CPU type isn't valid */ 1513 if (!mc->valid_cpu_types[i]) { 1514 g_autofree char *requested = cpu_model_from_type(machine->cpu_type); 1515 error_setg(errp, "Invalid CPU model: %s", requested); 1516 if (!mc->valid_cpu_types[1]) { 1517 g_autofree char *model = cpu_model_from_type( 1518 mc->valid_cpu_types[0]); 1519 error_append_hint(errp, "The only valid type is: %s\n", model); 1520 } else { 1521 error_append_hint(errp, "The valid models are: "); 1522 for (i = 0; mc->valid_cpu_types[i]; i++) { 1523 g_autofree char *model = cpu_model_from_type( 1524 mc->valid_cpu_types[i]); 1525 error_append_hint(errp, "%s%s", 1526 model, 1527 mc->valid_cpu_types[i + 1] ? ", " : ""); 1528 } 1529 error_append_hint(errp, "\n"); 1530 } 1531 1532 return false; 1533 } 1534 } 1535 1536 /* Check if CPU type is deprecated and warn if so */ 1537 cc = CPU_CLASS(oc); 1538 assert(cc != NULL); 1539 if (cc->deprecation_note) { 1540 warn_report("CPU model %s is deprecated -- %s", 1541 machine->cpu_type, cc->deprecation_note); 1542 } 1543 1544 return true; 1545 } 1546 1547 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) 1548 { 1549 ERRP_GUARD(); 1550 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1551 1552 /* This checkpoint is required by replay to separate prior clock 1553 reading from the other reads, because timer polling functions query 1554 clock values from the log. */ 1555 replay_checkpoint(CHECKPOINT_INIT); 1556 1557 if (!xen_enabled()) { 1558 /* On 32-bit hosts, QEMU is limited by virtual address space */ 1559 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 1560 error_setg(errp, "at most 2047 MB RAM can be simulated"); 1561 return; 1562 } 1563 } 1564 1565 if (machine->memdev) { 1566 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), 1567 "size", &error_abort); 1568 if (backend_size != machine->ram_size) { 1569 error_setg(errp, "Machine memory size does not match the size of the memory backend"); 1570 return; 1571 } 1572 } else if (machine_class->default_ram_id && machine->ram_size && 1573 numa_uses_legacy_mem()) { 1574 if (object_property_find(object_get_objects_root(), 1575 machine_class->default_ram_id)) { 1576 error_setg(errp, "object's id '%s' is reserved for the default" 1577 " RAM backend, it can't be used for any other purposes", 1578 machine_class->default_ram_id); 1579 error_append_hint(errp, 1580 "Change the object's 'id' to something else or disable" 1581 " automatic creation of the default RAM backend by setting" 1582 " 'memory-backend=%s' with '-machine'.\n", 1583 machine_class->default_ram_id); 1584 return; 1585 } 1586 1587 if (!machine_class->create_default_memdev(current_machine, mem_path, 1588 errp)) { 1589 return; 1590 } 1591 } 1592 1593 if (machine->numa_state) { 1594 numa_complete_configuration(machine); 1595 if (machine->numa_state->num_nodes) { 1596 machine_numa_finish_cpu_init(machine); 1597 if (machine_class->cpu_cluster_has_numa_boundary) { 1598 validate_cpu_cluster_to_numa_boundary(machine); 1599 } 1600 } 1601 } 1602 1603 if (!machine->ram && machine->memdev) { 1604 machine->ram = machine_consume_memdev(machine, machine->memdev); 1605 } 1606 1607 /* Check if the CPU type is supported */ 1608 if (machine->cpu_type && !is_cpu_type_supported(machine, errp)) { 1609 return; 1610 } 1611 1612 if (machine->cgs) { 1613 /* 1614 * With confidential guests, the host can't see the real 1615 * contents of RAM, so there's no point in it trying to merge 1616 * areas. 1617 */ 1618 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1619 1620 /* 1621 * Virtio devices can't count on directly accessing guest 1622 * memory, so they need iommu_platform=on to use normal DMA 1623 * mechanisms. That requires also disabling legacy virtio 1624 * support for those virtio pci devices which allow it. 1625 */ 1626 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1627 "on", true); 1628 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1629 "on", false); 1630 } 1631 1632 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1633 machine_class->init(machine); 1634 phase_advance(PHASE_MACHINE_INITIALIZED); 1635 } 1636 1637 static NotifierList machine_init_done_notifiers = 1638 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1639 1640 void qemu_add_machine_init_done_notifier(Notifier *notify) 1641 { 1642 notifier_list_add(&machine_init_done_notifiers, notify); 1643 if (phase_check(PHASE_MACHINE_READY)) { 1644 notify->notify(notify, NULL); 1645 } 1646 } 1647 1648 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1649 { 1650 notifier_remove(notify); 1651 } 1652 1653 void qdev_machine_creation_done(void) 1654 { 1655 cpu_synchronize_all_post_init(); 1656 1657 if (current_machine->boot_config.once) { 1658 qemu_boot_set(current_machine->boot_config.once, &error_fatal); 1659 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); 1660 } 1661 1662 /* 1663 * ok, initial machine setup is done, starting from now we can 1664 * only create hotpluggable devices 1665 */ 1666 phase_advance(PHASE_MACHINE_READY); 1667 qdev_assert_realized_properly(); 1668 1669 /* TODO: once all bus devices are qdevified, this should be done 1670 * when bus is created by qdev.c */ 1671 /* 1672 * This is where we arrange for the sysbus to be reset when the 1673 * whole simulation is reset. In turn, resetting the sysbus will cause 1674 * all devices hanging off it (and all their child buses, recursively) 1675 * to be reset. Note that this will *not* reset any Device objects 1676 * which are not attached to some part of the qbus tree! 1677 */ 1678 qemu_register_resettable(OBJECT(sysbus_get_default())); 1679 1680 notifier_list_notify(&machine_init_done_notifiers, NULL); 1681 1682 if (rom_check_and_register_reset() != 0) { 1683 exit(1); 1684 } 1685 1686 replay_start(); 1687 1688 /* This checkpoint is required by replay to separate prior clock 1689 reading from the other reads, because timer polling functions query 1690 clock values from the log. */ 1691 replay_checkpoint(CHECKPOINT_RESET); 1692 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1693 register_global_state(); 1694 } 1695 1696 static const TypeInfo machine_info = { 1697 .name = TYPE_MACHINE, 1698 .parent = TYPE_OBJECT, 1699 .abstract = true, 1700 .class_size = sizeof(MachineClass), 1701 .class_init = machine_class_init, 1702 .class_base_init = machine_class_base_init, 1703 .instance_size = sizeof(MachineState), 1704 .instance_init = machine_initfn, 1705 .instance_finalize = machine_finalize, 1706 }; 1707 1708 static void machine_register_types(void) 1709 { 1710 type_register_static(&machine_info); 1711 } 1712 1713 type_init(machine_register_types) 1714