1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qemu/accel.h" 16 #include "sysemu/replay.h" 17 #include "hw/boards.h" 18 #include "hw/loader.h" 19 #include "qemu/error-report.h" 20 #include "qapi/error.h" 21 #include "qapi/qapi-visit-machine.h" 22 #include "qemu/madvise.h" 23 #include "qom/object_interfaces.h" 24 #include "sysemu/cpus.h" 25 #include "sysemu/sysemu.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/xen.h" 29 #include "sysemu/qtest.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/mem/nvdimm.h" 32 #include "migration/global_state.h" 33 #include "exec/confidential-guest-support.h" 34 #include "hw/virtio/virtio-pci.h" 35 #include "hw/virtio/virtio-net.h" 36 #include "hw/virtio/virtio-iommu.h" 37 #include "audio/audio.h" 38 39 GlobalProperty hw_compat_9_2[] = {}; 40 const size_t hw_compat_9_2_len = G_N_ELEMENTS(hw_compat_9_2); 41 42 GlobalProperty hw_compat_9_1[] = { 43 { TYPE_PCI_DEVICE, "x-pcie-ext-tag", "false" }, 44 }; 45 const size_t hw_compat_9_1_len = G_N_ELEMENTS(hw_compat_9_1); 46 47 GlobalProperty hw_compat_9_0[] = { 48 {"arm-cpu", "backcompat-cntfrq", "true" }, 49 { "scsi-hd", "migrate-emulated-scsi-request", "false" }, 50 { "scsi-cd", "migrate-emulated-scsi-request", "false" }, 51 {"vfio-pci", "skip-vsc-check", "false" }, 52 { "virtio-pci", "x-pcie-pm-no-soft-reset", "off" }, 53 {"sd-card", "spec_version", "2" }, 54 }; 55 const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0); 56 57 GlobalProperty hw_compat_8_2[] = { 58 { "migration", "zero-page-detection", "legacy"}, 59 { TYPE_VIRTIO_IOMMU_PCI, "granule", "4k" }, 60 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "64" }, 61 { "virtio-gpu-device", "x-scanout-vmstate-version", "1" }, 62 }; 63 const size_t hw_compat_8_2_len = G_N_ELEMENTS(hw_compat_8_2); 64 65 GlobalProperty hw_compat_8_1[] = { 66 { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" }, 67 { "ramfb", "x-migrate", "off" }, 68 { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" }, 69 { "igb", "x-pcie-flr-init", "off" }, 70 { TYPE_VIRTIO_NET, "host_uso", "off"}, 71 { TYPE_VIRTIO_NET, "guest_uso4", "off"}, 72 { TYPE_VIRTIO_NET, "guest_uso6", "off"}, 73 }; 74 const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1); 75 76 GlobalProperty hw_compat_8_0[] = { 77 { "migration", "multifd-flush-after-each-section", "on"}, 78 { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, 79 }; 80 const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); 81 82 GlobalProperty hw_compat_7_2[] = { 83 { "e1000e", "migrate-timadj", "off" }, 84 { "virtio-mem", "x-early-migration", "false" }, 85 { "migration", "x-preempt-pre-7-2", "true" }, 86 { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" }, 87 }; 88 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); 89 90 GlobalProperty hw_compat_7_1[] = { 91 { "virtio-device", "queue_reset", "false" }, 92 { "virtio-rng-pci", "vectors", "0" }, 93 { "virtio-rng-pci-transitional", "vectors", "0" }, 94 { "virtio-rng-pci-non-transitional", "vectors", "0" }, 95 }; 96 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); 97 98 GlobalProperty hw_compat_7_0[] = { 99 { "arm-gicv3-common", "force-8-bit-prio", "on" }, 100 { "nvme-ns", "eui64-default", "on"}, 101 }; 102 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); 103 104 GlobalProperty hw_compat_6_2[] = { 105 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, 106 }; 107 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); 108 109 GlobalProperty hw_compat_6_1[] = { 110 { "vhost-user-vsock-device", "seqpacket", "off" }, 111 { "nvme-ns", "shared", "off" }, 112 }; 113 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); 114 115 GlobalProperty hw_compat_6_0[] = { 116 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 117 { "i8042", "extended-state", "false"}, 118 { "nvme-ns", "eui64-default", "off"}, 119 { "e1000", "init-vet", "off" }, 120 { "e1000e", "init-vet", "off" }, 121 { "vhost-vsock-device", "seqpacket", "off" }, 122 }; 123 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 124 125 GlobalProperty hw_compat_5_2[] = { 126 { "ICH9-LPC", "smm-compat", "on"}, 127 { "PIIX4_PM", "smm-compat", "on"}, 128 { "virtio-blk-device", "report-discard-granularity", "off" }, 129 { "virtio-net-pci-base", "vectors", "3"}, 130 { "nvme", "msix-exclusive-bar", "on"}, 131 }; 132 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 133 134 GlobalProperty hw_compat_5_1[] = { 135 { "vhost-scsi", "num_queues", "1"}, 136 { "vhost-user-blk", "num-queues", "1"}, 137 { "vhost-user-scsi", "num_queues", "1"}, 138 { "virtio-blk-device", "num-queues", "1"}, 139 { "virtio-scsi-device", "num_queues", "1"}, 140 { "nvme", "use-intel-id", "on"}, 141 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 142 { "pl011", "migrate-clk", "off" }, 143 { "virtio-pci", "x-ats-page-aligned", "off"}, 144 }; 145 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 146 147 GlobalProperty hw_compat_5_0[] = { 148 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 149 { "virtio-balloon-device", "page-poison", "false" }, 150 { "vmport", "x-read-set-eax", "off" }, 151 { "vmport", "x-signal-unsupported-cmd", "off" }, 152 { "vmport", "x-report-vmx-type", "off" }, 153 { "vmport", "x-cmds-v2", "off" }, 154 { "virtio-device", "x-disable-legacy-check", "true" }, 155 }; 156 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 157 158 GlobalProperty hw_compat_4_2[] = { 159 { "virtio-blk-device", "queue-size", "128"}, 160 { "virtio-scsi-device", "virtqueue_size", "128"}, 161 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 162 { "virtio-blk-device", "seg-max-adjust", "off"}, 163 { "virtio-scsi-device", "seg_max_adjust", "off"}, 164 { "vhost-blk-device", "seg_max_adjust", "off"}, 165 { "usb-host", "suppress-remote-wake", "off" }, 166 { "usb-redir", "suppress-remote-wake", "off" }, 167 { "qxl", "revision", "4" }, 168 { "qxl-vga", "revision", "4" }, 169 { "fw_cfg", "acpi-mr-restore", "false" }, 170 { "virtio-device", "use-disabled-flag", "false" }, 171 }; 172 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 173 174 GlobalProperty hw_compat_4_1[] = { 175 { "virtio-pci", "x-pcie-flr-init", "off" }, 176 }; 177 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 178 179 GlobalProperty hw_compat_4_0[] = { 180 { "VGA", "edid", "false" }, 181 { "secondary-vga", "edid", "false" }, 182 { "bochs-display", "edid", "false" }, 183 { "virtio-vga", "edid", "false" }, 184 { "virtio-gpu-device", "edid", "false" }, 185 { "virtio-device", "use-started", "false" }, 186 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 187 { "pl031", "migrate-tick-offset", "false" }, 188 }; 189 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 190 191 GlobalProperty hw_compat_3_1[] = { 192 { "pcie-root-port", "x-speed", "2_5" }, 193 { "pcie-root-port", "x-width", "1" }, 194 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 195 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 196 { "tpm-crb", "ppi", "false" }, 197 { "tpm-tis", "ppi", "false" }, 198 { "usb-kbd", "serial", "42" }, 199 { "usb-mouse", "serial", "42" }, 200 { "usb-tablet", "serial", "42" }, 201 { "virtio-blk-device", "discard", "false" }, 202 { "virtio-blk-device", "write-zeroes", "false" }, 203 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 204 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 205 }; 206 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 207 208 GlobalProperty hw_compat_3_0[] = {}; 209 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 210 211 GlobalProperty hw_compat_2_12[] = { 212 { "hda-audio", "use-timer", "false" }, 213 { "cirrus-vga", "global-vmstate", "true" }, 214 { "VGA", "global-vmstate", "true" }, 215 { "vmware-svga", "global-vmstate", "true" }, 216 { "qxl-vga", "global-vmstate", "true" }, 217 }; 218 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 219 220 GlobalProperty hw_compat_2_11[] = { 221 { "hpet", "hpet-offset-saved", "false" }, 222 { "virtio-blk-pci", "vectors", "2" }, 223 { "vhost-user-blk-pci", "vectors", "2" }, 224 { "e1000", "migrate_tso_props", "off" }, 225 }; 226 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 227 228 GlobalProperty hw_compat_2_10[] = { 229 { "virtio-mouse-device", "wheel-axis", "false" }, 230 { "virtio-tablet-device", "wheel-axis", "false" }, 231 }; 232 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 233 234 GlobalProperty hw_compat_2_9[] = { 235 { "pci-bridge", "shpc", "off" }, 236 { "intel-iommu", "pt", "off" }, 237 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 238 { "pcie-root-port", "x-migrate-msix", "false" }, 239 }; 240 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 241 242 GlobalProperty hw_compat_2_8[] = { 243 { "fw_cfg_mem", "x-file-slots", "0x10" }, 244 { "fw_cfg_io", "x-file-slots", "0x10" }, 245 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 246 { "pci-bridge", "shpc", "on" }, 247 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 248 { "virtio-pci", "x-pcie-deverr-init", "off" }, 249 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 250 { "virtio-pci", "x-pcie-pm-init", "off" }, 251 { "cirrus-vga", "vgamem_mb", "8" }, 252 { "isa-cirrus-vga", "vgamem_mb", "8" }, 253 }; 254 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 255 256 GlobalProperty hw_compat_2_7[] = { 257 { "virtio-pci", "page-per-vq", "on" }, 258 { "virtio-serial-device", "emergency-write", "off" }, 259 { "ioapic", "version", "0x11" }, 260 { "intel-iommu", "x-buggy-eim", "true" }, 261 { "virtio-pci", "x-ignore-backend-features", "on" }, 262 }; 263 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 264 265 GlobalProperty hw_compat_2_6[] = { 266 { "virtio-mmio", "format_transport_address", "off" }, 267 /* Optional because not all virtio-pci devices support legacy mode */ 268 { "virtio-pci", "disable-modern", "on", .optional = true }, 269 { "virtio-pci", "disable-legacy", "off", .optional = true }, 270 }; 271 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 272 273 GlobalProperty hw_compat_2_5[] = { 274 { "isa-fdc", "fallback", "144" }, 275 { "pvscsi", "x-old-pci-configuration", "on" }, 276 { "pvscsi", "x-disable-pcie", "on" }, 277 { "vmxnet3", "x-old-msi-offsets", "on" }, 278 { "vmxnet3", "x-disable-pcie", "on" }, 279 }; 280 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 281 282 GlobalProperty hw_compat_2_4[] = { 283 { "e1000", "extra_mac_registers", "off" }, 284 { "virtio-pci", "x-disable-pcie", "on" }, 285 { "virtio-pci", "migrate-extra", "off" }, 286 { "fw_cfg_mem", "dma_enabled", "off" }, 287 { "fw_cfg_io", "dma_enabled", "off" } 288 }; 289 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 290 291 MachineState *current_machine; 292 293 static char *machine_get_kernel(Object *obj, Error **errp) 294 { 295 MachineState *ms = MACHINE(obj); 296 297 return g_strdup(ms->kernel_filename); 298 } 299 300 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 301 { 302 MachineState *ms = MACHINE(obj); 303 304 g_free(ms->kernel_filename); 305 ms->kernel_filename = g_strdup(value); 306 } 307 308 static char *machine_get_shim(Object *obj, Error **errp) 309 { 310 MachineState *ms = MACHINE(obj); 311 312 return g_strdup(ms->shim_filename); 313 } 314 315 static void machine_set_shim(Object *obj, const char *value, Error **errp) 316 { 317 MachineState *ms = MACHINE(obj); 318 319 g_free(ms->shim_filename); 320 ms->shim_filename = g_strdup(value); 321 } 322 323 static char *machine_get_initrd(Object *obj, Error **errp) 324 { 325 MachineState *ms = MACHINE(obj); 326 327 return g_strdup(ms->initrd_filename); 328 } 329 330 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 331 { 332 MachineState *ms = MACHINE(obj); 333 334 g_free(ms->initrd_filename); 335 ms->initrd_filename = g_strdup(value); 336 } 337 338 static char *machine_get_append(Object *obj, Error **errp) 339 { 340 MachineState *ms = MACHINE(obj); 341 342 return g_strdup(ms->kernel_cmdline); 343 } 344 345 static void machine_set_append(Object *obj, const char *value, Error **errp) 346 { 347 MachineState *ms = MACHINE(obj); 348 349 g_free(ms->kernel_cmdline); 350 ms->kernel_cmdline = g_strdup(value); 351 } 352 353 static char *machine_get_dtb(Object *obj, Error **errp) 354 { 355 MachineState *ms = MACHINE(obj); 356 357 return g_strdup(ms->dtb); 358 } 359 360 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 361 { 362 MachineState *ms = MACHINE(obj); 363 364 g_free(ms->dtb); 365 ms->dtb = g_strdup(value); 366 } 367 368 static char *machine_get_dumpdtb(Object *obj, Error **errp) 369 { 370 MachineState *ms = MACHINE(obj); 371 372 return g_strdup(ms->dumpdtb); 373 } 374 375 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 376 { 377 MachineState *ms = MACHINE(obj); 378 379 g_free(ms->dumpdtb); 380 ms->dumpdtb = g_strdup(value); 381 } 382 383 static void machine_get_phandle_start(Object *obj, Visitor *v, 384 const char *name, void *opaque, 385 Error **errp) 386 { 387 MachineState *ms = MACHINE(obj); 388 int64_t value = ms->phandle_start; 389 390 visit_type_int(v, name, &value, errp); 391 } 392 393 static void machine_set_phandle_start(Object *obj, Visitor *v, 394 const char *name, void *opaque, 395 Error **errp) 396 { 397 MachineState *ms = MACHINE(obj); 398 int64_t value; 399 400 if (!visit_type_int(v, name, &value, errp)) { 401 return; 402 } 403 404 ms->phandle_start = value; 405 } 406 407 static char *machine_get_dt_compatible(Object *obj, Error **errp) 408 { 409 MachineState *ms = MACHINE(obj); 410 411 return g_strdup(ms->dt_compatible); 412 } 413 414 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 415 { 416 MachineState *ms = MACHINE(obj); 417 418 g_free(ms->dt_compatible); 419 ms->dt_compatible = g_strdup(value); 420 } 421 422 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 423 { 424 MachineState *ms = MACHINE(obj); 425 426 return ms->dump_guest_core; 427 } 428 429 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 430 { 431 MachineState *ms = MACHINE(obj); 432 433 if (!value && QEMU_MADV_DONTDUMP == QEMU_MADV_INVALID) { 434 error_setg(errp, "Dumping guest memory cannot be disabled on this host"); 435 return; 436 } 437 ms->dump_guest_core = value; 438 } 439 440 static bool machine_get_mem_merge(Object *obj, Error **errp) 441 { 442 MachineState *ms = MACHINE(obj); 443 444 return ms->mem_merge; 445 } 446 447 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 448 { 449 MachineState *ms = MACHINE(obj); 450 451 if (value && QEMU_MADV_MERGEABLE == QEMU_MADV_INVALID) { 452 error_setg(errp, "Memory merging is not supported on this host"); 453 return; 454 } 455 ms->mem_merge = value; 456 } 457 458 static bool machine_get_usb(Object *obj, Error **errp) 459 { 460 MachineState *ms = MACHINE(obj); 461 462 return ms->usb; 463 } 464 465 static void machine_set_usb(Object *obj, bool value, Error **errp) 466 { 467 MachineState *ms = MACHINE(obj); 468 469 ms->usb = value; 470 ms->usb_disabled = !value; 471 } 472 473 static bool machine_get_graphics(Object *obj, Error **errp) 474 { 475 MachineState *ms = MACHINE(obj); 476 477 return ms->enable_graphics; 478 } 479 480 static void machine_set_graphics(Object *obj, bool value, Error **errp) 481 { 482 MachineState *ms = MACHINE(obj); 483 484 ms->enable_graphics = value; 485 } 486 487 static char *machine_get_firmware(Object *obj, Error **errp) 488 { 489 MachineState *ms = MACHINE(obj); 490 491 return g_strdup(ms->firmware); 492 } 493 494 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 495 { 496 MachineState *ms = MACHINE(obj); 497 498 g_free(ms->firmware); 499 ms->firmware = g_strdup(value); 500 } 501 502 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 503 { 504 MachineState *ms = MACHINE(obj); 505 506 ms->suppress_vmdesc = value; 507 } 508 509 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 510 { 511 MachineState *ms = MACHINE(obj); 512 513 return ms->suppress_vmdesc; 514 } 515 516 static char *machine_get_memory_encryption(Object *obj, Error **errp) 517 { 518 MachineState *ms = MACHINE(obj); 519 520 if (ms->cgs) { 521 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 522 } 523 524 return NULL; 525 } 526 527 static void machine_set_memory_encryption(Object *obj, const char *value, 528 Error **errp) 529 { 530 Object *cgs = 531 object_resolve_path_component(object_get_objects_root(), value); 532 533 if (!cgs) { 534 error_setg(errp, "No such memory encryption object '%s'", value); 535 return; 536 } 537 538 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 539 } 540 541 static void machine_check_confidential_guest_support(const Object *obj, 542 const char *name, 543 Object *new_target, 544 Error **errp) 545 { 546 /* 547 * So far the only constraint is that the target has the 548 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 549 * by the QOM core 550 */ 551 } 552 553 static bool machine_get_nvdimm(Object *obj, Error **errp) 554 { 555 MachineState *ms = MACHINE(obj); 556 557 return ms->nvdimms_state->is_enabled; 558 } 559 560 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 561 { 562 MachineState *ms = MACHINE(obj); 563 564 ms->nvdimms_state->is_enabled = value; 565 } 566 567 static bool machine_get_hmat(Object *obj, Error **errp) 568 { 569 MachineState *ms = MACHINE(obj); 570 571 return ms->numa_state->hmat_enabled; 572 } 573 574 static void machine_set_hmat(Object *obj, bool value, Error **errp) 575 { 576 MachineState *ms = MACHINE(obj); 577 578 ms->numa_state->hmat_enabled = value; 579 } 580 581 static void machine_get_mem(Object *obj, Visitor *v, const char *name, 582 void *opaque, Error **errp) 583 { 584 MachineState *ms = MACHINE(obj); 585 MemorySizeConfiguration mem = { 586 .has_size = true, 587 .size = ms->ram_size, 588 .has_max_size = !!ms->ram_slots, 589 .max_size = ms->maxram_size, 590 .has_slots = !!ms->ram_slots, 591 .slots = ms->ram_slots, 592 }; 593 MemorySizeConfiguration *p_mem = &mem; 594 595 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); 596 } 597 598 static void machine_set_mem(Object *obj, Visitor *v, const char *name, 599 void *opaque, Error **errp) 600 { 601 ERRP_GUARD(); 602 MachineState *ms = MACHINE(obj); 603 MachineClass *mc = MACHINE_GET_CLASS(obj); 604 MemorySizeConfiguration *mem; 605 606 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { 607 return; 608 } 609 610 if (!mem->has_size) { 611 mem->has_size = true; 612 mem->size = mc->default_ram_size; 613 } 614 mem->size = QEMU_ALIGN_UP(mem->size, 8192); 615 if (mc->fixup_ram_size) { 616 mem->size = mc->fixup_ram_size(mem->size); 617 } 618 if ((ram_addr_t)mem->size != mem->size) { 619 error_setg(errp, "ram size %llu exceeds permitted maximum %llu", 620 (unsigned long long)mem->size, 621 (unsigned long long)RAM_ADDR_MAX); 622 goto out_free; 623 } 624 625 if (mem->has_max_size) { 626 if ((ram_addr_t)mem->max_size != mem->max_size) { 627 error_setg(errp, "ram size %llu exceeds permitted maximum %llu", 628 (unsigned long long)mem->max_size, 629 (unsigned long long)RAM_ADDR_MAX); 630 goto out_free; 631 } 632 if (mem->max_size < mem->size) { 633 error_setg(errp, "invalid value of maxmem: " 634 "maximum memory size (0x%" PRIx64 ") must be at least " 635 "the initial memory size (0x%" PRIx64 ")", 636 mem->max_size, mem->size); 637 goto out_free; 638 } 639 if (mem->has_slots && mem->slots && mem->max_size == mem->size) { 640 error_setg(errp, "invalid value of maxmem: " 641 "memory slots were specified but maximum memory size " 642 "(0x%" PRIx64 ") is equal to the initial memory size " 643 "(0x%" PRIx64 ")", mem->max_size, mem->size); 644 goto out_free; 645 } 646 ms->maxram_size = mem->max_size; 647 } else { 648 if (mem->has_slots) { 649 error_setg(errp, "slots specified but no max-size"); 650 goto out_free; 651 } 652 ms->maxram_size = mem->size; 653 } 654 ms->ram_size = mem->size; 655 ms->ram_slots = mem->has_slots ? mem->slots : 0; 656 out_free: 657 qapi_free_MemorySizeConfiguration(mem); 658 } 659 660 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 661 { 662 MachineState *ms = MACHINE(obj); 663 664 return g_strdup(ms->nvdimms_state->persistence_string); 665 } 666 667 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 668 Error **errp) 669 { 670 MachineState *ms = MACHINE(obj); 671 NVDIMMState *nvdimms_state = ms->nvdimms_state; 672 673 if (strcmp(value, "cpu") == 0) { 674 nvdimms_state->persistence = 3; 675 } else if (strcmp(value, "mem-ctrl") == 0) { 676 nvdimms_state->persistence = 2; 677 } else { 678 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 679 value); 680 return; 681 } 682 683 g_free(nvdimms_state->persistence_string); 684 nvdimms_state->persistence_string = g_strdup(value); 685 } 686 687 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 688 { 689 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 690 } 691 692 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 693 { 694 Object *obj = OBJECT(dev); 695 696 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 697 return false; 698 } 699 700 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); 701 } 702 703 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) 704 { 705 bool allowed = false; 706 strList *wl; 707 ObjectClass *klass = object_class_by_name(type); 708 709 for (wl = mc->allowed_dynamic_sysbus_devices; 710 !allowed && wl; 711 wl = wl->next) { 712 allowed |= !!object_class_dynamic_cast(klass, wl->value); 713 } 714 715 return allowed; 716 } 717 718 static char *machine_get_audiodev(Object *obj, Error **errp) 719 { 720 MachineState *ms = MACHINE(obj); 721 722 return g_strdup(ms->audiodev); 723 } 724 725 static void machine_set_audiodev(Object *obj, const char *value, 726 Error **errp) 727 { 728 MachineState *ms = MACHINE(obj); 729 730 if (!audio_state_by_name(value, errp)) { 731 return; 732 } 733 734 g_free(ms->audiodev); 735 ms->audiodev = g_strdup(value); 736 } 737 738 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 739 { 740 int i; 741 HotpluggableCPUList *head = NULL; 742 MachineClass *mc = MACHINE_GET_CLASS(machine); 743 744 /* force board to initialize possible_cpus if it hasn't been done yet */ 745 mc->possible_cpu_arch_ids(machine); 746 747 for (i = 0; i < machine->possible_cpus->len; i++) { 748 CPUState *cpu; 749 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 750 751 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 752 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 753 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 754 sizeof(*cpu_item->props)); 755 756 cpu = machine->possible_cpus->cpus[i].cpu; 757 if (cpu) { 758 cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); 759 } 760 QAPI_LIST_PREPEND(head, cpu_item); 761 } 762 return head; 763 } 764 765 /** 766 * machine_set_cpu_numa_node: 767 * @machine: machine object to modify 768 * @props: specifies which cpu objects to assign to 769 * numa node specified by @props.node_id 770 * @errp: if an error occurs, a pointer to an area to store the error 771 * 772 * Associate NUMA node specified by @props.node_id with cpu slots that 773 * match socket/core/thread-ids specified by @props. It's recommended to use 774 * query-hotpluggable-cpus.props values to specify affected cpu slots, 775 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 776 * 777 * However for CLI convenience it's possible to pass in subset of properties, 778 * which would affect all cpu slots that match it. 779 * Ex for pc machine: 780 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 781 * -numa cpu,node-id=0,socket_id=0 \ 782 * -numa cpu,node-id=1,socket_id=1 783 * will assign all child cores of socket 0 to node 0 and 784 * of socket 1 to node 1. 785 * 786 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 787 * return error. 788 * Empty subset is disallowed and function will return with error in this case. 789 */ 790 void machine_set_cpu_numa_node(MachineState *machine, 791 const CpuInstanceProperties *props, Error **errp) 792 { 793 MachineClass *mc = MACHINE_GET_CLASS(machine); 794 NodeInfo *numa_info = machine->numa_state->nodes; 795 bool match = false; 796 int i; 797 798 if (!mc->possible_cpu_arch_ids) { 799 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 800 return; 801 } 802 803 /* disabling node mapping is not supported, forbid it */ 804 assert(props->has_node_id); 805 806 /* force board to initialize possible_cpus if it hasn't been done yet */ 807 mc->possible_cpu_arch_ids(machine); 808 809 for (i = 0; i < machine->possible_cpus->len; i++) { 810 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 811 812 /* reject unsupported by board properties */ 813 if (props->has_thread_id && !slot->props.has_thread_id) { 814 error_setg(errp, "thread-id is not supported"); 815 return; 816 } 817 818 if (props->has_core_id && !slot->props.has_core_id) { 819 error_setg(errp, "core-id is not supported"); 820 return; 821 } 822 823 if (props->has_module_id && !slot->props.has_module_id) { 824 error_setg(errp, "module-id is not supported"); 825 return; 826 } 827 828 if (props->has_cluster_id && !slot->props.has_cluster_id) { 829 error_setg(errp, "cluster-id is not supported"); 830 return; 831 } 832 833 if (props->has_socket_id && !slot->props.has_socket_id) { 834 error_setg(errp, "socket-id is not supported"); 835 return; 836 } 837 838 if (props->has_die_id && !slot->props.has_die_id) { 839 error_setg(errp, "die-id is not supported"); 840 return; 841 } 842 843 /* skip slots with explicit mismatch */ 844 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 845 continue; 846 } 847 848 if (props->has_core_id && props->core_id != slot->props.core_id) { 849 continue; 850 } 851 852 if (props->has_module_id && 853 props->module_id != slot->props.module_id) { 854 continue; 855 } 856 857 if (props->has_cluster_id && 858 props->cluster_id != slot->props.cluster_id) { 859 continue; 860 } 861 862 if (props->has_die_id && props->die_id != slot->props.die_id) { 863 continue; 864 } 865 866 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 867 continue; 868 } 869 870 /* reject assignment if slot is already assigned, for compatibility 871 * of legacy cpu_index mapping with SPAPR core based mapping do not 872 * error out if cpu thread and matched core have the same node-id */ 873 if (slot->props.has_node_id && 874 slot->props.node_id != props->node_id) { 875 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 876 slot->props.node_id); 877 return; 878 } 879 880 /* assign slot to node as it's matched '-numa cpu' key */ 881 match = true; 882 slot->props.node_id = props->node_id; 883 slot->props.has_node_id = props->has_node_id; 884 885 if (machine->numa_state->hmat_enabled) { 886 if ((numa_info[props->node_id].initiator < MAX_NODES) && 887 (props->node_id != numa_info[props->node_id].initiator)) { 888 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 889 " should be itself (got %" PRIu16 ")", 890 props->node_id, numa_info[props->node_id].initiator); 891 return; 892 } 893 numa_info[props->node_id].has_cpu = true; 894 numa_info[props->node_id].initiator = props->node_id; 895 } 896 } 897 898 if (!match) { 899 error_setg(errp, "no match found"); 900 } 901 } 902 903 static void machine_get_smp(Object *obj, Visitor *v, const char *name, 904 void *opaque, Error **errp) 905 { 906 MachineState *ms = MACHINE(obj); 907 SMPConfiguration *config = &(SMPConfiguration){ 908 .has_cpus = true, .cpus = ms->smp.cpus, 909 .has_drawers = true, .drawers = ms->smp.drawers, 910 .has_books = true, .books = ms->smp.books, 911 .has_sockets = true, .sockets = ms->smp.sockets, 912 .has_dies = true, .dies = ms->smp.dies, 913 .has_clusters = true, .clusters = ms->smp.clusters, 914 .has_modules = true, .modules = ms->smp.modules, 915 .has_cores = true, .cores = ms->smp.cores, 916 .has_threads = true, .threads = ms->smp.threads, 917 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, 918 }; 919 920 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { 921 return; 922 } 923 } 924 925 static void machine_set_smp(Object *obj, Visitor *v, const char *name, 926 void *opaque, Error **errp) 927 { 928 MachineState *ms = MACHINE(obj); 929 g_autoptr(SMPConfiguration) config = NULL; 930 931 if (!visit_type_SMPConfiguration(v, name, &config, errp)) { 932 return; 933 } 934 935 machine_parse_smp_config(ms, config, errp); 936 } 937 938 static void machine_get_smp_cache(Object *obj, Visitor *v, const char *name, 939 void *opaque, Error **errp) 940 { 941 MachineState *ms = MACHINE(obj); 942 SmpCache *cache = &ms->smp_cache; 943 SmpCachePropertiesList *head = NULL; 944 SmpCachePropertiesList **tail = &head; 945 946 for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { 947 SmpCacheProperties *node = g_new(SmpCacheProperties, 1); 948 949 node->cache = cache->props[i].cache; 950 node->topology = cache->props[i].topology; 951 QAPI_LIST_APPEND(tail, node); 952 } 953 954 visit_type_SmpCachePropertiesList(v, name, &head, errp); 955 qapi_free_SmpCachePropertiesList(head); 956 } 957 958 static void machine_set_smp_cache(Object *obj, Visitor *v, const char *name, 959 void *opaque, Error **errp) 960 { 961 MachineState *ms = MACHINE(obj); 962 SmpCachePropertiesList *caches; 963 964 if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) { 965 return; 966 } 967 968 machine_parse_smp_cache(ms, caches, errp); 969 qapi_free_SmpCachePropertiesList(caches); 970 } 971 972 static void machine_get_boot(Object *obj, Visitor *v, const char *name, 973 void *opaque, Error **errp) 974 { 975 MachineState *ms = MACHINE(obj); 976 BootConfiguration *config = &ms->boot_config; 977 visit_type_BootConfiguration(v, name, &config, &error_abort); 978 } 979 980 static void machine_free_boot_config(MachineState *ms) 981 { 982 g_free(ms->boot_config.order); 983 g_free(ms->boot_config.once); 984 g_free(ms->boot_config.splash); 985 } 986 987 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) 988 { 989 MachineClass *machine_class = MACHINE_GET_CLASS(ms); 990 991 machine_free_boot_config(ms); 992 ms->boot_config = *config; 993 if (!config->order) { 994 ms->boot_config.order = g_strdup(machine_class->default_boot_order); 995 } 996 } 997 998 static void machine_set_boot(Object *obj, Visitor *v, const char *name, 999 void *opaque, Error **errp) 1000 { 1001 ERRP_GUARD(); 1002 MachineState *ms = MACHINE(obj); 1003 BootConfiguration *config = NULL; 1004 1005 if (!visit_type_BootConfiguration(v, name, &config, errp)) { 1006 return; 1007 } 1008 if (config->order) { 1009 validate_bootdevices(config->order, errp); 1010 if (*errp) { 1011 goto out_free; 1012 } 1013 } 1014 if (config->once) { 1015 validate_bootdevices(config->once, errp); 1016 if (*errp) { 1017 goto out_free; 1018 } 1019 } 1020 1021 machine_copy_boot_config(ms, config); 1022 /* Strings live in ms->boot_config. */ 1023 free(config); 1024 return; 1025 1026 out_free: 1027 qapi_free_BootConfiguration(config); 1028 } 1029 1030 void machine_add_audiodev_property(MachineClass *mc) 1031 { 1032 ObjectClass *oc = OBJECT_CLASS(mc); 1033 1034 object_class_property_add_str(oc, "audiodev", 1035 machine_get_audiodev, 1036 machine_set_audiodev); 1037 object_class_property_set_description(oc, "audiodev", 1038 "Audiodev to use for default machine devices"); 1039 } 1040 1041 static bool create_default_memdev(MachineState *ms, const char *path, 1042 Error **errp) 1043 { 1044 Object *obj; 1045 MachineClass *mc = MACHINE_GET_CLASS(ms); 1046 bool r = false; 1047 1048 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 1049 if (path) { 1050 if (!object_property_set_str(obj, "mem-path", path, errp)) { 1051 goto out; 1052 } 1053 } 1054 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { 1055 goto out; 1056 } 1057 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 1058 obj); 1059 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 1060 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 1061 false, errp)) { 1062 goto out; 1063 } 1064 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { 1065 goto out; 1066 } 1067 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); 1068 1069 out: 1070 object_unref(obj); 1071 return r; 1072 } 1073 1074 static void machine_class_init(ObjectClass *oc, void *data) 1075 { 1076 MachineClass *mc = MACHINE_CLASS(oc); 1077 1078 /* Default 128 MB as guest ram size */ 1079 mc->default_ram_size = 128 * MiB; 1080 mc->rom_file_has_mr = true; 1081 /* 1082 * SMBIOS 3.1.0 7.18.5 Memory Device — Extended Size 1083 * use max possible value that could be encoded into 1084 * 'Extended Size' field (2047Tb). 1085 */ 1086 mc->smbios_memory_device_size = 2047 * TiB; 1087 1088 /* numa node memory size aligned on 8MB by default. 1089 * On Linux, each node's border has to be 8MB aligned 1090 */ 1091 mc->numa_mem_align_shift = 23; 1092 1093 mc->create_default_memdev = create_default_memdev; 1094 1095 object_class_property_add_str(oc, "kernel", 1096 machine_get_kernel, machine_set_kernel); 1097 object_class_property_set_description(oc, "kernel", 1098 "Linux kernel image file"); 1099 1100 object_class_property_add_str(oc, "shim", 1101 machine_get_shim, machine_set_shim); 1102 object_class_property_set_description(oc, "shim", 1103 "shim.efi file"); 1104 1105 object_class_property_add_str(oc, "initrd", 1106 machine_get_initrd, machine_set_initrd); 1107 object_class_property_set_description(oc, "initrd", 1108 "Linux initial ramdisk file"); 1109 1110 object_class_property_add_str(oc, "append", 1111 machine_get_append, machine_set_append); 1112 object_class_property_set_description(oc, "append", 1113 "Linux kernel command line"); 1114 1115 object_class_property_add_str(oc, "dtb", 1116 machine_get_dtb, machine_set_dtb); 1117 object_class_property_set_description(oc, "dtb", 1118 "Linux kernel device tree file"); 1119 1120 object_class_property_add_str(oc, "dumpdtb", 1121 machine_get_dumpdtb, machine_set_dumpdtb); 1122 object_class_property_set_description(oc, "dumpdtb", 1123 "Dump current dtb to a file and quit"); 1124 1125 object_class_property_add(oc, "boot", "BootConfiguration", 1126 machine_get_boot, machine_set_boot, 1127 NULL, NULL); 1128 object_class_property_set_description(oc, "boot", 1129 "Boot configuration"); 1130 1131 object_class_property_add(oc, "smp", "SMPConfiguration", 1132 machine_get_smp, machine_set_smp, 1133 NULL, NULL); 1134 object_class_property_set_description(oc, "smp", 1135 "CPU topology"); 1136 1137 object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper", 1138 machine_get_smp_cache, machine_set_smp_cache, NULL, NULL); 1139 object_class_property_set_description(oc, "smp-cache", 1140 "Cache properties list for SMP machine"); 1141 1142 object_class_property_add(oc, "phandle-start", "int", 1143 machine_get_phandle_start, machine_set_phandle_start, 1144 NULL, NULL); 1145 object_class_property_set_description(oc, "phandle-start", 1146 "The first phandle ID we may generate dynamically"); 1147 1148 object_class_property_add_str(oc, "dt-compatible", 1149 machine_get_dt_compatible, machine_set_dt_compatible); 1150 object_class_property_set_description(oc, "dt-compatible", 1151 "Overrides the \"compatible\" property of the dt root node"); 1152 1153 object_class_property_add_bool(oc, "dump-guest-core", 1154 machine_get_dump_guest_core, machine_set_dump_guest_core); 1155 object_class_property_set_description(oc, "dump-guest-core", 1156 "Include guest memory in a core dump"); 1157 1158 object_class_property_add_bool(oc, "mem-merge", 1159 machine_get_mem_merge, machine_set_mem_merge); 1160 object_class_property_set_description(oc, "mem-merge", 1161 "Enable/disable memory merge support"); 1162 1163 object_class_property_add_bool(oc, "usb", 1164 machine_get_usb, machine_set_usb); 1165 object_class_property_set_description(oc, "usb", 1166 "Set on/off to enable/disable usb"); 1167 1168 object_class_property_add_bool(oc, "graphics", 1169 machine_get_graphics, machine_set_graphics); 1170 object_class_property_set_description(oc, "graphics", 1171 "Set on/off to enable/disable graphics emulation"); 1172 1173 object_class_property_add_str(oc, "firmware", 1174 machine_get_firmware, machine_set_firmware); 1175 object_class_property_set_description(oc, "firmware", 1176 "Firmware image"); 1177 1178 object_class_property_add_bool(oc, "suppress-vmdesc", 1179 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 1180 object_class_property_set_description(oc, "suppress-vmdesc", 1181 "Set on to disable self-describing migration"); 1182 1183 object_class_property_add_link(oc, "confidential-guest-support", 1184 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 1185 offsetof(MachineState, cgs), 1186 machine_check_confidential_guest_support, 1187 OBJ_PROP_LINK_STRONG); 1188 object_class_property_set_description(oc, "confidential-guest-support", 1189 "Set confidential guest scheme to support"); 1190 1191 /* For compatibility */ 1192 object_class_property_add_str(oc, "memory-encryption", 1193 machine_get_memory_encryption, machine_set_memory_encryption); 1194 object_class_property_set_description(oc, "memory-encryption", 1195 "Set memory encryption object to use"); 1196 1197 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, 1198 offsetof(MachineState, memdev), object_property_allow_set_link, 1199 OBJ_PROP_LINK_STRONG); 1200 object_class_property_set_description(oc, "memory-backend", 1201 "Set RAM backend" 1202 "Valid value is ID of hostmem based backend"); 1203 1204 object_class_property_add(oc, "memory", "MemorySizeConfiguration", 1205 machine_get_mem, machine_set_mem, 1206 NULL, NULL); 1207 object_class_property_set_description(oc, "memory", 1208 "Memory size configuration"); 1209 } 1210 1211 static void machine_class_base_init(ObjectClass *oc, void *data) 1212 { 1213 MachineClass *mc = MACHINE_CLASS(oc); 1214 mc->max_cpus = mc->max_cpus ?: 1; 1215 mc->min_cpus = mc->min_cpus ?: 1; 1216 mc->default_cpus = mc->default_cpus ?: 1; 1217 1218 if (!object_class_is_abstract(oc)) { 1219 const char *cname = object_class_get_name(oc); 1220 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 1221 mc->name = g_strndup(cname, 1222 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 1223 mc->compat_props = g_ptr_array_new(); 1224 } 1225 } 1226 1227 static void machine_initfn(Object *obj) 1228 { 1229 MachineState *ms = MACHINE(obj); 1230 MachineClass *mc = MACHINE_GET_CLASS(obj); 1231 1232 container_get(obj, "/peripheral"); 1233 container_get(obj, "/peripheral-anon"); 1234 1235 ms->dump_guest_core = true; 1236 ms->mem_merge = (QEMU_MADV_MERGEABLE != QEMU_MADV_INVALID); 1237 ms->enable_graphics = true; 1238 ms->kernel_cmdline = g_strdup(""); 1239 ms->ram_size = mc->default_ram_size; 1240 ms->maxram_size = mc->default_ram_size; 1241 1242 if (mc->nvdimm_supported) { 1243 ms->nvdimms_state = g_new0(NVDIMMState, 1); 1244 object_property_add_bool(obj, "nvdimm", 1245 machine_get_nvdimm, machine_set_nvdimm); 1246 object_property_set_description(obj, "nvdimm", 1247 "Set on/off to enable/disable " 1248 "NVDIMM instantiation"); 1249 1250 object_property_add_str(obj, "nvdimm-persistence", 1251 machine_get_nvdimm_persistence, 1252 machine_set_nvdimm_persistence); 1253 object_property_set_description(obj, "nvdimm-persistence", 1254 "Set NVDIMM persistence" 1255 "Valid values are cpu, mem-ctrl"); 1256 } 1257 1258 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 1259 ms->numa_state = g_new0(NumaState, 1); 1260 object_property_add_bool(obj, "hmat", 1261 machine_get_hmat, machine_set_hmat); 1262 object_property_set_description(obj, "hmat", 1263 "Set on/off to enable/disable " 1264 "ACPI Heterogeneous Memory Attribute " 1265 "Table (HMAT)"); 1266 } 1267 1268 /* default to mc->default_cpus */ 1269 ms->smp.cpus = mc->default_cpus; 1270 ms->smp.max_cpus = mc->default_cpus; 1271 ms->smp.drawers = 1; 1272 ms->smp.books = 1; 1273 ms->smp.sockets = 1; 1274 ms->smp.dies = 1; 1275 ms->smp.clusters = 1; 1276 ms->smp.modules = 1; 1277 ms->smp.cores = 1; 1278 ms->smp.threads = 1; 1279 1280 for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { 1281 ms->smp_cache.props[i].cache = (CacheLevelAndType)i; 1282 ms->smp_cache.props[i].topology = CPU_TOPOLOGY_LEVEL_DEFAULT; 1283 } 1284 1285 machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); 1286 } 1287 1288 static void machine_finalize(Object *obj) 1289 { 1290 MachineState *ms = MACHINE(obj); 1291 1292 machine_free_boot_config(ms); 1293 g_free(ms->kernel_filename); 1294 g_free(ms->initrd_filename); 1295 g_free(ms->kernel_cmdline); 1296 g_free(ms->dtb); 1297 g_free(ms->dumpdtb); 1298 g_free(ms->dt_compatible); 1299 g_free(ms->firmware); 1300 g_free(ms->device_memory); 1301 g_free(ms->nvdimms_state); 1302 g_free(ms->numa_state); 1303 g_free(ms->audiodev); 1304 } 1305 1306 bool machine_usb(MachineState *machine) 1307 { 1308 return machine->usb; 1309 } 1310 1311 int machine_phandle_start(MachineState *machine) 1312 { 1313 return machine->phandle_start; 1314 } 1315 1316 bool machine_dump_guest_core(MachineState *machine) 1317 { 1318 return machine->dump_guest_core; 1319 } 1320 1321 bool machine_mem_merge(MachineState *machine) 1322 { 1323 return machine->mem_merge; 1324 } 1325 1326 bool machine_require_guest_memfd(MachineState *machine) 1327 { 1328 return machine->cgs && machine->cgs->require_guest_memfd; 1329 } 1330 1331 static char *cpu_slot_to_string(const CPUArchId *cpu) 1332 { 1333 GString *s = g_string_new(NULL); 1334 if (cpu->props.has_socket_id) { 1335 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1336 } 1337 if (cpu->props.has_die_id) { 1338 if (s->len) { 1339 g_string_append_printf(s, ", "); 1340 } 1341 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1342 } 1343 if (cpu->props.has_cluster_id) { 1344 if (s->len) { 1345 g_string_append_printf(s, ", "); 1346 } 1347 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); 1348 } 1349 if (cpu->props.has_module_id) { 1350 if (s->len) { 1351 g_string_append_printf(s, ", "); 1352 } 1353 g_string_append_printf(s, "module-id: %"PRId64, cpu->props.module_id); 1354 } 1355 if (cpu->props.has_core_id) { 1356 if (s->len) { 1357 g_string_append_printf(s, ", "); 1358 } 1359 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1360 } 1361 if (cpu->props.has_thread_id) { 1362 if (s->len) { 1363 g_string_append_printf(s, ", "); 1364 } 1365 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1366 } 1367 return g_string_free(s, false); 1368 } 1369 1370 static void numa_validate_initiator(NumaState *numa_state) 1371 { 1372 int i; 1373 NodeInfo *numa_info = numa_state->nodes; 1374 1375 for (i = 0; i < numa_state->num_nodes; i++) { 1376 if (numa_info[i].initiator == MAX_NODES) { 1377 continue; 1378 } 1379 1380 if (!numa_info[numa_info[i].initiator].present) { 1381 error_report("NUMA node %" PRIu16 " is missing, use " 1382 "'-numa node' option to declare it first", 1383 numa_info[i].initiator); 1384 exit(1); 1385 } 1386 1387 if (!numa_info[numa_info[i].initiator].has_cpu) { 1388 error_report("The initiator of NUMA node %d is invalid", i); 1389 exit(1); 1390 } 1391 } 1392 } 1393 1394 static void machine_numa_finish_cpu_init(MachineState *machine) 1395 { 1396 int i; 1397 bool default_mapping; 1398 GString *s = g_string_new(NULL); 1399 MachineClass *mc = MACHINE_GET_CLASS(machine); 1400 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1401 1402 assert(machine->numa_state->num_nodes); 1403 for (i = 0; i < possible_cpus->len; i++) { 1404 if (possible_cpus->cpus[i].props.has_node_id) { 1405 break; 1406 } 1407 } 1408 default_mapping = (i == possible_cpus->len); 1409 1410 for (i = 0; i < possible_cpus->len; i++) { 1411 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1412 1413 if (!cpu_slot->props.has_node_id) { 1414 /* fetch default mapping from board and enable it */ 1415 CpuInstanceProperties props = cpu_slot->props; 1416 1417 props.node_id = mc->get_default_cpu_node_id(machine, i); 1418 if (!default_mapping) { 1419 /* record slots with not set mapping, 1420 * TODO: make it hard error in future */ 1421 char *cpu_str = cpu_slot_to_string(cpu_slot); 1422 g_string_append_printf(s, "%sCPU %d [%s]", 1423 s->len ? ", " : "", i, cpu_str); 1424 g_free(cpu_str); 1425 1426 /* non mapped cpus used to fallback to node 0 */ 1427 props.node_id = 0; 1428 } 1429 1430 props.has_node_id = true; 1431 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1432 } 1433 } 1434 1435 if (machine->numa_state->hmat_enabled) { 1436 numa_validate_initiator(machine->numa_state); 1437 } 1438 1439 if (s->len && !qtest_enabled()) { 1440 warn_report("CPU(s) not present in any NUMA nodes: %s", 1441 s->str); 1442 warn_report("All CPU(s) up to maxcpus should be described " 1443 "in NUMA config, ability to start up with partial NUMA " 1444 "mappings is obsoleted and will be removed in future"); 1445 } 1446 g_string_free(s, true); 1447 } 1448 1449 static void validate_cpu_cluster_to_numa_boundary(MachineState *ms) 1450 { 1451 MachineClass *mc = MACHINE_GET_CLASS(ms); 1452 NumaState *state = ms->numa_state; 1453 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1454 const CPUArchId *cpus = possible_cpus->cpus; 1455 int i, j; 1456 1457 if (qtest_enabled() || state->num_nodes <= 1 || possible_cpus->len <= 1) { 1458 return; 1459 } 1460 1461 /* 1462 * The Linux scheduling domain can't be parsed when the multiple CPUs 1463 * in one cluster have been associated with different NUMA nodes. However, 1464 * it's fine to associate one NUMA node with CPUs in different clusters. 1465 */ 1466 for (i = 0; i < possible_cpus->len; i++) { 1467 for (j = i + 1; j < possible_cpus->len; j++) { 1468 if (cpus[i].props.has_socket_id && 1469 cpus[i].props.has_cluster_id && 1470 cpus[i].props.has_node_id && 1471 cpus[j].props.has_socket_id && 1472 cpus[j].props.has_cluster_id && 1473 cpus[j].props.has_node_id && 1474 cpus[i].props.socket_id == cpus[j].props.socket_id && 1475 cpus[i].props.cluster_id == cpus[j].props.cluster_id && 1476 cpus[i].props.node_id != cpus[j].props.node_id) { 1477 warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64 1478 " have been associated with node-%" PRId64 " and node-%" PRId64 1479 " respectively. It can cause OSes like Linux to" 1480 " misbehave", i, j, cpus[i].props.socket_id, 1481 cpus[i].props.cluster_id, cpus[i].props.node_id, 1482 cpus[j].props.node_id); 1483 } 1484 } 1485 } 1486 } 1487 1488 MemoryRegion *machine_consume_memdev(MachineState *machine, 1489 HostMemoryBackend *backend) 1490 { 1491 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1492 1493 if (host_memory_backend_is_mapped(backend)) { 1494 error_report("memory backend %s can't be used multiple times.", 1495 object_get_canonical_path_component(OBJECT(backend))); 1496 exit(EXIT_FAILURE); 1497 } 1498 host_memory_backend_set_mapped(backend, true); 1499 vmstate_register_ram_global(ret); 1500 return ret; 1501 } 1502 1503 const char *machine_class_default_cpu_type(MachineClass *mc) 1504 { 1505 if (mc->valid_cpu_types && !mc->valid_cpu_types[1]) { 1506 /* Only a single CPU type allowed: use it as default. */ 1507 return mc->valid_cpu_types[0]; 1508 } 1509 return mc->default_cpu_type; 1510 } 1511 1512 static bool is_cpu_type_supported(const MachineState *machine, Error **errp) 1513 { 1514 MachineClass *mc = MACHINE_GET_CLASS(machine); 1515 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1516 CPUClass *cc; 1517 int i; 1518 1519 /* 1520 * Check if the user specified CPU type is supported when the valid 1521 * CPU types have been determined. Note that the user specified CPU 1522 * type is provided through '-cpu' option. 1523 */ 1524 if (mc->valid_cpu_types) { 1525 assert(mc->valid_cpu_types[0] != NULL); 1526 for (i = 0; mc->valid_cpu_types[i]; i++) { 1527 if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) { 1528 break; 1529 } 1530 } 1531 1532 /* The user specified CPU type isn't valid */ 1533 if (!mc->valid_cpu_types[i]) { 1534 g_autofree char *requested = cpu_model_from_type(machine->cpu_type); 1535 error_setg(errp, "Invalid CPU model: %s", requested); 1536 if (!mc->valid_cpu_types[1]) { 1537 g_autofree char *model = cpu_model_from_type( 1538 mc->valid_cpu_types[0]); 1539 error_append_hint(errp, "The only valid type is: %s\n", model); 1540 } else { 1541 error_append_hint(errp, "The valid models are: "); 1542 for (i = 0; mc->valid_cpu_types[i]; i++) { 1543 g_autofree char *model = cpu_model_from_type( 1544 mc->valid_cpu_types[i]); 1545 error_append_hint(errp, "%s%s", 1546 model, 1547 mc->valid_cpu_types[i + 1] ? ", " : ""); 1548 } 1549 error_append_hint(errp, "\n"); 1550 } 1551 1552 return false; 1553 } 1554 } 1555 1556 /* Check if CPU type is deprecated and warn if so */ 1557 cc = CPU_CLASS(oc); 1558 assert(cc != NULL); 1559 if (cc->deprecation_note) { 1560 warn_report("CPU model %s is deprecated -- %s", 1561 machine->cpu_type, cc->deprecation_note); 1562 } 1563 1564 return true; 1565 } 1566 1567 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) 1568 { 1569 ERRP_GUARD(); 1570 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1571 1572 /* This checkpoint is required by replay to separate prior clock 1573 reading from the other reads, because timer polling functions query 1574 clock values from the log. */ 1575 replay_checkpoint(CHECKPOINT_INIT); 1576 1577 if (!xen_enabled()) { 1578 /* On 32-bit hosts, QEMU is limited by virtual address space */ 1579 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 1580 error_setg(errp, "at most 2047 MB RAM can be simulated"); 1581 return; 1582 } 1583 } 1584 1585 if (machine->memdev) { 1586 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), 1587 "size", &error_abort); 1588 if (backend_size != machine->ram_size) { 1589 error_setg(errp, "Machine memory size does not match the size of the memory backend"); 1590 return; 1591 } 1592 } else if (machine_class->default_ram_id && machine->ram_size && 1593 numa_uses_legacy_mem()) { 1594 if (object_property_find(object_get_objects_root(), 1595 machine_class->default_ram_id)) { 1596 error_setg(errp, "object's id '%s' is reserved for the default" 1597 " RAM backend, it can't be used for any other purposes", 1598 machine_class->default_ram_id); 1599 error_append_hint(errp, 1600 "Change the object's 'id' to something else or disable" 1601 " automatic creation of the default RAM backend by setting" 1602 " 'memory-backend=%s' with '-machine'.\n", 1603 machine_class->default_ram_id); 1604 return; 1605 } 1606 1607 if (!machine_class->create_default_memdev(current_machine, mem_path, 1608 errp)) { 1609 return; 1610 } 1611 } 1612 1613 if (machine->numa_state) { 1614 numa_complete_configuration(machine); 1615 if (machine->numa_state->num_nodes) { 1616 machine_numa_finish_cpu_init(machine); 1617 if (machine_class->cpu_cluster_has_numa_boundary) { 1618 validate_cpu_cluster_to_numa_boundary(machine); 1619 } 1620 } 1621 } 1622 1623 if (!machine->ram && machine->memdev) { 1624 machine->ram = machine_consume_memdev(machine, machine->memdev); 1625 } 1626 1627 /* Check if the CPU type is supported */ 1628 if (machine->cpu_type && !is_cpu_type_supported(machine, errp)) { 1629 return; 1630 } 1631 1632 if (machine->cgs) { 1633 /* 1634 * With confidential guests, the host can't see the real 1635 * contents of RAM, so there's no point in it trying to merge 1636 * areas. 1637 */ 1638 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1639 1640 /* 1641 * Virtio devices can't count on directly accessing guest 1642 * memory, so they need iommu_platform=on to use normal DMA 1643 * mechanisms. That requires also disabling legacy virtio 1644 * support for those virtio pci devices which allow it. 1645 */ 1646 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1647 "on", true); 1648 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1649 "on", false); 1650 } 1651 1652 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1653 machine_class->init(machine); 1654 phase_advance(PHASE_MACHINE_INITIALIZED); 1655 } 1656 1657 static NotifierList machine_init_done_notifiers = 1658 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1659 1660 void qemu_add_machine_init_done_notifier(Notifier *notify) 1661 { 1662 notifier_list_add(&machine_init_done_notifiers, notify); 1663 if (phase_check(PHASE_MACHINE_READY)) { 1664 notify->notify(notify, NULL); 1665 } 1666 } 1667 1668 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1669 { 1670 notifier_remove(notify); 1671 } 1672 1673 void qdev_machine_creation_done(void) 1674 { 1675 cpu_synchronize_all_post_init(); 1676 1677 if (current_machine->boot_config.once) { 1678 qemu_boot_set(current_machine->boot_config.once, &error_fatal); 1679 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); 1680 } 1681 1682 /* 1683 * ok, initial machine setup is done, starting from now we can 1684 * only create hotpluggable devices 1685 */ 1686 phase_advance(PHASE_MACHINE_READY); 1687 qdev_assert_realized_properly(); 1688 1689 /* TODO: once all bus devices are qdevified, this should be done 1690 * when bus is created by qdev.c */ 1691 /* 1692 * This is where we arrange for the sysbus to be reset when the 1693 * whole simulation is reset. In turn, resetting the sysbus will cause 1694 * all devices hanging off it (and all their child buses, recursively) 1695 * to be reset. Note that this will *not* reset any Device objects 1696 * which are not attached to some part of the qbus tree! 1697 */ 1698 qemu_register_resettable(OBJECT(sysbus_get_default())); 1699 1700 notifier_list_notify(&machine_init_done_notifiers, NULL); 1701 1702 if (rom_check_and_register_reset() != 0) { 1703 exit(1); 1704 } 1705 1706 replay_start(); 1707 1708 /* This checkpoint is required by replay to separate prior clock 1709 reading from the other reads, because timer polling functions query 1710 clock values from the log. */ 1711 replay_checkpoint(CHECKPOINT_RESET); 1712 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1713 register_global_state(); 1714 } 1715 1716 static const TypeInfo machine_info = { 1717 .name = TYPE_MACHINE, 1718 .parent = TYPE_OBJECT, 1719 .abstract = true, 1720 .class_size = sizeof(MachineClass), 1721 .class_init = machine_class_init, 1722 .class_base_init = machine_class_base_init, 1723 .instance_size = sizeof(MachineState), 1724 .instance_init = machine_initfn, 1725 .instance_finalize = machine_finalize, 1726 }; 1727 1728 static void machine_register_types(void) 1729 { 1730 type_register_static(&machine_info); 1731 } 1732 1733 type_init(machine_register_types) 1734