1 /* 2 * STM32F2XX USART 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/char/stm32f2xx_usart.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/qdev-properties-system.h" 30 #include "qemu/log.h" 31 #include "qemu/module.h" 32 33 #include "trace.h" 34 35 static int stm32f2xx_usart_can_receive(void *opaque) 36 { 37 STM32F2XXUsartState *s = opaque; 38 39 if (!(s->usart_sr & USART_SR_RXNE)) { 40 return 1; 41 } 42 43 return 0; 44 } 45 46 static void stm32f2xx_update_irq(STM32F2XXUsartState *s) 47 { 48 uint32_t mask = s->usart_sr & s->usart_cr1; 49 50 if (mask & (USART_SR_TXE | USART_SR_TC | USART_SR_RXNE)) { 51 qemu_set_irq(s->irq, 1); 52 } else { 53 qemu_set_irq(s->irq, 0); 54 } 55 } 56 57 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size) 58 { 59 STM32F2XXUsartState *s = opaque; 60 DeviceState *d = DEVICE(s); 61 62 if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) { 63 /* USART not enabled - drop the chars */ 64 trace_stm32f2xx_usart_drop(d->id); 65 return; 66 } 67 68 s->usart_dr = *buf; 69 s->usart_sr |= USART_SR_RXNE; 70 71 stm32f2xx_update_irq(s); 72 73 trace_stm32f2xx_usart_receive(d->id, *buf); 74 } 75 76 static void stm32f2xx_usart_reset(DeviceState *dev) 77 { 78 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 79 80 s->usart_sr = USART_SR_RESET; 81 s->usart_dr = 0x00000000; 82 s->usart_brr = 0x00000000; 83 s->usart_cr1 = 0x00000000; 84 s->usart_cr2 = 0x00000000; 85 s->usart_cr3 = 0x00000000; 86 s->usart_gtpr = 0x00000000; 87 88 stm32f2xx_update_irq(s); 89 } 90 91 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, 92 unsigned int size) 93 { 94 STM32F2XXUsartState *s = opaque; 95 DeviceState *d = DEVICE(s); 96 uint64_t retvalue = 0; 97 98 switch (addr) { 99 case USART_SR: 100 retvalue = s->usart_sr; 101 qemu_chr_fe_accept_input(&s->chr); 102 break; 103 case USART_DR: 104 retvalue = s->usart_dr & 0x3FF; 105 s->usart_sr &= ~USART_SR_RXNE; 106 qemu_chr_fe_accept_input(&s->chr); 107 stm32f2xx_update_irq(s); 108 break; 109 case USART_BRR: 110 retvalue = s->usart_brr; 111 break; 112 case USART_CR1: 113 retvalue = s->usart_cr1; 114 break; 115 case USART_CR2: 116 retvalue = s->usart_cr2; 117 break; 118 case USART_CR3: 119 retvalue = s->usart_cr3; 120 break; 121 case USART_GTPR: 122 retvalue = s->usart_gtpr; 123 break; 124 default: 125 qemu_log_mask(LOG_GUEST_ERROR, 126 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 127 return 0; 128 } 129 130 trace_stm32f2xx_usart_read(d->id, size, addr, retvalue); 131 132 return retvalue; 133 } 134 135 static void stm32f2xx_usart_write(void *opaque, hwaddr addr, 136 uint64_t val64, unsigned int size) 137 { 138 STM32F2XXUsartState *s = opaque; 139 DeviceState *d = DEVICE(s); 140 uint32_t value = val64; 141 unsigned char ch; 142 143 trace_stm32f2xx_usart_write(d->id, size, addr, val64); 144 145 switch (addr) { 146 case USART_SR: 147 if (value <= 0x3FF) { 148 /* I/O being synchronous, TXE is always set. In addition, it may 149 only be set by hardware, so keep it set here. */ 150 s->usart_sr = value | USART_SR_TXE; 151 } else { 152 s->usart_sr &= value; 153 } 154 stm32f2xx_update_irq(s); 155 return; 156 case USART_DR: 157 if (value < 0xF000) { 158 ch = value; 159 /* XXX this blocks entire thread. Rewrite to use 160 * qemu_chr_fe_write and background I/O callbacks */ 161 qemu_chr_fe_write_all(&s->chr, &ch, 1); 162 /* XXX I/O are currently synchronous, making it impossible for 163 software to observe transient states where TXE or TC aren't 164 set. Unlike TXE however, which is read-only, software may 165 clear TC by writing 0 to the SR register, so set it again 166 on each write. */ 167 s->usart_sr |= USART_SR_TC; 168 stm32f2xx_update_irq(s); 169 } 170 return; 171 case USART_BRR: 172 s->usart_brr = value; 173 return; 174 case USART_CR1: 175 s->usart_cr1 = value; 176 stm32f2xx_update_irq(s); 177 return; 178 case USART_CR2: 179 s->usart_cr2 = value; 180 return; 181 case USART_CR3: 182 s->usart_cr3 = value; 183 return; 184 case USART_GTPR: 185 s->usart_gtpr = value; 186 return; 187 default: 188 qemu_log_mask(LOG_GUEST_ERROR, 189 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 190 } 191 } 192 193 static const MemoryRegionOps stm32f2xx_usart_ops = { 194 .read = stm32f2xx_usart_read, 195 .write = stm32f2xx_usart_write, 196 .endianness = DEVICE_NATIVE_ENDIAN, 197 }; 198 199 static const Property stm32f2xx_usart_properties[] = { 200 DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr), 201 }; 202 203 static void stm32f2xx_usart_init(Object *obj) 204 { 205 STM32F2XXUsartState *s = STM32F2XX_USART(obj); 206 207 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 208 209 memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s, 210 TYPE_STM32F2XX_USART, 0x400); 211 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 212 } 213 214 static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp) 215 { 216 STM32F2XXUsartState *s = STM32F2XX_USART(dev); 217 218 qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive, 219 stm32f2xx_usart_receive, NULL, NULL, 220 s, NULL, true); 221 } 222 223 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data) 224 { 225 DeviceClass *dc = DEVICE_CLASS(klass); 226 227 device_class_set_legacy_reset(dc, stm32f2xx_usart_reset); 228 device_class_set_props(dc, stm32f2xx_usart_properties); 229 dc->realize = stm32f2xx_usart_realize; 230 } 231 232 static const TypeInfo stm32f2xx_usart_info = { 233 .name = TYPE_STM32F2XX_USART, 234 .parent = TYPE_SYS_BUS_DEVICE, 235 .instance_size = sizeof(STM32F2XXUsartState), 236 .instance_init = stm32f2xx_usart_init, 237 .class_init = stm32f2xx_usart_class_init, 238 }; 239 240 static void stm32f2xx_usart_register_types(void) 241 { 242 type_register_static(&stm32f2xx_usart_info); 243 } 244 245 type_init(stm32f2xx_usart_register_types) 246