1 /* 2 * QEMU SCI/SCIF serial port emulation 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * 6 * Based on serial.c - QEMU 16450 UART emulation 7 * Copyright (c) 2003-2004 Fabrice Bellard 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/irq.h" 30 #include "hw/sh4/sh.h" 31 #include "chardev/char-fe.h" 32 #include "qapi/error.h" 33 #include "qemu/timer.h" 34 35 //#define DEBUG_SERIAL 36 37 #define SH_SERIAL_FLAG_TEND (1 << 0) 38 #define SH_SERIAL_FLAG_TDE (1 << 1) 39 #define SH_SERIAL_FLAG_RDF (1 << 2) 40 #define SH_SERIAL_FLAG_BRK (1 << 3) 41 #define SH_SERIAL_FLAG_DR (1 << 4) 42 43 #define SH_RX_FIFO_LENGTH (16) 44 45 typedef struct { 46 MemoryRegion iomem; 47 MemoryRegion iomem_p4; 48 MemoryRegion iomem_a7; 49 uint8_t smr; 50 uint8_t brr; 51 uint8_t scr; 52 uint8_t dr; /* ftdr / tdr */ 53 uint8_t sr; /* fsr / ssr */ 54 uint16_t fcr; 55 uint8_t sptr; 56 57 uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */ 58 uint8_t rx_cnt; 59 uint8_t rx_tail; 60 uint8_t rx_head; 61 62 int freq; 63 int feat; 64 int flags; 65 int rtrg; 66 67 CharBackend chr; 68 QEMUTimer *fifo_timeout_timer; 69 uint64_t etu; /* Elementary Time Unit (ns) */ 70 71 qemu_irq eri; 72 qemu_irq rxi; 73 qemu_irq txi; 74 qemu_irq tei; 75 qemu_irq bri; 76 } sh_serial_state; 77 78 static void sh_serial_clear_fifo(sh_serial_state * s) 79 { 80 memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); 81 s->rx_cnt = 0; 82 s->rx_head = 0; 83 s->rx_tail = 0; 84 } 85 86 static void sh_serial_write(void *opaque, hwaddr offs, 87 uint64_t val, unsigned size) 88 { 89 sh_serial_state *s = opaque; 90 unsigned char ch; 91 92 #ifdef DEBUG_SERIAL 93 printf("sh_serial: write offs=0x%02x val=0x%02x\n", 94 offs, val); 95 #endif 96 switch(offs) { 97 case 0x00: /* SMR */ 98 s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); 99 return; 100 case 0x04: /* BRR */ 101 s->brr = val; 102 return; 103 case 0x08: /* SCR */ 104 /* TODO : For SH7751, SCIF mask should be 0xfb. */ 105 s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); 106 if (!(val & (1 << 5))) 107 s->flags |= SH_SERIAL_FLAG_TEND; 108 if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) { 109 qemu_set_irq(s->txi, val & (1 << 7)); 110 } 111 if (!(val & (1 << 6))) { 112 qemu_set_irq(s->rxi, 0); 113 } 114 return; 115 case 0x0c: /* FTDR / TDR */ 116 if (qemu_chr_fe_backend_connected(&s->chr)) { 117 ch = val; 118 /* 119 * XXX this blocks entire thread. Rewrite to use 120 * qemu_chr_fe_write and background I/O callbacks 121 */ 122 qemu_chr_fe_write_all(&s->chr, &ch, 1); 123 } 124 s->dr = val; 125 s->flags &= ~SH_SERIAL_FLAG_TDE; 126 return; 127 #if 0 128 case 0x14: /* FRDR / RDR */ 129 ret = 0; 130 break; 131 #endif 132 } 133 if (s->feat & SH_SERIAL_FEAT_SCIF) { 134 switch(offs) { 135 case 0x10: /* FSR */ 136 if (!(val & (1 << 6))) 137 s->flags &= ~SH_SERIAL_FLAG_TEND; 138 if (!(val & (1 << 5))) 139 s->flags &= ~SH_SERIAL_FLAG_TDE; 140 if (!(val & (1 << 4))) 141 s->flags &= ~SH_SERIAL_FLAG_BRK; 142 if (!(val & (1 << 1))) 143 s->flags &= ~SH_SERIAL_FLAG_RDF; 144 if (!(val & (1 << 0))) 145 s->flags &= ~SH_SERIAL_FLAG_DR; 146 147 if (!(val & (1 << 1)) || !(val & (1 << 0))) { 148 if (s->rxi) { 149 qemu_set_irq(s->rxi, 0); 150 } 151 } 152 return; 153 case 0x18: /* FCR */ 154 s->fcr = val; 155 switch ((val >> 6) & 3) { 156 case 0: 157 s->rtrg = 1; 158 break; 159 case 1: 160 s->rtrg = 4; 161 break; 162 case 2: 163 s->rtrg = 8; 164 break; 165 case 3: 166 s->rtrg = 14; 167 break; 168 } 169 if (val & (1 << 1)) { 170 sh_serial_clear_fifo(s); 171 s->sr &= ~(1 << 1); 172 } 173 174 return; 175 case 0x20: /* SPTR */ 176 s->sptr = val & 0xf3; 177 return; 178 case 0x24: /* LSR */ 179 return; 180 } 181 } 182 else { 183 switch(offs) { 184 #if 0 185 case 0x0c: 186 ret = s->dr; 187 break; 188 case 0x10: 189 ret = 0; 190 break; 191 #endif 192 case 0x1c: 193 s->sptr = val & 0x8f; 194 return; 195 } 196 } 197 198 fprintf(stderr, "sh_serial: unsupported write to 0x%02" 199 HWADDR_PRIx "\n", offs); 200 abort(); 201 } 202 203 static uint64_t sh_serial_read(void *opaque, hwaddr offs, 204 unsigned size) 205 { 206 sh_serial_state *s = opaque; 207 uint32_t ret = ~0; 208 209 #if 0 210 switch(offs) { 211 case 0x00: 212 ret = s->smr; 213 break; 214 case 0x04: 215 ret = s->brr; 216 break; 217 case 0x08: 218 ret = s->scr; 219 break; 220 case 0x14: 221 ret = 0; 222 break; 223 } 224 #endif 225 if (s->feat & SH_SERIAL_FEAT_SCIF) { 226 switch(offs) { 227 case 0x00: /* SMR */ 228 ret = s->smr; 229 break; 230 case 0x08: /* SCR */ 231 ret = s->scr; 232 break; 233 case 0x10: /* FSR */ 234 ret = 0; 235 if (s->flags & SH_SERIAL_FLAG_TEND) 236 ret |= (1 << 6); 237 if (s->flags & SH_SERIAL_FLAG_TDE) 238 ret |= (1 << 5); 239 if (s->flags & SH_SERIAL_FLAG_BRK) 240 ret |= (1 << 4); 241 if (s->flags & SH_SERIAL_FLAG_RDF) 242 ret |= (1 << 1); 243 if (s->flags & SH_SERIAL_FLAG_DR) 244 ret |= (1 << 0); 245 246 if (s->scr & (1 << 5)) 247 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; 248 249 break; 250 case 0x14: 251 if (s->rx_cnt > 0) { 252 ret = s->rx_fifo[s->rx_tail++]; 253 s->rx_cnt--; 254 if (s->rx_tail == SH_RX_FIFO_LENGTH) 255 s->rx_tail = 0; 256 if (s->rx_cnt < s->rtrg) 257 s->flags &= ~SH_SERIAL_FLAG_RDF; 258 } 259 break; 260 case 0x18: 261 ret = s->fcr; 262 break; 263 case 0x1c: 264 ret = s->rx_cnt; 265 break; 266 case 0x20: 267 ret = s->sptr; 268 break; 269 case 0x24: 270 ret = 0; 271 break; 272 } 273 } 274 else { 275 switch(offs) { 276 #if 0 277 case 0x0c: 278 ret = s->dr; 279 break; 280 case 0x10: 281 ret = 0; 282 break; 283 case 0x14: 284 ret = s->rx_fifo[0]; 285 break; 286 #endif 287 case 0x1c: 288 ret = s->sptr; 289 break; 290 } 291 } 292 #ifdef DEBUG_SERIAL 293 printf("sh_serial: read offs=0x%02x val=0x%x\n", 294 offs, ret); 295 #endif 296 297 if (ret & ~((1 << 16) - 1)) { 298 fprintf(stderr, "sh_serial: unsupported read from 0x%02" 299 HWADDR_PRIx "\n", offs); 300 abort(); 301 } 302 303 return ret; 304 } 305 306 static int sh_serial_can_receive(sh_serial_state *s) 307 { 308 return s->scr & (1 << 4); 309 } 310 311 static void sh_serial_receive_break(sh_serial_state *s) 312 { 313 if (s->feat & SH_SERIAL_FEAT_SCIF) 314 s->sr |= (1 << 4); 315 } 316 317 static int sh_serial_can_receive1(void *opaque) 318 { 319 sh_serial_state *s = opaque; 320 return sh_serial_can_receive(s); 321 } 322 323 static void sh_serial_timeout_int(void *opaque) 324 { 325 sh_serial_state *s = opaque; 326 327 s->flags |= SH_SERIAL_FLAG_RDF; 328 if (s->scr & (1 << 6) && s->rxi) { 329 qemu_set_irq(s->rxi, 1); 330 } 331 } 332 333 static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) 334 { 335 sh_serial_state *s = opaque; 336 337 if (s->feat & SH_SERIAL_FEAT_SCIF) { 338 int i; 339 for (i = 0; i < size; i++) { 340 if (s->rx_cnt < SH_RX_FIFO_LENGTH) { 341 s->rx_fifo[s->rx_head++] = buf[i]; 342 if (s->rx_head == SH_RX_FIFO_LENGTH) { 343 s->rx_head = 0; 344 } 345 s->rx_cnt++; 346 if (s->rx_cnt >= s->rtrg) { 347 s->flags |= SH_SERIAL_FLAG_RDF; 348 if (s->scr & (1 << 6) && s->rxi) { 349 timer_del(s->fifo_timeout_timer); 350 qemu_set_irq(s->rxi, 1); 351 } 352 } else { 353 timer_mod(s->fifo_timeout_timer, 354 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu); 355 } 356 } 357 } 358 } else { 359 s->rx_fifo[0] = buf[0]; 360 } 361 } 362 363 static void sh_serial_event(void *opaque, QEMUChrEvent event) 364 { 365 sh_serial_state *s = opaque; 366 if (event == CHR_EVENT_BREAK) 367 sh_serial_receive_break(s); 368 } 369 370 static const MemoryRegionOps sh_serial_ops = { 371 .read = sh_serial_read, 372 .write = sh_serial_write, 373 .endianness = DEVICE_NATIVE_ENDIAN, 374 }; 375 376 void sh_serial_init(MemoryRegion *sysmem, 377 hwaddr base, int feat, 378 uint32_t freq, Chardev *chr, 379 qemu_irq eri_source, 380 qemu_irq rxi_source, 381 qemu_irq txi_source, 382 qemu_irq tei_source, 383 qemu_irq bri_source) 384 { 385 sh_serial_state *s; 386 387 s = g_malloc0(sizeof(sh_serial_state)); 388 389 s->feat = feat; 390 s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; 391 s->rtrg = 1; 392 393 s->smr = 0; 394 s->brr = 0xff; 395 s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */ 396 s->sptr = 0; 397 398 if (feat & SH_SERIAL_FEAT_SCIF) { 399 s->fcr = 0; 400 } 401 else { 402 s->dr = 0xff; 403 } 404 405 sh_serial_clear_fifo(s); 406 407 memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s, 408 "serial", 0x100000000ULL); 409 410 memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem, 411 0, 0x28); 412 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); 413 414 memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem, 415 0, 0x28); 416 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); 417 418 if (chr) { 419 qemu_chr_fe_init(&s->chr, chr, &error_abort); 420 qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1, 421 sh_serial_receive1, 422 sh_serial_event, NULL, s, NULL, true); 423 } 424 425 s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 426 sh_serial_timeout_int, s); 427 s->etu = NANOSECONDS_PER_SECOND / 9600; 428 s->eri = eri_source; 429 s->rxi = rxi_source; 430 s->txi = txi_source; 431 s->tei = tei_source; 432 s->bri = bri_source; 433 } 434