1 /* 2 * QEMU 16550A multi UART emulation 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Copyright (c) 2003-2004 Fabrice Bellard 7 * Copyright (c) 2008 Citrix Systems, Inc. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 /* see docs/specs/pci-serial.rst */ 29 30 #include "qemu/osdep.h" 31 #include "qapi/error.h" 32 #include "hw/char/serial.h" 33 #include "hw/irq.h" 34 #include "hw/pci/pci_device.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/qdev-properties-system.h" 37 #include "migration/vmstate.h" 38 39 #define PCI_SERIAL_MAX_PORTS 4 40 41 typedef struct PCIMultiSerialState { 42 PCIDevice dev; 43 MemoryRegion iobar; 44 uint32_t ports; 45 char *name[PCI_SERIAL_MAX_PORTS]; 46 SerialState state[PCI_SERIAL_MAX_PORTS]; 47 uint32_t level[PCI_SERIAL_MAX_PORTS]; 48 IRQState irqs[PCI_SERIAL_MAX_PORTS]; 49 } PCIMultiSerialState; 50 51 static void multi_serial_pci_exit(PCIDevice *dev) 52 { 53 PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); 54 SerialState *s; 55 int i; 56 57 for (i = 0; i < pci->ports; i++) { 58 s = pci->state + i; 59 qdev_unrealize(DEVICE(s)); 60 memory_region_del_subregion(&pci->iobar, &s->io); 61 g_free(pci->name[i]); 62 } 63 } 64 65 static void multi_serial_irq_mux(void *opaque, int n, int level) 66 { 67 PCIMultiSerialState *pci = opaque; 68 int i, pending = 0; 69 70 pci->level[n] = level; 71 for (i = 0; i < pci->ports; i++) { 72 if (pci->level[i]) { 73 pending = 1; 74 } 75 } 76 pci_set_irq(&pci->dev, pending); 77 } 78 79 static size_t multi_serial_get_port_count(PCIDeviceClass *pc) 80 { 81 switch (pc->device_id) { 82 case 0x0003: 83 return 2; 84 case 0x0004: 85 return 4; 86 } 87 88 g_assert_not_reached(); 89 } 90 91 92 static void multi_serial_pci_realize(PCIDevice *dev, Error **errp) 93 { 94 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 95 PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); 96 SerialState *s; 97 size_t i, nports = multi_serial_get_port_count(pc); 98 99 pci->dev.config[PCI_CLASS_PROG] = 2; /* 16550 compatible */ 100 pci->dev.config[PCI_INTERRUPT_PIN] = 1; 101 memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nports); 102 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar); 103 104 for (i = 0; i < nports; i++) { 105 s = pci->state + i; 106 if (!qdev_realize(DEVICE(s), NULL, errp)) { 107 multi_serial_pci_exit(dev); 108 return; 109 } 110 s->irq = &pci->irqs[i]; 111 pci->name[i] = g_strdup_printf("uart #%zu", i + 1); 112 memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, 113 pci->name[i], 8); 114 memory_region_add_subregion(&pci->iobar, 8 * i, &s->io); 115 pci->ports++; 116 } 117 } 118 119 static const VMStateDescription vmstate_pci_multi_serial = { 120 .name = "pci-serial-multi", 121 .version_id = 1, 122 .minimum_version_id = 1, 123 .fields = (const VMStateField[]) { 124 VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState), 125 VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS, 126 0, vmstate_serial, SerialState), 127 VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS), 128 VMSTATE_END_OF_LIST() 129 } 130 }; 131 132 static const Property multi_2x_serial_pci_properties[] = { 133 DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), 134 DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), 135 }; 136 137 static const Property multi_4x_serial_pci_properties[] = { 138 DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), 139 DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), 140 DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr), 141 DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr), 142 }; 143 144 static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, 145 const void *data) 146 { 147 DeviceClass *dc = DEVICE_CLASS(klass); 148 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 149 pc->realize = multi_serial_pci_realize; 150 pc->exit = multi_serial_pci_exit; 151 pc->vendor_id = PCI_VENDOR_ID_REDHAT; 152 pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2; 153 pc->revision = 1; 154 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 155 dc->vmsd = &vmstate_pci_multi_serial; 156 device_class_set_props(dc, multi_2x_serial_pci_properties); 157 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 158 } 159 160 static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, 161 const void *data) 162 { 163 DeviceClass *dc = DEVICE_CLASS(klass); 164 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 165 pc->realize = multi_serial_pci_realize; 166 pc->exit = multi_serial_pci_exit; 167 pc->vendor_id = PCI_VENDOR_ID_REDHAT; 168 pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4; 169 pc->revision = 1; 170 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 171 dc->vmsd = &vmstate_pci_multi_serial; 172 device_class_set_props(dc, multi_4x_serial_pci_properties); 173 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 174 } 175 176 static void multi_serial_init(Object *o) 177 { 178 PCIDevice *dev = PCI_DEVICE(o); 179 PCIMultiSerialState *pms = DO_UPCAST(PCIMultiSerialState, dev, dev); 180 size_t i, nports = multi_serial_get_port_count(PCI_DEVICE_GET_CLASS(dev)); 181 182 for (i = 0; i < nports; i++) { 183 qemu_init_irq(&pms->irqs[i], multi_serial_irq_mux, pms, i); 184 object_initialize_child(o, "serial[*]", &pms->state[i], TYPE_SERIAL); 185 } 186 } 187 188 static const TypeInfo multi_2x_serial_pci_info = { 189 .name = "pci-serial-2x", 190 .parent = TYPE_PCI_DEVICE, 191 .instance_size = sizeof(PCIMultiSerialState), 192 .instance_init = multi_serial_init, 193 .class_init = multi_2x_serial_pci_class_initfn, 194 .interfaces = (const InterfaceInfo[]) { 195 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 196 { }, 197 }, 198 }; 199 200 static const TypeInfo multi_4x_serial_pci_info = { 201 .name = "pci-serial-4x", 202 .parent = TYPE_PCI_DEVICE, 203 .instance_size = sizeof(PCIMultiSerialState), 204 .instance_init = multi_serial_init, 205 .class_init = multi_4x_serial_pci_class_initfn, 206 .interfaces = (const InterfaceInfo[]) { 207 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 208 { }, 209 }, 210 }; 211 212 static void multi_serial_pci_register_types(void) 213 { 214 type_register_static(&multi_2x_serial_pci_info); 215 type_register_static(&multi_4x_serial_pci_info); 216 } 217 218 type_init(multi_serial_pci_register_types) 219