xref: /qemu/hw/char/serial-pci-multi.c (revision d6454270575da1f16a8923c7cb240e46ef243f72)
1d09ecd8cSThomas Huth /*
2d09ecd8cSThomas Huth  * QEMU 16550A multi UART emulation
3d09ecd8cSThomas Huth  *
4d09ecd8cSThomas Huth  * SPDX-License-Identifier: MIT
5d09ecd8cSThomas Huth  *
6d09ecd8cSThomas Huth  * Copyright (c) 2003-2004 Fabrice Bellard
7d09ecd8cSThomas Huth  * Copyright (c) 2008 Citrix Systems, Inc.
8d09ecd8cSThomas Huth  *
9d09ecd8cSThomas Huth  * Permission is hereby granted, free of charge, to any person obtaining a copy
10d09ecd8cSThomas Huth  * of this software and associated documentation files (the "Software"), to deal
11d09ecd8cSThomas Huth  * in the Software without restriction, including without limitation the rights
12d09ecd8cSThomas Huth  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13d09ecd8cSThomas Huth  * copies of the Software, and to permit persons to whom the Software is
14d09ecd8cSThomas Huth  * furnished to do so, subject to the following conditions:
15d09ecd8cSThomas Huth  *
16d09ecd8cSThomas Huth  * The above copyright notice and this permission notice shall be included in
17d09ecd8cSThomas Huth  * all copies or substantial portions of the Software.
18d09ecd8cSThomas Huth  *
19d09ecd8cSThomas Huth  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20d09ecd8cSThomas Huth  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21d09ecd8cSThomas Huth  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22d09ecd8cSThomas Huth  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23d09ecd8cSThomas Huth  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24d09ecd8cSThomas Huth  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25d09ecd8cSThomas Huth  * THE SOFTWARE.
26d09ecd8cSThomas Huth  */
27d09ecd8cSThomas Huth 
28d09ecd8cSThomas Huth /* see docs/specs/pci-serial.txt */
29d09ecd8cSThomas Huth 
30d09ecd8cSThomas Huth #include "qemu/osdep.h"
31d09ecd8cSThomas Huth #include "qapi/error.h"
32d09ecd8cSThomas Huth #include "hw/char/serial.h"
3364552b6bSMarkus Armbruster #include "hw/irq.h"
34d09ecd8cSThomas Huth #include "hw/pci/pci.h"
35*d6454270SMarkus Armbruster #include "migration/vmstate.h"
36d09ecd8cSThomas Huth 
37d09ecd8cSThomas Huth #define PCI_SERIAL_MAX_PORTS 4
38d09ecd8cSThomas Huth 
39d09ecd8cSThomas Huth typedef struct PCIMultiSerialState {
40d09ecd8cSThomas Huth     PCIDevice    dev;
41d09ecd8cSThomas Huth     MemoryRegion iobar;
42d09ecd8cSThomas Huth     uint32_t     ports;
43d09ecd8cSThomas Huth     char         *name[PCI_SERIAL_MAX_PORTS];
44d09ecd8cSThomas Huth     SerialState  state[PCI_SERIAL_MAX_PORTS];
45d09ecd8cSThomas Huth     uint32_t     level[PCI_SERIAL_MAX_PORTS];
46d09ecd8cSThomas Huth     qemu_irq     *irqs;
47d09ecd8cSThomas Huth     uint8_t      prog_if;
48d09ecd8cSThomas Huth } PCIMultiSerialState;
49d09ecd8cSThomas Huth 
50d09ecd8cSThomas Huth static void multi_serial_pci_exit(PCIDevice *dev)
51d09ecd8cSThomas Huth {
52d09ecd8cSThomas Huth     PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
53d09ecd8cSThomas Huth     SerialState *s;
54d09ecd8cSThomas Huth     int i;
55d09ecd8cSThomas Huth 
56d09ecd8cSThomas Huth     for (i = 0; i < pci->ports; i++) {
57d09ecd8cSThomas Huth         s = pci->state + i;
58d09ecd8cSThomas Huth         serial_exit_core(s);
59d09ecd8cSThomas Huth         memory_region_del_subregion(&pci->iobar, &s->io);
60d09ecd8cSThomas Huth         g_free(pci->name[i]);
61d09ecd8cSThomas Huth     }
62d09ecd8cSThomas Huth     qemu_free_irqs(pci->irqs, pci->ports);
63d09ecd8cSThomas Huth }
64d09ecd8cSThomas Huth 
65d09ecd8cSThomas Huth static void multi_serial_irq_mux(void *opaque, int n, int level)
66d09ecd8cSThomas Huth {
67d09ecd8cSThomas Huth     PCIMultiSerialState *pci = opaque;
68d09ecd8cSThomas Huth     int i, pending = 0;
69d09ecd8cSThomas Huth 
70d09ecd8cSThomas Huth     pci->level[n] = level;
71d09ecd8cSThomas Huth     for (i = 0; i < pci->ports; i++) {
72d09ecd8cSThomas Huth         if (pci->level[i]) {
73d09ecd8cSThomas Huth             pending = 1;
74d09ecd8cSThomas Huth         }
75d09ecd8cSThomas Huth     }
76d09ecd8cSThomas Huth     pci_set_irq(&pci->dev, pending);
77d09ecd8cSThomas Huth }
78d09ecd8cSThomas Huth 
79d09ecd8cSThomas Huth static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
80d09ecd8cSThomas Huth {
81d09ecd8cSThomas Huth     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
82d09ecd8cSThomas Huth     PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
83d09ecd8cSThomas Huth     SerialState *s;
84d09ecd8cSThomas Huth     Error *err = NULL;
85d09ecd8cSThomas Huth     int i, nr_ports = 0;
86d09ecd8cSThomas Huth 
87d09ecd8cSThomas Huth     switch (pc->device_id) {
88d09ecd8cSThomas Huth     case 0x0003:
89d09ecd8cSThomas Huth         nr_ports = 2;
90d09ecd8cSThomas Huth         break;
91d09ecd8cSThomas Huth     case 0x0004:
92d09ecd8cSThomas Huth         nr_ports = 4;
93d09ecd8cSThomas Huth         break;
94d09ecd8cSThomas Huth     }
95d09ecd8cSThomas Huth     assert(nr_ports > 0);
96d09ecd8cSThomas Huth     assert(nr_ports <= PCI_SERIAL_MAX_PORTS);
97d09ecd8cSThomas Huth 
98d09ecd8cSThomas Huth     pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
99d09ecd8cSThomas Huth     pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
100d09ecd8cSThomas Huth     memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
101d09ecd8cSThomas Huth     pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
102d09ecd8cSThomas Huth     pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
103d09ecd8cSThomas Huth                                    nr_ports);
104d09ecd8cSThomas Huth 
105d09ecd8cSThomas Huth     for (i = 0; i < nr_ports; i++) {
106d09ecd8cSThomas Huth         s = pci->state + i;
107d09ecd8cSThomas Huth         s->baudbase = 115200;
108d09ecd8cSThomas Huth         serial_realize_core(s, &err);
109d09ecd8cSThomas Huth         if (err != NULL) {
110d09ecd8cSThomas Huth             error_propagate(errp, err);
111d09ecd8cSThomas Huth             multi_serial_pci_exit(dev);
112d09ecd8cSThomas Huth             return;
113d09ecd8cSThomas Huth         }
114d09ecd8cSThomas Huth         s->irq = pci->irqs[i];
115d09ecd8cSThomas Huth         pci->name[i] = g_strdup_printf("uart #%d", i + 1);
116d09ecd8cSThomas Huth         memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
117d09ecd8cSThomas Huth                               pci->name[i], 8);
118d09ecd8cSThomas Huth         memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
119d09ecd8cSThomas Huth         pci->ports++;
120d09ecd8cSThomas Huth     }
121d09ecd8cSThomas Huth }
122d09ecd8cSThomas Huth 
123d09ecd8cSThomas Huth static const VMStateDescription vmstate_pci_multi_serial = {
124d09ecd8cSThomas Huth     .name = "pci-serial-multi",
125d09ecd8cSThomas Huth     .version_id = 1,
126d09ecd8cSThomas Huth     .minimum_version_id = 1,
127d09ecd8cSThomas Huth     .fields = (VMStateField[]) {
128d09ecd8cSThomas Huth         VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
129d09ecd8cSThomas Huth         VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
130d09ecd8cSThomas Huth                              0, vmstate_serial, SerialState),
131d09ecd8cSThomas Huth         VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
132d09ecd8cSThomas Huth         VMSTATE_END_OF_LIST()
133d09ecd8cSThomas Huth     }
134d09ecd8cSThomas Huth };
135d09ecd8cSThomas Huth 
136d09ecd8cSThomas Huth static Property multi_2x_serial_pci_properties[] = {
137d09ecd8cSThomas Huth     DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
138d09ecd8cSThomas Huth     DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
139d09ecd8cSThomas Huth     DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
140d09ecd8cSThomas Huth     DEFINE_PROP_END_OF_LIST(),
141d09ecd8cSThomas Huth };
142d09ecd8cSThomas Huth 
143d09ecd8cSThomas Huth static Property multi_4x_serial_pci_properties[] = {
144d09ecd8cSThomas Huth     DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
145d09ecd8cSThomas Huth     DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
146d09ecd8cSThomas Huth     DEFINE_PROP_CHR("chardev3",  PCIMultiSerialState, state[2].chr),
147d09ecd8cSThomas Huth     DEFINE_PROP_CHR("chardev4",  PCIMultiSerialState, state[3].chr),
148d09ecd8cSThomas Huth     DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
149d09ecd8cSThomas Huth     DEFINE_PROP_END_OF_LIST(),
150d09ecd8cSThomas Huth };
151d09ecd8cSThomas Huth 
152d09ecd8cSThomas Huth static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
153d09ecd8cSThomas Huth {
154d09ecd8cSThomas Huth     DeviceClass *dc = DEVICE_CLASS(klass);
155d09ecd8cSThomas Huth     PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
156d09ecd8cSThomas Huth     pc->realize = multi_serial_pci_realize;
157d09ecd8cSThomas Huth     pc->exit = multi_serial_pci_exit;
158d09ecd8cSThomas Huth     pc->vendor_id = PCI_VENDOR_ID_REDHAT;
159d09ecd8cSThomas Huth     pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
160d09ecd8cSThomas Huth     pc->revision = 1;
161d09ecd8cSThomas Huth     pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
162d09ecd8cSThomas Huth     dc->vmsd = &vmstate_pci_multi_serial;
163d09ecd8cSThomas Huth     dc->props = multi_2x_serial_pci_properties;
164d09ecd8cSThomas Huth     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
165d09ecd8cSThomas Huth }
166d09ecd8cSThomas Huth 
167d09ecd8cSThomas Huth static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
168d09ecd8cSThomas Huth {
169d09ecd8cSThomas Huth     DeviceClass *dc = DEVICE_CLASS(klass);
170d09ecd8cSThomas Huth     PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
171d09ecd8cSThomas Huth     pc->realize = multi_serial_pci_realize;
172d09ecd8cSThomas Huth     pc->exit = multi_serial_pci_exit;
173d09ecd8cSThomas Huth     pc->vendor_id = PCI_VENDOR_ID_REDHAT;
174d09ecd8cSThomas Huth     pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
175d09ecd8cSThomas Huth     pc->revision = 1;
176d09ecd8cSThomas Huth     pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
177d09ecd8cSThomas Huth     dc->vmsd = &vmstate_pci_multi_serial;
178d09ecd8cSThomas Huth     dc->props = multi_4x_serial_pci_properties;
179d09ecd8cSThomas Huth     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
180d09ecd8cSThomas Huth }
181d09ecd8cSThomas Huth 
182d09ecd8cSThomas Huth static const TypeInfo multi_2x_serial_pci_info = {
183d09ecd8cSThomas Huth     .name          = "pci-serial-2x",
184d09ecd8cSThomas Huth     .parent        = TYPE_PCI_DEVICE,
185d09ecd8cSThomas Huth     .instance_size = sizeof(PCIMultiSerialState),
186d09ecd8cSThomas Huth     .class_init    = multi_2x_serial_pci_class_initfn,
187d09ecd8cSThomas Huth     .interfaces = (InterfaceInfo[]) {
188d09ecd8cSThomas Huth         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
189d09ecd8cSThomas Huth         { },
190d09ecd8cSThomas Huth     },
191d09ecd8cSThomas Huth };
192d09ecd8cSThomas Huth 
193d09ecd8cSThomas Huth static const TypeInfo multi_4x_serial_pci_info = {
194d09ecd8cSThomas Huth     .name          = "pci-serial-4x",
195d09ecd8cSThomas Huth     .parent        = TYPE_PCI_DEVICE,
196d09ecd8cSThomas Huth     .instance_size = sizeof(PCIMultiSerialState),
197d09ecd8cSThomas Huth     .class_init    = multi_4x_serial_pci_class_initfn,
198d09ecd8cSThomas Huth     .interfaces = (InterfaceInfo[]) {
199d09ecd8cSThomas Huth         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
200d09ecd8cSThomas Huth         { },
201d09ecd8cSThomas Huth     },
202d09ecd8cSThomas Huth };
203d09ecd8cSThomas Huth 
204d09ecd8cSThomas Huth static void multi_serial_pci_register_types(void)
205d09ecd8cSThomas Huth {
206d09ecd8cSThomas Huth     type_register_static(&multi_2x_serial_pci_info);
207d09ecd8cSThomas Huth     type_register_static(&multi_4x_serial_pci_info);
208d09ecd8cSThomas Huth }
209d09ecd8cSThomas Huth 
210d09ecd8cSThomas Huth type_init(multi_serial_pci_register_types)
211