1d09ecd8cSThomas Huth /* 2d09ecd8cSThomas Huth * QEMU 16550A multi UART emulation 3d09ecd8cSThomas Huth * 4d09ecd8cSThomas Huth * SPDX-License-Identifier: MIT 5d09ecd8cSThomas Huth * 6d09ecd8cSThomas Huth * Copyright (c) 2003-2004 Fabrice Bellard 7d09ecd8cSThomas Huth * Copyright (c) 2008 Citrix Systems, Inc. 8d09ecd8cSThomas Huth * 9d09ecd8cSThomas Huth * Permission is hereby granted, free of charge, to any person obtaining a copy 10d09ecd8cSThomas Huth * of this software and associated documentation files (the "Software"), to deal 11d09ecd8cSThomas Huth * in the Software without restriction, including without limitation the rights 12d09ecd8cSThomas Huth * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13d09ecd8cSThomas Huth * copies of the Software, and to permit persons to whom the Software is 14d09ecd8cSThomas Huth * furnished to do so, subject to the following conditions: 15d09ecd8cSThomas Huth * 16d09ecd8cSThomas Huth * The above copyright notice and this permission notice shall be included in 17d09ecd8cSThomas Huth * all copies or substantial portions of the Software. 18d09ecd8cSThomas Huth * 19d09ecd8cSThomas Huth * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20d09ecd8cSThomas Huth * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21d09ecd8cSThomas Huth * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22d09ecd8cSThomas Huth * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23d09ecd8cSThomas Huth * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24d09ecd8cSThomas Huth * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25d09ecd8cSThomas Huth * THE SOFTWARE. 26d09ecd8cSThomas Huth */ 27d09ecd8cSThomas Huth 28d09ecd8cSThomas Huth /* see docs/specs/pci-serial.txt */ 29d09ecd8cSThomas Huth 30d09ecd8cSThomas Huth #include "qemu/osdep.h" 31d09ecd8cSThomas Huth #include "qapi/error.h" 32d09ecd8cSThomas Huth #include "hw/char/serial.h" 3364552b6bSMarkus Armbruster #include "hw/irq.h" 34d09ecd8cSThomas Huth #include "hw/pci/pci.h" 35a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 36*ce35e229SEduardo Habkost #include "hw/qdev-properties-system.h" 37d6454270SMarkus Armbruster #include "migration/vmstate.h" 38d09ecd8cSThomas Huth 39d09ecd8cSThomas Huth #define PCI_SERIAL_MAX_PORTS 4 40d09ecd8cSThomas Huth 41d09ecd8cSThomas Huth typedef struct PCIMultiSerialState { 42d09ecd8cSThomas Huth PCIDevice dev; 43d09ecd8cSThomas Huth MemoryRegion iobar; 44d09ecd8cSThomas Huth uint32_t ports; 45d09ecd8cSThomas Huth char *name[PCI_SERIAL_MAX_PORTS]; 46d09ecd8cSThomas Huth SerialState state[PCI_SERIAL_MAX_PORTS]; 47d09ecd8cSThomas Huth uint32_t level[PCI_SERIAL_MAX_PORTS]; 48d09ecd8cSThomas Huth qemu_irq *irqs; 49d09ecd8cSThomas Huth uint8_t prog_if; 50d09ecd8cSThomas Huth } PCIMultiSerialState; 51d09ecd8cSThomas Huth 52d09ecd8cSThomas Huth static void multi_serial_pci_exit(PCIDevice *dev) 53d09ecd8cSThomas Huth { 54d09ecd8cSThomas Huth PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); 55d09ecd8cSThomas Huth SerialState *s; 56d09ecd8cSThomas Huth int i; 57d09ecd8cSThomas Huth 58d09ecd8cSThomas Huth for (i = 0; i < pci->ports; i++) { 59d09ecd8cSThomas Huth s = pci->state + i; 60981c3dcdSMarkus Armbruster qdev_unrealize(DEVICE(s)); 61d09ecd8cSThomas Huth memory_region_del_subregion(&pci->iobar, &s->io); 62d09ecd8cSThomas Huth g_free(pci->name[i]); 63d09ecd8cSThomas Huth } 64d09ecd8cSThomas Huth qemu_free_irqs(pci->irqs, pci->ports); 65d09ecd8cSThomas Huth } 66d09ecd8cSThomas Huth 67d09ecd8cSThomas Huth static void multi_serial_irq_mux(void *opaque, int n, int level) 68d09ecd8cSThomas Huth { 69d09ecd8cSThomas Huth PCIMultiSerialState *pci = opaque; 70d09ecd8cSThomas Huth int i, pending = 0; 71d09ecd8cSThomas Huth 72d09ecd8cSThomas Huth pci->level[n] = level; 73d09ecd8cSThomas Huth for (i = 0; i < pci->ports; i++) { 74d09ecd8cSThomas Huth if (pci->level[i]) { 75d09ecd8cSThomas Huth pending = 1; 76d09ecd8cSThomas Huth } 77d09ecd8cSThomas Huth } 78d09ecd8cSThomas Huth pci_set_irq(&pci->dev, pending); 79d09ecd8cSThomas Huth } 80d09ecd8cSThomas Huth 814305d482SMarc-André Lureau static size_t multi_serial_get_port_count(PCIDeviceClass *pc) 824305d482SMarc-André Lureau { 834305d482SMarc-André Lureau switch (pc->device_id) { 844305d482SMarc-André Lureau case 0x0003: 854305d482SMarc-André Lureau return 2; 864305d482SMarc-André Lureau case 0x0004: 874305d482SMarc-André Lureau return 4; 884305d482SMarc-André Lureau } 894305d482SMarc-André Lureau 904305d482SMarc-André Lureau g_assert_not_reached(); 914305d482SMarc-André Lureau } 924305d482SMarc-André Lureau 934305d482SMarc-André Lureau 94d09ecd8cSThomas Huth static void multi_serial_pci_realize(PCIDevice *dev, Error **errp) 95d09ecd8cSThomas Huth { 96d09ecd8cSThomas Huth PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 97d09ecd8cSThomas Huth PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); 98d09ecd8cSThomas Huth SerialState *s; 994305d482SMarc-André Lureau size_t i, nports = multi_serial_get_port_count(pc); 100d09ecd8cSThomas Huth 101d09ecd8cSThomas Huth pci->dev.config[PCI_CLASS_PROG] = pci->prog_if; 102d09ecd8cSThomas Huth pci->dev.config[PCI_INTERRUPT_PIN] = 0x01; 1034305d482SMarc-André Lureau memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nports); 104d09ecd8cSThomas Huth pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar); 1054305d482SMarc-André Lureau pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, nports); 106d09ecd8cSThomas Huth 1074305d482SMarc-André Lureau for (i = 0; i < nports; i++) { 108d09ecd8cSThomas Huth s = pci->state + i; 109668f62ecSMarkus Armbruster if (!qdev_realize(DEVICE(s), NULL, errp)) { 110d09ecd8cSThomas Huth multi_serial_pci_exit(dev); 111d09ecd8cSThomas Huth return; 112d09ecd8cSThomas Huth } 113d09ecd8cSThomas Huth s->irq = pci->irqs[i]; 1144305d482SMarc-André Lureau pci->name[i] = g_strdup_printf("uart #%zu", i + 1); 115d09ecd8cSThomas Huth memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, 116d09ecd8cSThomas Huth pci->name[i], 8); 117d09ecd8cSThomas Huth memory_region_add_subregion(&pci->iobar, 8 * i, &s->io); 118d09ecd8cSThomas Huth pci->ports++; 119d09ecd8cSThomas Huth } 120d09ecd8cSThomas Huth } 121d09ecd8cSThomas Huth 122d09ecd8cSThomas Huth static const VMStateDescription vmstate_pci_multi_serial = { 123d09ecd8cSThomas Huth .name = "pci-serial-multi", 124d09ecd8cSThomas Huth .version_id = 1, 125d09ecd8cSThomas Huth .minimum_version_id = 1, 126d09ecd8cSThomas Huth .fields = (VMStateField[]) { 127d09ecd8cSThomas Huth VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState), 128d09ecd8cSThomas Huth VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS, 129d09ecd8cSThomas Huth 0, vmstate_serial, SerialState), 130d09ecd8cSThomas Huth VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS), 131d09ecd8cSThomas Huth VMSTATE_END_OF_LIST() 132d09ecd8cSThomas Huth } 133d09ecd8cSThomas Huth }; 134d09ecd8cSThomas Huth 135d09ecd8cSThomas Huth static Property multi_2x_serial_pci_properties[] = { 136d09ecd8cSThomas Huth DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), 137d09ecd8cSThomas Huth DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), 138d09ecd8cSThomas Huth DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02), 139d09ecd8cSThomas Huth DEFINE_PROP_END_OF_LIST(), 140d09ecd8cSThomas Huth }; 141d09ecd8cSThomas Huth 142d09ecd8cSThomas Huth static Property multi_4x_serial_pci_properties[] = { 143d09ecd8cSThomas Huth DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), 144d09ecd8cSThomas Huth DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), 145d09ecd8cSThomas Huth DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr), 146d09ecd8cSThomas Huth DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr), 147d09ecd8cSThomas Huth DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02), 148d09ecd8cSThomas Huth DEFINE_PROP_END_OF_LIST(), 149d09ecd8cSThomas Huth }; 150d09ecd8cSThomas Huth 151d09ecd8cSThomas Huth static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data) 152d09ecd8cSThomas Huth { 153d09ecd8cSThomas Huth DeviceClass *dc = DEVICE_CLASS(klass); 154d09ecd8cSThomas Huth PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 155d09ecd8cSThomas Huth pc->realize = multi_serial_pci_realize; 156d09ecd8cSThomas Huth pc->exit = multi_serial_pci_exit; 157d09ecd8cSThomas Huth pc->vendor_id = PCI_VENDOR_ID_REDHAT; 158d09ecd8cSThomas Huth pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2; 159d09ecd8cSThomas Huth pc->revision = 1; 160d09ecd8cSThomas Huth pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 161d09ecd8cSThomas Huth dc->vmsd = &vmstate_pci_multi_serial; 1624f67d30bSMarc-André Lureau device_class_set_props(dc, multi_2x_serial_pci_properties); 163d09ecd8cSThomas Huth set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 164d09ecd8cSThomas Huth } 165d09ecd8cSThomas Huth 166d09ecd8cSThomas Huth static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data) 167d09ecd8cSThomas Huth { 168d09ecd8cSThomas Huth DeviceClass *dc = DEVICE_CLASS(klass); 169d09ecd8cSThomas Huth PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 170d09ecd8cSThomas Huth pc->realize = multi_serial_pci_realize; 171d09ecd8cSThomas Huth pc->exit = multi_serial_pci_exit; 172d09ecd8cSThomas Huth pc->vendor_id = PCI_VENDOR_ID_REDHAT; 173d09ecd8cSThomas Huth pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4; 174d09ecd8cSThomas Huth pc->revision = 1; 175d09ecd8cSThomas Huth pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 176d09ecd8cSThomas Huth dc->vmsd = &vmstate_pci_multi_serial; 1774f67d30bSMarc-André Lureau device_class_set_props(dc, multi_4x_serial_pci_properties); 178d09ecd8cSThomas Huth set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 179d09ecd8cSThomas Huth } 180d09ecd8cSThomas Huth 1817781b88eSMarc-André Lureau static void multi_serial_init(Object *o) 1827781b88eSMarc-André Lureau { 1837781b88eSMarc-André Lureau PCIDevice *dev = PCI_DEVICE(o); 1847781b88eSMarc-André Lureau PCIMultiSerialState *pms = DO_UPCAST(PCIMultiSerialState, dev, dev); 1857781b88eSMarc-André Lureau size_t i, nports = multi_serial_get_port_count(PCI_DEVICE_GET_CLASS(dev)); 1867781b88eSMarc-André Lureau 1877781b88eSMarc-André Lureau for (i = 0; i < nports; i++) { 1889fc7fc4dSMarkus Armbruster object_initialize_child(o, "serial[*]", &pms->state[i], TYPE_SERIAL); 1897781b88eSMarc-André Lureau } 1907781b88eSMarc-André Lureau } 1917781b88eSMarc-André Lureau 192d09ecd8cSThomas Huth static const TypeInfo multi_2x_serial_pci_info = { 193d09ecd8cSThomas Huth .name = "pci-serial-2x", 194d09ecd8cSThomas Huth .parent = TYPE_PCI_DEVICE, 195d09ecd8cSThomas Huth .instance_size = sizeof(PCIMultiSerialState), 1967781b88eSMarc-André Lureau .instance_init = multi_serial_init, 197d09ecd8cSThomas Huth .class_init = multi_2x_serial_pci_class_initfn, 198d09ecd8cSThomas Huth .interfaces = (InterfaceInfo[]) { 199d09ecd8cSThomas Huth { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 200d09ecd8cSThomas Huth { }, 201d09ecd8cSThomas Huth }, 202d09ecd8cSThomas Huth }; 203d09ecd8cSThomas Huth 204d09ecd8cSThomas Huth static const TypeInfo multi_4x_serial_pci_info = { 205d09ecd8cSThomas Huth .name = "pci-serial-4x", 206d09ecd8cSThomas Huth .parent = TYPE_PCI_DEVICE, 207d09ecd8cSThomas Huth .instance_size = sizeof(PCIMultiSerialState), 2087781b88eSMarc-André Lureau .instance_init = multi_serial_init, 209d09ecd8cSThomas Huth .class_init = multi_4x_serial_pci_class_initfn, 210d09ecd8cSThomas Huth .interfaces = (InterfaceInfo[]) { 211d09ecd8cSThomas Huth { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 212d09ecd8cSThomas Huth { }, 213d09ecd8cSThomas Huth }, 214d09ecd8cSThomas Huth }; 215d09ecd8cSThomas Huth 216d09ecd8cSThomas Huth static void multi_serial_pci_register_types(void) 217d09ecd8cSThomas Huth { 218d09ecd8cSThomas Huth type_register_static(&multi_2x_serial_pci_info); 219d09ecd8cSThomas Huth type_register_static(&multi_4x_serial_pci_info); 220d09ecd8cSThomas Huth } 221d09ecd8cSThomas Huth 222d09ecd8cSThomas Huth type_init(multi_serial_pci_register_types) 223