1 /* 2 * QEMU Parallel PORT emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2007 Marko Kohtala 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "hw/hw.h" 28 #include "sysemu/char.h" 29 #include "hw/isa/isa.h" 30 #include "hw/i386/pc.h" 31 #include "sysemu/sysemu.h" 32 33 //#define DEBUG_PARALLEL 34 35 #ifdef DEBUG_PARALLEL 36 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) 37 #else 38 #define pdebug(fmt, ...) ((void)0) 39 #endif 40 41 #define PARA_REG_DATA 0 42 #define PARA_REG_STS 1 43 #define PARA_REG_CTR 2 44 #define PARA_REG_EPP_ADDR 3 45 #define PARA_REG_EPP_DATA 4 46 47 /* 48 * These are the definitions for the Printer Status Register 49 */ 50 #define PARA_STS_BUSY 0x80 /* Busy complement */ 51 #define PARA_STS_ACK 0x40 /* Acknowledge */ 52 #define PARA_STS_PAPER 0x20 /* Out of paper */ 53 #define PARA_STS_ONLINE 0x10 /* Online */ 54 #define PARA_STS_ERROR 0x08 /* Error complement */ 55 #define PARA_STS_TMOUT 0x01 /* EPP timeout */ 56 57 /* 58 * These are the definitions for the Printer Control Register 59 */ 60 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ 61 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ 62 #define PARA_CTR_SELECT 0x08 /* Select In complement */ 63 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ 64 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ 65 #define PARA_CTR_STROBE 0x01 /* Strobe complement */ 66 67 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) 68 69 typedef struct ParallelState { 70 MemoryRegion iomem; 71 uint8_t dataw; 72 uint8_t datar; 73 uint8_t status; 74 uint8_t control; 75 qemu_irq irq; 76 int irq_pending; 77 CharDriverState *chr; 78 int hw_driver; 79 int epp_timeout; 80 uint32_t last_read_offset; /* For debugging */ 81 /* Memory-mapped interface */ 82 int it_shift; 83 PortioList portio_list; 84 } ParallelState; 85 86 #define TYPE_ISA_PARALLEL "isa-parallel" 87 #define ISA_PARALLEL(obj) \ 88 OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL) 89 90 typedef struct ISAParallelState { 91 ISADevice parent_obj; 92 93 uint32_t index; 94 uint32_t iobase; 95 uint32_t isairq; 96 ParallelState state; 97 } ISAParallelState; 98 99 static void parallel_update_irq(ParallelState *s) 100 { 101 if (s->irq_pending) 102 qemu_irq_raise(s->irq); 103 else 104 qemu_irq_lower(s->irq); 105 } 106 107 static void 108 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) 109 { 110 ParallelState *s = opaque; 111 112 pdebug("write addr=0x%02x val=0x%02x\n", addr, val); 113 114 addr &= 7; 115 switch(addr) { 116 case PARA_REG_DATA: 117 s->dataw = val; 118 parallel_update_irq(s); 119 break; 120 case PARA_REG_CTR: 121 val |= 0xc0; 122 if ((val & PARA_CTR_INIT) == 0 ) { 123 s->status = PARA_STS_BUSY; 124 s->status |= PARA_STS_ACK; 125 s->status |= PARA_STS_ONLINE; 126 s->status |= PARA_STS_ERROR; 127 } 128 else if (val & PARA_CTR_SELECT) { 129 if (val & PARA_CTR_STROBE) { 130 s->status &= ~PARA_STS_BUSY; 131 if ((s->control & PARA_CTR_STROBE) == 0) 132 qemu_chr_fe_write(s->chr, &s->dataw, 1); 133 } else { 134 if (s->control & PARA_CTR_INTEN) { 135 s->irq_pending = 1; 136 } 137 } 138 } 139 parallel_update_irq(s); 140 s->control = val; 141 break; 142 } 143 } 144 145 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) 146 { 147 ParallelState *s = opaque; 148 uint8_t parm = val; 149 int dir; 150 151 /* Sometimes programs do several writes for timing purposes on old 152 HW. Take care not to waste time on writes that do nothing. */ 153 154 s->last_read_offset = ~0U; 155 156 addr &= 7; 157 switch(addr) { 158 case PARA_REG_DATA: 159 if (s->dataw == val) 160 return; 161 pdebug("wd%02x\n", val); 162 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); 163 s->dataw = val; 164 break; 165 case PARA_REG_STS: 166 pdebug("ws%02x\n", val); 167 if (val & PARA_STS_TMOUT) 168 s->epp_timeout = 0; 169 break; 170 case PARA_REG_CTR: 171 val |= 0xc0; 172 if (s->control == val) 173 return; 174 pdebug("wc%02x\n", val); 175 176 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { 177 if (val & PARA_CTR_DIR) { 178 dir = 1; 179 } else { 180 dir = 0; 181 } 182 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); 183 parm &= ~PARA_CTR_DIR; 184 } 185 186 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); 187 s->control = val; 188 break; 189 case PARA_REG_EPP_ADDR: 190 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 191 /* Controls not correct for EPP address cycle, so do nothing */ 192 pdebug("wa%02x s\n", val); 193 else { 194 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 195 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { 196 s->epp_timeout = 1; 197 pdebug("wa%02x t\n", val); 198 } 199 else 200 pdebug("wa%02x\n", val); 201 } 202 break; 203 case PARA_REG_EPP_DATA: 204 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) 205 /* Controls not correct for EPP data cycle, so do nothing */ 206 pdebug("we%02x s\n", val); 207 else { 208 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; 209 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { 210 s->epp_timeout = 1; 211 pdebug("we%02x t\n", val); 212 } 213 else 214 pdebug("we%02x\n", val); 215 } 216 break; 217 } 218 } 219 220 static void 221 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) 222 { 223 ParallelState *s = opaque; 224 uint16_t eppdata = cpu_to_le16(val); 225 int err; 226 struct ParallelIOArg ioarg = { 227 .buffer = &eppdata, .count = sizeof(eppdata) 228 }; 229 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 230 /* Controls not correct for EPP data cycle, so do nothing */ 231 pdebug("we%04x s\n", val); 232 return; 233 } 234 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 235 if (err) { 236 s->epp_timeout = 1; 237 pdebug("we%04x t\n", val); 238 } 239 else 240 pdebug("we%04x\n", val); 241 } 242 243 static void 244 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) 245 { 246 ParallelState *s = opaque; 247 uint32_t eppdata = cpu_to_le32(val); 248 int err; 249 struct ParallelIOArg ioarg = { 250 .buffer = &eppdata, .count = sizeof(eppdata) 251 }; 252 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { 253 /* Controls not correct for EPP data cycle, so do nothing */ 254 pdebug("we%08x s\n", val); 255 return; 256 } 257 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); 258 if (err) { 259 s->epp_timeout = 1; 260 pdebug("we%08x t\n", val); 261 } 262 else 263 pdebug("we%08x\n", val); 264 } 265 266 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) 267 { 268 ParallelState *s = opaque; 269 uint32_t ret = 0xff; 270 271 addr &= 7; 272 switch(addr) { 273 case PARA_REG_DATA: 274 if (s->control & PARA_CTR_DIR) 275 ret = s->datar; 276 else 277 ret = s->dataw; 278 break; 279 case PARA_REG_STS: 280 ret = s->status; 281 s->irq_pending = 0; 282 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { 283 /* XXX Fixme: wait 5 microseconds */ 284 if (s->status & PARA_STS_ACK) 285 s->status &= ~PARA_STS_ACK; 286 else { 287 /* XXX Fixme: wait 5 microseconds */ 288 s->status |= PARA_STS_ACK; 289 s->status |= PARA_STS_BUSY; 290 } 291 } 292 parallel_update_irq(s); 293 break; 294 case PARA_REG_CTR: 295 ret = s->control; 296 break; 297 } 298 pdebug("read addr=0x%02x val=0x%02x\n", addr, ret); 299 return ret; 300 } 301 302 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) 303 { 304 ParallelState *s = opaque; 305 uint8_t ret = 0xff; 306 addr &= 7; 307 switch(addr) { 308 case PARA_REG_DATA: 309 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); 310 if (s->last_read_offset != addr || s->datar != ret) 311 pdebug("rd%02x\n", ret); 312 s->datar = ret; 313 break; 314 case PARA_REG_STS: 315 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); 316 ret &= ~PARA_STS_TMOUT; 317 if (s->epp_timeout) 318 ret |= PARA_STS_TMOUT; 319 if (s->last_read_offset != addr || s->status != ret) 320 pdebug("rs%02x\n", ret); 321 s->status = ret; 322 break; 323 case PARA_REG_CTR: 324 /* s->control has some bits fixed to 1. It is zero only when 325 it has not been yet written to. */ 326 if (s->control == 0) { 327 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); 328 if (s->last_read_offset != addr) 329 pdebug("rc%02x\n", ret); 330 s->control = ret; 331 } 332 else { 333 ret = s->control; 334 if (s->last_read_offset != addr) 335 pdebug("rc%02x\n", ret); 336 } 337 break; 338 case PARA_REG_EPP_ADDR: 339 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) 340 /* Controls not correct for EPP addr cycle, so do nothing */ 341 pdebug("ra%02x s\n", ret); 342 else { 343 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 344 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { 345 s->epp_timeout = 1; 346 pdebug("ra%02x t\n", ret); 347 } 348 else 349 pdebug("ra%02x\n", ret); 350 } 351 break; 352 case PARA_REG_EPP_DATA: 353 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) 354 /* Controls not correct for EPP data cycle, so do nothing */ 355 pdebug("re%02x s\n", ret); 356 else { 357 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; 358 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { 359 s->epp_timeout = 1; 360 pdebug("re%02x t\n", ret); 361 } 362 else 363 pdebug("re%02x\n", ret); 364 } 365 break; 366 } 367 s->last_read_offset = addr; 368 return ret; 369 } 370 371 static uint32_t 372 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) 373 { 374 ParallelState *s = opaque; 375 uint32_t ret; 376 uint16_t eppdata = ~0; 377 int err; 378 struct ParallelIOArg ioarg = { 379 .buffer = &eppdata, .count = sizeof(eppdata) 380 }; 381 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 382 /* Controls not correct for EPP data cycle, so do nothing */ 383 pdebug("re%04x s\n", eppdata); 384 return eppdata; 385 } 386 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 387 ret = le16_to_cpu(eppdata); 388 389 if (err) { 390 s->epp_timeout = 1; 391 pdebug("re%04x t\n", ret); 392 } 393 else 394 pdebug("re%04x\n", ret); 395 return ret; 396 } 397 398 static uint32_t 399 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) 400 { 401 ParallelState *s = opaque; 402 uint32_t ret; 403 uint32_t eppdata = ~0U; 404 int err; 405 struct ParallelIOArg ioarg = { 406 .buffer = &eppdata, .count = sizeof(eppdata) 407 }; 408 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { 409 /* Controls not correct for EPP data cycle, so do nothing */ 410 pdebug("re%08x s\n", eppdata); 411 return eppdata; 412 } 413 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); 414 ret = le32_to_cpu(eppdata); 415 416 if (err) { 417 s->epp_timeout = 1; 418 pdebug("re%08x t\n", ret); 419 } 420 else 421 pdebug("re%08x\n", ret); 422 return ret; 423 } 424 425 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) 426 { 427 pdebug("wecp%d=%02x\n", addr & 7, val); 428 } 429 430 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) 431 { 432 uint8_t ret = 0xff; 433 434 pdebug("recp%d:%02x\n", addr & 7, ret); 435 return ret; 436 } 437 438 static void parallel_reset(void *opaque) 439 { 440 ParallelState *s = opaque; 441 442 s->datar = ~0; 443 s->dataw = ~0; 444 s->status = PARA_STS_BUSY; 445 s->status |= PARA_STS_ACK; 446 s->status |= PARA_STS_ONLINE; 447 s->status |= PARA_STS_ERROR; 448 s->status |= PARA_STS_TMOUT; 449 s->control = PARA_CTR_SELECT; 450 s->control |= PARA_CTR_INIT; 451 s->control |= 0xc0; 452 s->irq_pending = 0; 453 s->hw_driver = 0; 454 s->epp_timeout = 0; 455 s->last_read_offset = ~0U; 456 } 457 458 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 459 460 static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { 461 { 0, 8, 1, 462 .read = parallel_ioport_read_hw, 463 .write = parallel_ioport_write_hw }, 464 { 4, 1, 2, 465 .read = parallel_ioport_eppdata_read_hw2, 466 .write = parallel_ioport_eppdata_write_hw2 }, 467 { 4, 1, 4, 468 .read = parallel_ioport_eppdata_read_hw4, 469 .write = parallel_ioport_eppdata_write_hw4 }, 470 { 0x400, 8, 1, 471 .read = parallel_ioport_ecp_read, 472 .write = parallel_ioport_ecp_write }, 473 PORTIO_END_OF_LIST(), 474 }; 475 476 static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { 477 { 0, 8, 1, 478 .read = parallel_ioport_read_sw, 479 .write = parallel_ioport_write_sw }, 480 PORTIO_END_OF_LIST(), 481 }; 482 483 484 static const VMStateDescription vmstate_parallel_isa = { 485 .name = "parallel_isa", 486 .version_id = 1, 487 .minimum_version_id = 1, 488 .fields = (VMStateField[]) { 489 VMSTATE_UINT8(state.dataw, ISAParallelState), 490 VMSTATE_UINT8(state.datar, ISAParallelState), 491 VMSTATE_UINT8(state.status, ISAParallelState), 492 VMSTATE_UINT8(state.control, ISAParallelState), 493 VMSTATE_INT32(state.irq_pending, ISAParallelState), 494 VMSTATE_INT32(state.epp_timeout, ISAParallelState), 495 VMSTATE_END_OF_LIST() 496 } 497 }; 498 499 500 static void parallel_isa_realizefn(DeviceState *dev, Error **errp) 501 { 502 static int index; 503 ISADevice *isadev = ISA_DEVICE(dev); 504 ISAParallelState *isa = ISA_PARALLEL(dev); 505 ParallelState *s = &isa->state; 506 int base; 507 uint8_t dummy; 508 509 if (!s->chr) { 510 error_setg(errp, "Can't create parallel device, empty char device"); 511 return; 512 } 513 514 if (isa->index == -1) { 515 isa->index = index; 516 } 517 if (isa->index >= MAX_PARALLEL_PORTS) { 518 error_setg(errp, "Max. supported number of parallel ports is %d.", 519 MAX_PARALLEL_PORTS); 520 return; 521 } 522 if (isa->iobase == -1) { 523 isa->iobase = isa_parallel_io[isa->index]; 524 } 525 index++; 526 527 base = isa->iobase; 528 isa_init_irq(isadev, &s->irq, isa->isairq); 529 qemu_register_reset(parallel_reset, s); 530 531 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { 532 s->hw_driver = 1; 533 s->status = dummy; 534 } 535 536 isa_register_portio_list(isadev, &s->portio_list, base, 537 (s->hw_driver 538 ? &isa_parallel_portio_hw_list[0] 539 : &isa_parallel_portio_sw_list[0]), 540 s, "parallel"); 541 } 542 543 /* Memory mapped interface */ 544 static uint32_t parallel_mm_readb (void *opaque, hwaddr addr) 545 { 546 ParallelState *s = opaque; 547 548 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; 549 } 550 551 static void parallel_mm_writeb (void *opaque, 552 hwaddr addr, uint32_t value) 553 { 554 ParallelState *s = opaque; 555 556 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF); 557 } 558 559 static uint32_t parallel_mm_readw (void *opaque, hwaddr addr) 560 { 561 ParallelState *s = opaque; 562 563 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; 564 } 565 566 static void parallel_mm_writew (void *opaque, 567 hwaddr addr, uint32_t value) 568 { 569 ParallelState *s = opaque; 570 571 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF); 572 } 573 574 static uint32_t parallel_mm_readl (void *opaque, hwaddr addr) 575 { 576 ParallelState *s = opaque; 577 578 return parallel_ioport_read_sw(s, addr >> s->it_shift); 579 } 580 581 static void parallel_mm_writel (void *opaque, 582 hwaddr addr, uint32_t value) 583 { 584 ParallelState *s = opaque; 585 586 parallel_ioport_write_sw(s, addr >> s->it_shift, value); 587 } 588 589 static const MemoryRegionOps parallel_mm_ops = { 590 .old_mmio = { 591 .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, 592 .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, 593 }, 594 .endianness = DEVICE_NATIVE_ENDIAN, 595 }; 596 597 /* If fd is zero, it means that the parallel device uses the console */ 598 bool parallel_mm_init(MemoryRegion *address_space, 599 hwaddr base, int it_shift, qemu_irq irq, 600 CharDriverState *chr) 601 { 602 ParallelState *s; 603 604 s = g_malloc0(sizeof(ParallelState)); 605 s->irq = irq; 606 s->chr = chr; 607 s->it_shift = it_shift; 608 qemu_register_reset(parallel_reset, s); 609 610 memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, 611 "parallel", 8 << it_shift); 612 memory_region_add_subregion(address_space, base, &s->iomem); 613 return true; 614 } 615 616 static Property parallel_isa_properties[] = { 617 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), 618 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), 619 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), 620 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), 621 DEFINE_PROP_END_OF_LIST(), 622 }; 623 624 static void parallel_isa_class_initfn(ObjectClass *klass, void *data) 625 { 626 DeviceClass *dc = DEVICE_CLASS(klass); 627 628 dc->realize = parallel_isa_realizefn; 629 dc->vmsd = &vmstate_parallel_isa; 630 dc->props = parallel_isa_properties; 631 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 632 } 633 634 static const TypeInfo parallel_isa_info = { 635 .name = TYPE_ISA_PARALLEL, 636 .parent = TYPE_ISA_DEVICE, 637 .instance_size = sizeof(ISAParallelState), 638 .class_init = parallel_isa_class_initfn, 639 }; 640 641 static void parallel_register_types(void) 642 { 643 type_register_static(¶llel_isa_info); 644 } 645 646 type_init(parallel_register_types) 647