1 /* 2 * Microchip PolarFire SoC MMUART emulation 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 or 12 * (at your option) version 3 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/log.h" 25 #include "chardev/char.h" 26 #include "hw/char/mchp_pfsoc_mmuart.h" 27 28 #define REGS_OFFSET 0x20 29 30 static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size) 31 { 32 MchpPfSoCMMUartState *s = opaque; 33 34 addr >>= 2; 35 if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) { 36 qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n", 37 __func__, addr << 2); 38 return 0; 39 } 40 41 return s->reg[addr]; 42 } 43 44 static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr, 45 uint64_t value, unsigned size) 46 { 47 MchpPfSoCMMUartState *s = opaque; 48 uint32_t val32 = (uint32_t)value; 49 50 addr >>= 2; 51 if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) { 52 qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx 53 " v=0x%x\n", __func__, addr << 2, val32); 54 return; 55 } 56 57 s->reg[addr] = val32; 58 } 59 60 static const MemoryRegionOps mchp_pfsoc_mmuart_ops = { 61 .read = mchp_pfsoc_mmuart_read, 62 .write = mchp_pfsoc_mmuart_write, 63 .endianness = DEVICE_LITTLE_ENDIAN, 64 .impl = { 65 .min_access_size = 4, 66 .max_access_size = 4, 67 }, 68 }; 69 70 MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, 71 hwaddr base, qemu_irq irq, Chardev *chr) 72 { 73 MchpPfSoCMMUartState *s; 74 75 s = g_new0(MchpPfSoCMMUartState, 1); 76 77 memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000); 78 79 memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, 80 "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET); 81 memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem); 82 83 s->base = base; 84 s->irq = irq; 85 86 s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr, 87 DEVICE_LITTLE_ENDIAN); 88 89 memory_region_add_subregion(sysmem, base, &s->container); 90 91 return s; 92 } 93