1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This is a `bare-bones' implementation of the IMX series serial ports. 13 * TODO: 14 * -- implement FIFOs. The real hardware has 32 word transmit 15 * and receive FIFOs; we currently use a 1-char buffer 16 * -- implement DMA 17 * -- implement BAUD-rate and modem lines, for when the backend 18 * is a real serial device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/char/imx_serial.h" 23 #include "hw/irq.h" 24 #include "hw/qdev-properties.h" 25 #include "hw/qdev-properties-system.h" 26 #include "migration/vmstate.h" 27 #include "qemu/log.h" 28 #include "qemu/module.h" 29 #include "qemu/fifo32.h" 30 #include "trace.h" 31 32 #ifndef DEBUG_IMX_UART 33 #define DEBUG_IMX_UART 0 34 #endif 35 36 #define DPRINTF(fmt, args...) \ 37 do { \ 38 if (DEBUG_IMX_UART) { \ 39 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ 40 __func__, ##args); \ 41 } \ 42 } while (0) 43 44 static const VMStateDescription vmstate_imx_serial = { 45 .name = TYPE_IMX_SERIAL, 46 .version_id = 3, 47 .minimum_version_id = 3, 48 .fields = (const VMStateField[]) { 49 VMSTATE_FIFO32(rx_fifo, IMXSerialState), 50 VMSTATE_TIMER(ageing_timer, IMXSerialState), 51 VMSTATE_UINT32(usr1, IMXSerialState), 52 VMSTATE_UINT32(usr2, IMXSerialState), 53 VMSTATE_UINT32(ucr1, IMXSerialState), 54 VMSTATE_UINT32(uts1, IMXSerialState), 55 VMSTATE_UINT32(onems, IMXSerialState), 56 VMSTATE_UINT32(ufcr, IMXSerialState), 57 VMSTATE_UINT32(ubmr, IMXSerialState), 58 VMSTATE_UINT32(ubrc, IMXSerialState), 59 VMSTATE_UINT32(ucr3, IMXSerialState), 60 VMSTATE_UINT32(ucr4, IMXSerialState), 61 VMSTATE_END_OF_LIST() 62 }, 63 }; 64 65 static void imx_update(IMXSerialState *s) 66 { 67 uint32_t usr1; 68 uint32_t usr2; 69 uint32_t mask; 70 71 /* 72 * Lucky for us TRDY and RRDY has the same offset in both USR1 and 73 * UCR1, so we can get away with something as simple as the 74 * following: 75 */ 76 usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); 77 /* 78 * Interrupt if AGTIM is set (ageing timer interrupt in RxFIFO) 79 */ 80 usr1 |= (s->ucr2 & UCR2_ATEN) ? (s->usr1 & USR1_AGTIM) : 0; 81 /* 82 * Bits that we want in USR2 are not as conveniently laid out, 83 * unfortunately. 84 */ 85 mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; 86 /* 87 * TCEN and TXDC are both bit 3 88 * ORE and OREN are both bit 1 89 * RDR and DREN are both bit 0 90 */ 91 mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN | UCR4_OREN); 92 93 usr2 = s->usr2 & mask; 94 95 qemu_set_irq(s->irq, usr1 || usr2); 96 } 97 98 static void imx_serial_rx_fifo_push(IMXSerialState *s, uint32_t value) 99 { 100 uint32_t pushed_value = value; 101 if (fifo32_is_full(&s->rx_fifo)) { 102 /* Set ORE if FIFO is already full */ 103 s->usr2 |= USR2_ORE; 104 } else { 105 if (fifo32_num_used(&s->rx_fifo) == FIFO_SIZE - 1) { 106 /* Set OVRRUN on 32nd character in FIFO */ 107 pushed_value |= URXD_ERR | URXD_OVRRUN; 108 } 109 fifo32_push(&s->rx_fifo, pushed_value); 110 } 111 } 112 113 static uint32_t imx_serial_rx_fifo_pop(IMXSerialState *s) 114 { 115 if (fifo32_is_empty(&s->rx_fifo)) { 116 return 0; 117 } 118 return fifo32_pop(&s->rx_fifo); 119 } 120 121 static void imx_serial_rx_fifo_ageing_timer_int(void *opaque) 122 { 123 IMXSerialState *s = (IMXSerialState *) opaque; 124 s->usr1 |= USR1_AGTIM; 125 imx_update(s); 126 } 127 128 static void imx_serial_rx_fifo_ageing_timer_restart(void *opaque) 129 { 130 /* 131 * Ageing timer starts ticking when 132 * RX FIFO is non empty and below trigger level. 133 * Timer is reset if new character is received or 134 * a FIFO read occurs. 135 * Timer triggers an interrupt when duration of 136 * 8 characters has passed (assuming 115200 baudrate). 137 */ 138 IMXSerialState *s = (IMXSerialState *) opaque; 139 140 if (!(s->usr1 & USR1_RRDY) && !(s->uts1 & UTS1_RXEMPTY)) { 141 timer_mod_ns(&s->ageing_timer, 142 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + AGE_DURATION_NS); 143 } else { 144 timer_del(&s->ageing_timer); 145 } 146 } 147 148 static void imx_serial_reset(IMXSerialState *s) 149 { 150 151 s->usr1 = USR1_TRDY | USR1_RXDS; 152 /* 153 * Fake attachment of a terminal: assert RTS. 154 */ 155 s->usr1 |= USR1_RTSS; 156 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 157 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 158 s->ucr1 = 0; 159 s->ucr2 = UCR2_SRST; 160 s->ucr3 = 0x700; 161 s->ubmr = 0; 162 s->ubrc = 4; 163 s->ufcr = BIT(11) | BIT(0); 164 165 fifo32_reset(&s->rx_fifo); 166 timer_del(&s->ageing_timer); 167 } 168 169 static void imx_serial_reset_at_boot(DeviceState *dev) 170 { 171 IMXSerialState *s = IMX_SERIAL(dev); 172 173 imx_serial_reset(s); 174 175 /* 176 * enable the uart on boot, so messages from the linux decompressor 177 * are visible. On real hardware this is done by the boot rom 178 * before anything else is loaded. 179 */ 180 s->ucr1 = UCR1_UARTEN; 181 s->ucr2 = UCR2_TXEN; 182 183 } 184 185 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 186 unsigned size) 187 { 188 IMXSerialState *s = (IMXSerialState *)opaque; 189 Chardev *chr = qemu_chr_fe_get_driver(&s->chr); 190 uint32_t c, rx_used; 191 uint8_t rxtl = s->ufcr & TL_MASK; 192 uint64_t value; 193 194 switch (offset >> 2) { 195 case 0x0: /* URXD */ 196 c = imx_serial_rx_fifo_pop(s); 197 if (!(s->uts1 & UTS1_RXEMPTY)) { 198 /* Character is valid */ 199 c |= URXD_CHARRDY; 200 rx_used = fifo32_num_used(&s->rx_fifo); 201 /* Clear RRDY if below threshold */ 202 if (rx_used < rxtl) { 203 s->usr1 &= ~USR1_RRDY; 204 } 205 if (rx_used == 0) { 206 s->usr2 &= ~USR2_RDR; 207 s->uts1 |= UTS1_RXEMPTY; 208 } 209 imx_update(s); 210 imx_serial_rx_fifo_ageing_timer_restart(s); 211 qemu_chr_fe_accept_input(&s->chr); 212 } 213 value = c; 214 break; 215 216 case 0x20: /* UCR1 */ 217 value = s->ucr1; 218 break; 219 220 case 0x21: /* UCR2 */ 221 value = s->ucr2; 222 break; 223 224 case 0x25: /* USR1 */ 225 value = s->usr1; 226 break; 227 228 case 0x26: /* USR2 */ 229 value = s->usr2; 230 break; 231 232 case 0x2A: /* BRM Modulator */ 233 value = s->ubmr; 234 break; 235 236 case 0x2B: /* Baud Rate Count */ 237 value = s->ubrc; 238 break; 239 240 case 0x2d: /* Test register */ 241 value = s->uts1; 242 break; 243 244 case 0x24: /* UFCR */ 245 value = s->ufcr; 246 break; 247 248 case 0x2c: 249 value = s->onems; 250 break; 251 252 case 0x22: /* UCR3 */ 253 value = s->ucr3; 254 break; 255 256 case 0x23: /* UCR4 */ 257 value = s->ucr4; 258 break; 259 260 case 0x29: /* BRM Incremental */ 261 value = 0x0; /* TODO */ 262 break; 263 264 default: 265 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 266 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 267 value = 0; 268 break; 269 } 270 271 trace_imx_serial_read(chr ? chr->label : "NODEV", offset, value); 272 273 return value; 274 } 275 276 static void imx_serial_write(void *opaque, hwaddr offset, 277 uint64_t value, unsigned size) 278 { 279 IMXSerialState *s = (IMXSerialState *)opaque; 280 Chardev *chr = qemu_chr_fe_get_driver(&s->chr); 281 unsigned char ch; 282 283 trace_imx_serial_write(chr ? chr->label : "NODEV", offset, value); 284 285 switch (offset >> 2) { 286 case 0x10: /* UTXD */ 287 ch = value; 288 if (s->ucr2 & UCR2_TXEN) { 289 /* XXX this blocks entire thread. Rewrite to use 290 * qemu_chr_fe_write and background I/O callbacks */ 291 qemu_chr_fe_write_all(&s->chr, &ch, 1); 292 s->usr1 &= ~USR1_TRDY; 293 s->usr2 &= ~USR2_TXDC; 294 imx_update(s); 295 s->usr1 |= USR1_TRDY; 296 s->usr2 |= USR2_TXDC; 297 imx_update(s); 298 } 299 break; 300 301 case 0x20: /* UCR1 */ 302 s->ucr1 = value & 0xffff; 303 304 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 305 306 imx_update(s); 307 break; 308 309 case 0x21: /* UCR2 */ 310 /* 311 * Only a few bits in control register 2 are implemented as yet. 312 * If it's intended to use a real serial device as a back-end, this 313 * register will have to be implemented more fully. 314 */ 315 if (!(value & UCR2_SRST)) { 316 imx_serial_reset(s); 317 imx_update(s); 318 value |= UCR2_SRST; 319 } 320 if (value & UCR2_RXEN) { 321 if (!(s->ucr2 & UCR2_RXEN)) { 322 qemu_chr_fe_accept_input(&s->chr); 323 } 324 } 325 s->ucr2 = value & 0xffff; 326 break; 327 328 case 0x25: /* USR1 */ 329 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 330 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 331 s->usr1 &= ~value; 332 break; 333 334 case 0x26: /* USR2 */ 335 /* 336 * Writing 1 to some bits clears them; all other 337 * values are ignored 338 */ 339 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 340 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 341 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 342 s->usr2 &= ~value; 343 break; 344 345 /* 346 * Linux expects to see what it writes to these registers 347 * We don't currently alter the baud rate 348 */ 349 case 0x29: /* UBIR */ 350 s->ubrc = value & 0xffff; 351 break; 352 353 case 0x2a: /* UBMR */ 354 s->ubmr = value & 0xffff; 355 break; 356 357 case 0x2c: /* One ms reg */ 358 s->onems = value & 0xffff; 359 break; 360 361 case 0x24: /* FIFO control register */ 362 s->ufcr = value & 0xffff; 363 break; 364 365 case 0x22: /* UCR3 */ 366 s->ucr3 = value & 0xffff; 367 break; 368 369 case 0x23: /* UCR4 */ 370 s->ucr4 = value & 0xffff; 371 imx_update(s); 372 break; 373 374 case 0x2d: /* UTS1 */ 375 qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" 376 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 377 /* TODO */ 378 break; 379 380 default: 381 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 382 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 383 } 384 } 385 386 static int imx_can_receive(void *opaque) 387 { 388 IMXSerialState *s = (IMXSerialState *)opaque; 389 return s->ucr2 & UCR2_RXEN && fifo32_num_used(&s->rx_fifo) < FIFO_SIZE; 390 } 391 392 static void imx_put_data(void *opaque, uint32_t value) 393 { 394 IMXSerialState *s = (IMXSerialState *)opaque; 395 Chardev *chr = qemu_chr_fe_get_driver(&s->chr); 396 uint8_t rxtl = s->ufcr & TL_MASK; 397 398 trace_imx_serial_put_data(chr ? chr->label : "NODEV", value); 399 400 imx_serial_rx_fifo_push(s, value); 401 if (fifo32_num_used(&s->rx_fifo) >= rxtl) { 402 s->usr1 |= USR1_RRDY; 403 } 404 s->usr2 |= USR2_RDR; 405 s->uts1 &= ~UTS1_RXEMPTY; 406 if (value & URXD_BRK) { 407 s->usr2 |= USR2_BRCD; 408 } 409 410 imx_serial_rx_fifo_ageing_timer_restart(s); 411 412 imx_update(s); 413 } 414 415 static void imx_receive(void *opaque, const uint8_t *buf, int size) 416 { 417 IMXSerialState *s = (IMXSerialState *)opaque; 418 419 s->usr2 |= USR2_WAKE; 420 imx_put_data(opaque, *buf); 421 } 422 423 static void imx_event(void *opaque, QEMUChrEvent event) 424 { 425 if (event == CHR_EVENT_BREAK) { 426 imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); 427 } 428 } 429 430 431 static const struct MemoryRegionOps imx_serial_ops = { 432 .read = imx_serial_read, 433 .write = imx_serial_write, 434 .endianness = DEVICE_NATIVE_ENDIAN, 435 }; 436 437 static void imx_serial_realize(DeviceState *dev, Error **errp) 438 { 439 IMXSerialState *s = IMX_SERIAL(dev); 440 441 fifo32_create(&s->rx_fifo, FIFO_SIZE); 442 timer_init_ns(&s->ageing_timer, QEMU_CLOCK_VIRTUAL, 443 imx_serial_rx_fifo_ageing_timer_int, s); 444 445 DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); 446 447 qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, 448 imx_event, NULL, s, NULL, true); 449 } 450 451 static void imx_serial_init(Object *obj) 452 { 453 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 454 IMXSerialState *s = IMX_SERIAL(obj); 455 456 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, 457 TYPE_IMX_SERIAL, 0x1000); 458 sysbus_init_mmio(sbd, &s->iomem); 459 sysbus_init_irq(sbd, &s->irq); 460 } 461 462 static const Property imx_serial_properties[] = { 463 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 464 }; 465 466 static void imx_serial_class_init(ObjectClass *klass, void *data) 467 { 468 DeviceClass *dc = DEVICE_CLASS(klass); 469 470 dc->realize = imx_serial_realize; 471 dc->vmsd = &vmstate_imx_serial; 472 device_class_set_legacy_reset(dc, imx_serial_reset_at_boot); 473 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 474 dc->desc = "i.MX series UART"; 475 device_class_set_props(dc, imx_serial_properties); 476 } 477 478 static const TypeInfo imx_serial_info = { 479 .name = TYPE_IMX_SERIAL, 480 .parent = TYPE_SYS_BUS_DEVICE, 481 .instance_size = sizeof(IMXSerialState), 482 .instance_init = imx_serial_init, 483 .class_init = imx_serial_class_init, 484 }; 485 486 static void imx_serial_register_types(void) 487 { 488 type_register_static(&imx_serial_info); 489 } 490 491 type_init(imx_serial_register_types) 492