1a7d2d98cSAlistair Francis /* 2a7d2d98cSAlistair Francis * QEMU lowRISC Ibex UART device 3a7d2d98cSAlistair Francis * 4a7d2d98cSAlistair Francis * Copyright (c) 2020 Western Digital 5a7d2d98cSAlistair Francis * 6a7d2d98cSAlistair Francis * For details check the documentation here: 7a7d2d98cSAlistair Francis * https://docs.opentitan.org/hw/ip/uart/doc/ 8a7d2d98cSAlistair Francis * 9a7d2d98cSAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 10a7d2d98cSAlistair Francis * of this software and associated documentation files (the "Software"), to deal 11a7d2d98cSAlistair Francis * in the Software without restriction, including without limitation the rights 12a7d2d98cSAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13a7d2d98cSAlistair Francis * copies of the Software, and to permit persons to whom the Software is 14a7d2d98cSAlistair Francis * furnished to do so, subject to the following conditions: 15a7d2d98cSAlistair Francis * 16a7d2d98cSAlistair Francis * The above copyright notice and this permission notice shall be included in 17a7d2d98cSAlistair Francis * all copies or substantial portions of the Software. 18a7d2d98cSAlistair Francis * 19a7d2d98cSAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20a7d2d98cSAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21a7d2d98cSAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22a7d2d98cSAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23a7d2d98cSAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24a7d2d98cSAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25a7d2d98cSAlistair Francis * THE SOFTWARE. 26a7d2d98cSAlistair Francis */ 27a7d2d98cSAlistair Francis 28a7d2d98cSAlistair Francis #include "qemu/osdep.h" 29a7d2d98cSAlistair Francis #include "hw/char/ibex_uart.h" 30a7d2d98cSAlistair Francis #include "hw/irq.h" 31940aabb9SAlistair Francis #include "hw/qdev-clock.h" 32a7d2d98cSAlistair Francis #include "hw/qdev-properties.h" 33ce35e229SEduardo Habkost #include "hw/qdev-properties-system.h" 34a7d2d98cSAlistair Francis #include "migration/vmstate.h" 35a7d2d98cSAlistair Francis #include "qemu/log.h" 36a7d2d98cSAlistair Francis #include "qemu/module.h" 37a7d2d98cSAlistair Francis 38a7d2d98cSAlistair Francis static void ibex_uart_update_irqs(IbexUartState *s) 39a7d2d98cSAlistair Francis { 4059093cc4SAlistair Francis if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) { 41a7d2d98cSAlistair Francis qemu_set_irq(s->tx_watermark, 1); 42a7d2d98cSAlistair Francis } else { 43a7d2d98cSAlistair Francis qemu_set_irq(s->tx_watermark, 0); 44a7d2d98cSAlistair Francis } 45a7d2d98cSAlistair Francis 4659093cc4SAlistair Francis if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) { 47a7d2d98cSAlistair Francis qemu_set_irq(s->rx_watermark, 1); 48a7d2d98cSAlistair Francis } else { 49a7d2d98cSAlistair Francis qemu_set_irq(s->rx_watermark, 0); 50a7d2d98cSAlistair Francis } 51a7d2d98cSAlistair Francis 5259093cc4SAlistair Francis if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) { 53a7d2d98cSAlistair Francis qemu_set_irq(s->tx_empty, 1); 54a7d2d98cSAlistair Francis } else { 55a7d2d98cSAlistair Francis qemu_set_irq(s->tx_empty, 0); 56a7d2d98cSAlistair Francis } 57a7d2d98cSAlistair Francis 5859093cc4SAlistair Francis if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) { 59a7d2d98cSAlistair Francis qemu_set_irq(s->rx_overflow, 1); 60a7d2d98cSAlistair Francis } else { 61a7d2d98cSAlistair Francis qemu_set_irq(s->rx_overflow, 0); 62a7d2d98cSAlistair Francis } 63a7d2d98cSAlistair Francis } 64a7d2d98cSAlistair Francis 65a7d2d98cSAlistair Francis static int ibex_uart_can_receive(void *opaque) 66a7d2d98cSAlistair Francis { 67a7d2d98cSAlistair Francis IbexUartState *s = opaque; 68a7d2d98cSAlistair Francis 69*82a4ed8eSAlexander Wagner if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) 70*82a4ed8eSAlexander Wagner && !(s->uart_status & R_STATUS_RXFULL_MASK)) { 71a7d2d98cSAlistair Francis return 1; 72a7d2d98cSAlistair Francis } 73a7d2d98cSAlistair Francis 74a7d2d98cSAlistair Francis return 0; 75a7d2d98cSAlistair Francis } 76a7d2d98cSAlistair Francis 77a7d2d98cSAlistair Francis static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size) 78a7d2d98cSAlistair Francis { 79a7d2d98cSAlistair Francis IbexUartState *s = opaque; 8059093cc4SAlistair Francis uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK) 8159093cc4SAlistair Francis >> R_FIFO_CTRL_RXILVL_SHIFT; 82a7d2d98cSAlistair Francis 83a7d2d98cSAlistair Francis s->uart_rdata = *buf; 84a7d2d98cSAlistair Francis 8559093cc4SAlistair Francis s->uart_status &= ~R_STATUS_RXIDLE_MASK; 8659093cc4SAlistair Francis s->uart_status &= ~R_STATUS_RXEMPTY_MASK; 87*82a4ed8eSAlexander Wagner /* The RXFULL is set after receiving a single byte 88*82a4ed8eSAlexander Wagner * as the FIFO buffers are not yet implemented. 89*82a4ed8eSAlexander Wagner */ 90*82a4ed8eSAlexander Wagner s->uart_status |= R_STATUS_RXFULL_MASK; 91*82a4ed8eSAlexander Wagner s->rx_level += 1; 92a7d2d98cSAlistair Francis 93a7d2d98cSAlistair Francis if (size > rx_fifo_level) { 9459093cc4SAlistair Francis s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK; 95a7d2d98cSAlistair Francis } 96a7d2d98cSAlistair Francis 97a7d2d98cSAlistair Francis ibex_uart_update_irqs(s); 98a7d2d98cSAlistair Francis } 99a7d2d98cSAlistair Francis 100a7d2d98cSAlistair Francis static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond, 101a7d2d98cSAlistair Francis void *opaque) 102a7d2d98cSAlistair Francis { 103a7d2d98cSAlistair Francis IbexUartState *s = opaque; 10459093cc4SAlistair Francis uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK) 10559093cc4SAlistair Francis >> R_FIFO_CTRL_TXILVL_SHIFT; 106a7d2d98cSAlistair Francis int ret; 107a7d2d98cSAlistair Francis 108a7d2d98cSAlistair Francis /* instant drain the fifo when there's no back-end */ 109a7d2d98cSAlistair Francis if (!qemu_chr_fe_backend_connected(&s->chr)) { 110a7d2d98cSAlistair Francis s->tx_level = 0; 111a7d2d98cSAlistair Francis return FALSE; 112a7d2d98cSAlistair Francis } 113a7d2d98cSAlistair Francis 114a7d2d98cSAlistair Francis if (!s->tx_level) { 11559093cc4SAlistair Francis s->uart_status &= ~R_STATUS_TXFULL_MASK; 11659093cc4SAlistair Francis s->uart_status |= R_STATUS_TXEMPTY_MASK; 11759093cc4SAlistair Francis s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; 11859093cc4SAlistair Francis s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; 119a7d2d98cSAlistair Francis ibex_uart_update_irqs(s); 120a7d2d98cSAlistair Francis return FALSE; 121a7d2d98cSAlistair Francis } 122a7d2d98cSAlistair Francis 123a7d2d98cSAlistair Francis ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); 124a7d2d98cSAlistair Francis 125a7d2d98cSAlistair Francis if (ret >= 0) { 126a7d2d98cSAlistair Francis s->tx_level -= ret; 127a7d2d98cSAlistair Francis memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level); 128a7d2d98cSAlistair Francis } 129a7d2d98cSAlistair Francis 130a7d2d98cSAlistair Francis if (s->tx_level) { 131a7d2d98cSAlistair Francis guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 132a7d2d98cSAlistair Francis ibex_uart_xmit, s); 133a7d2d98cSAlistair Francis if (!r) { 134a7d2d98cSAlistair Francis s->tx_level = 0; 135a7d2d98cSAlistair Francis return FALSE; 136a7d2d98cSAlistair Francis } 137a7d2d98cSAlistair Francis } 138a7d2d98cSAlistair Francis 139a7d2d98cSAlistair Francis /* Clear the TX Full bit */ 140a7d2d98cSAlistair Francis if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) { 14159093cc4SAlistair Francis s->uart_status &= ~R_STATUS_TXFULL_MASK; 142a7d2d98cSAlistair Francis } 143a7d2d98cSAlistair Francis 144a7d2d98cSAlistair Francis /* Disable the TX_WATERMARK IRQ */ 145a7d2d98cSAlistair Francis if (s->tx_level < tx_fifo_level) { 14659093cc4SAlistair Francis s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; 147a7d2d98cSAlistair Francis } 148a7d2d98cSAlistair Francis 149a7d2d98cSAlistair Francis /* Set TX empty */ 150a7d2d98cSAlistair Francis if (s->tx_level == 0) { 15159093cc4SAlistair Francis s->uart_status |= R_STATUS_TXEMPTY_MASK; 15259093cc4SAlistair Francis s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; 153a7d2d98cSAlistair Francis } 154a7d2d98cSAlistair Francis 155a7d2d98cSAlistair Francis ibex_uart_update_irqs(s); 156a7d2d98cSAlistair Francis return FALSE; 157a7d2d98cSAlistair Francis } 158a7d2d98cSAlistair Francis 159a7d2d98cSAlistair Francis static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf, 160a7d2d98cSAlistair Francis int size) 161a7d2d98cSAlistair Francis { 162a7d2d98cSAlistair Francis uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 16359093cc4SAlistair Francis uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK) 16459093cc4SAlistair Francis >> R_FIFO_CTRL_TXILVL_SHIFT; 165a7d2d98cSAlistair Francis 166a7d2d98cSAlistair Francis if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) { 167a7d2d98cSAlistair Francis size = IBEX_UART_TX_FIFO_SIZE - s->tx_level; 168a7d2d98cSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "ibex_uart: TX FIFO overflow"); 169a7d2d98cSAlistair Francis } 170a7d2d98cSAlistair Francis 171a7d2d98cSAlistair Francis memcpy(s->tx_fifo + s->tx_level, buf, size); 172a7d2d98cSAlistair Francis s->tx_level += size; 173a7d2d98cSAlistair Francis 174a7d2d98cSAlistair Francis if (s->tx_level > 0) { 17559093cc4SAlistair Francis s->uart_status &= ~R_STATUS_TXEMPTY_MASK; 176a7d2d98cSAlistair Francis } 177a7d2d98cSAlistair Francis 178a7d2d98cSAlistair Francis if (s->tx_level >= tx_fifo_level) { 17959093cc4SAlistair Francis s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK; 180a7d2d98cSAlistair Francis ibex_uart_update_irqs(s); 181a7d2d98cSAlistair Francis } 182a7d2d98cSAlistair Francis 183a7d2d98cSAlistair Francis if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) { 18459093cc4SAlistair Francis s->uart_status |= R_STATUS_TXFULL_MASK; 185a7d2d98cSAlistair Francis } 186a7d2d98cSAlistair Francis 187a7d2d98cSAlistair Francis timer_mod(s->fifo_trigger_handle, current_time + 188a7d2d98cSAlistair Francis (s->char_tx_time * 4)); 189a7d2d98cSAlistair Francis } 190a7d2d98cSAlistair Francis 191a7d2d98cSAlistair Francis static void ibex_uart_reset(DeviceState *dev) 192a7d2d98cSAlistair Francis { 193a7d2d98cSAlistair Francis IbexUartState *s = IBEX_UART(dev); 194a7d2d98cSAlistair Francis 195a7d2d98cSAlistair Francis s->uart_intr_state = 0x00000000; 196a7d2d98cSAlistair Francis s->uart_intr_state = 0x00000000; 197a7d2d98cSAlistair Francis s->uart_intr_enable = 0x00000000; 198a7d2d98cSAlistair Francis s->uart_ctrl = 0x00000000; 199a7d2d98cSAlistair Francis s->uart_status = 0x0000003c; 200a7d2d98cSAlistair Francis s->uart_rdata = 0x00000000; 201a7d2d98cSAlistair Francis s->uart_fifo_ctrl = 0x00000000; 202a7d2d98cSAlistair Francis s->uart_fifo_status = 0x00000000; 203a7d2d98cSAlistair Francis s->uart_ovrd = 0x00000000; 204a7d2d98cSAlistair Francis s->uart_val = 0x00000000; 205a7d2d98cSAlistair Francis s->uart_timeout_ctrl = 0x00000000; 206a7d2d98cSAlistair Francis 207a7d2d98cSAlistair Francis s->tx_level = 0; 208*82a4ed8eSAlexander Wagner s->rx_level = 0; 209a7d2d98cSAlistair Francis 210a7d2d98cSAlistair Francis s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10; 211a7d2d98cSAlistair Francis 212a7d2d98cSAlistair Francis ibex_uart_update_irqs(s); 213a7d2d98cSAlistair Francis } 214a7d2d98cSAlistair Francis 215940aabb9SAlistair Francis static uint64_t ibex_uart_get_baud(IbexUartState *s) 216940aabb9SAlistair Francis { 217940aabb9SAlistair Francis uint64_t baud; 218940aabb9SAlistair Francis 21959093cc4SAlistair Francis baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16); 220940aabb9SAlistair Francis baud *= clock_get_hz(s->f_clk); 221940aabb9SAlistair Francis baud >>= 20; 222940aabb9SAlistair Francis 223940aabb9SAlistair Francis return baud; 224940aabb9SAlistair Francis } 225940aabb9SAlistair Francis 226a7d2d98cSAlistair Francis static uint64_t ibex_uart_read(void *opaque, hwaddr addr, 227a7d2d98cSAlistair Francis unsigned int size) 228a7d2d98cSAlistair Francis { 229a7d2d98cSAlistair Francis IbexUartState *s = opaque; 230a7d2d98cSAlistair Francis uint64_t retvalue = 0; 231a7d2d98cSAlistair Francis 23259093cc4SAlistair Francis switch (addr >> 2) { 23359093cc4SAlistair Francis case R_INTR_STATE: 234a7d2d98cSAlistair Francis retvalue = s->uart_intr_state; 235a7d2d98cSAlistair Francis break; 23659093cc4SAlistair Francis case R_INTR_ENABLE: 237a7d2d98cSAlistair Francis retvalue = s->uart_intr_enable; 238a7d2d98cSAlistair Francis break; 23959093cc4SAlistair Francis case R_INTR_TEST: 240a7d2d98cSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 241a7d2d98cSAlistair Francis "%s: wdata is write only\n", __func__); 242a7d2d98cSAlistair Francis break; 243a7d2d98cSAlistair Francis 24459093cc4SAlistair Francis case R_CTRL: 245a7d2d98cSAlistair Francis retvalue = s->uart_ctrl; 246a7d2d98cSAlistair Francis break; 24759093cc4SAlistair Francis case R_STATUS: 248a7d2d98cSAlistair Francis retvalue = s->uart_status; 249a7d2d98cSAlistair Francis break; 250a7d2d98cSAlistair Francis 25159093cc4SAlistair Francis case R_RDATA: 252a7d2d98cSAlistair Francis retvalue = s->uart_rdata; 253*82a4ed8eSAlexander Wagner if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) { 254a7d2d98cSAlistair Francis qemu_chr_fe_accept_input(&s->chr); 255a7d2d98cSAlistair Francis 256*82a4ed8eSAlexander Wagner s->rx_level -= 1; 257*82a4ed8eSAlexander Wagner s->uart_status &= ~R_STATUS_RXFULL_MASK; 258*82a4ed8eSAlexander Wagner if (s->rx_level == 0) { 25959093cc4SAlistair Francis s->uart_status |= R_STATUS_RXIDLE_MASK; 26059093cc4SAlistair Francis s->uart_status |= R_STATUS_RXEMPTY_MASK; 261a7d2d98cSAlistair Francis } 262*82a4ed8eSAlexander Wagner } 263a7d2d98cSAlistair Francis break; 26459093cc4SAlistair Francis case R_WDATA: 265a7d2d98cSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 266a7d2d98cSAlistair Francis "%s: wdata is write only\n", __func__); 267a7d2d98cSAlistair Francis break; 268a7d2d98cSAlistair Francis 26959093cc4SAlistair Francis case R_FIFO_CTRL: 270a7d2d98cSAlistair Francis retvalue = s->uart_fifo_ctrl; 271a7d2d98cSAlistair Francis break; 27259093cc4SAlistair Francis case R_FIFO_STATUS: 273a7d2d98cSAlistair Francis retvalue = s->uart_fifo_status; 274a7d2d98cSAlistair Francis 275*82a4ed8eSAlexander Wagner retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT; 276*82a4ed8eSAlexander Wagner retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT; 277a7d2d98cSAlistair Francis 278a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 279a7d2d98cSAlistair Francis "%s: RX fifos are not supported\n", __func__); 280a7d2d98cSAlistair Francis break; 281a7d2d98cSAlistair Francis 28259093cc4SAlistair Francis case R_OVRD: 283a7d2d98cSAlistair Francis retvalue = s->uart_ovrd; 284a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 285a7d2d98cSAlistair Francis "%s: ovrd is not supported\n", __func__); 286a7d2d98cSAlistair Francis break; 28759093cc4SAlistair Francis case R_VAL: 288a7d2d98cSAlistair Francis retvalue = s->uart_val; 289a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 290a7d2d98cSAlistair Francis "%s: val is not supported\n", __func__); 291a7d2d98cSAlistair Francis break; 29259093cc4SAlistair Francis case R_TIMEOUT_CTRL: 293a7d2d98cSAlistair Francis retvalue = s->uart_timeout_ctrl; 294a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 295a7d2d98cSAlistair Francis "%s: timeout_ctrl is not supported\n", __func__); 296a7d2d98cSAlistair Francis break; 297a7d2d98cSAlistair Francis default: 298a7d2d98cSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 299a7d2d98cSAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 300a7d2d98cSAlistair Francis return 0; 301a7d2d98cSAlistair Francis } 302a7d2d98cSAlistair Francis 303a7d2d98cSAlistair Francis return retvalue; 304a7d2d98cSAlistair Francis } 305a7d2d98cSAlistair Francis 306a7d2d98cSAlistair Francis static void ibex_uart_write(void *opaque, hwaddr addr, 307a7d2d98cSAlistair Francis uint64_t val64, unsigned int size) 308a7d2d98cSAlistair Francis { 309a7d2d98cSAlistair Francis IbexUartState *s = opaque; 310a7d2d98cSAlistair Francis uint32_t value = val64; 311a7d2d98cSAlistair Francis 31259093cc4SAlistair Francis switch (addr >> 2) { 31359093cc4SAlistair Francis case R_INTR_STATE: 314a7d2d98cSAlistair Francis /* Write 1 clear */ 315a7d2d98cSAlistair Francis s->uart_intr_state &= ~value; 316a7d2d98cSAlistair Francis ibex_uart_update_irqs(s); 317a7d2d98cSAlistair Francis break; 31859093cc4SAlistair Francis case R_INTR_ENABLE: 319a7d2d98cSAlistair Francis s->uart_intr_enable = value; 320a7d2d98cSAlistair Francis ibex_uart_update_irqs(s); 321a7d2d98cSAlistair Francis break; 32259093cc4SAlistair Francis case R_INTR_TEST: 323a7d2d98cSAlistair Francis s->uart_intr_state |= value; 324a7d2d98cSAlistair Francis ibex_uart_update_irqs(s); 325a7d2d98cSAlistair Francis break; 326a7d2d98cSAlistair Francis 32759093cc4SAlistair Francis case R_CTRL: 328a7d2d98cSAlistair Francis s->uart_ctrl = value; 329a7d2d98cSAlistair Francis 33059093cc4SAlistair Francis if (value & R_CTRL_NF_MASK) { 331a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 332a7d2d98cSAlistair Francis "%s: UART_CTRL_NF is not supported\n", __func__); 333a7d2d98cSAlistair Francis } 33459093cc4SAlistair Francis if (value & R_CTRL_SLPBK_MASK) { 335a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 336a7d2d98cSAlistair Francis "%s: UART_CTRL_SLPBK is not supported\n", __func__); 337a7d2d98cSAlistair Francis } 33859093cc4SAlistair Francis if (value & R_CTRL_LLPBK_MASK) { 339a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 340a7d2d98cSAlistair Francis "%s: UART_CTRL_LLPBK is not supported\n", __func__); 341a7d2d98cSAlistair Francis } 34259093cc4SAlistair Francis if (value & R_CTRL_PARITY_EN_MASK) { 343a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 344a7d2d98cSAlistair Francis "%s: UART_CTRL_PARITY_EN is not supported\n", 345a7d2d98cSAlistair Francis __func__); 346a7d2d98cSAlistair Francis } 34759093cc4SAlistair Francis if (value & R_CTRL_PARITY_ODD_MASK) { 348a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 349a7d2d98cSAlistair Francis "%s: UART_CTRL_PARITY_ODD is not supported\n", 350a7d2d98cSAlistair Francis __func__); 351a7d2d98cSAlistair Francis } 35259093cc4SAlistair Francis if (value & R_CTRL_RXBLVL_MASK) { 353a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 354a7d2d98cSAlistair Francis "%s: UART_CTRL_RXBLVL is not supported\n", __func__); 355a7d2d98cSAlistair Francis } 35659093cc4SAlistair Francis if (value & R_CTRL_NCO_MASK) { 357940aabb9SAlistair Francis uint64_t baud = ibex_uart_get_baud(s); 358a7d2d98cSAlistair Francis 359a7d2d98cSAlistair Francis s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10; 360a7d2d98cSAlistair Francis } 361a7d2d98cSAlistair Francis break; 36259093cc4SAlistair Francis case R_STATUS: 363a7d2d98cSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 364a7d2d98cSAlistair Francis "%s: status is read only\n", __func__); 365a7d2d98cSAlistair Francis break; 366a7d2d98cSAlistair Francis 36759093cc4SAlistair Francis case R_RDATA: 368a7d2d98cSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 369a7d2d98cSAlistair Francis "%s: rdata is read only\n", __func__); 370a7d2d98cSAlistair Francis break; 37159093cc4SAlistair Francis case R_WDATA: 372a7d2d98cSAlistair Francis uart_write_tx_fifo(s, (uint8_t *) &value, 1); 373a7d2d98cSAlistair Francis break; 374a7d2d98cSAlistair Francis 37559093cc4SAlistair Francis case R_FIFO_CTRL: 376a7d2d98cSAlistair Francis s->uart_fifo_ctrl = value; 377a7d2d98cSAlistair Francis 37859093cc4SAlistair Francis if (value & R_FIFO_CTRL_RXRST_MASK) { 379*82a4ed8eSAlexander Wagner s->rx_level = 0; 380a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 381a7d2d98cSAlistair Francis "%s: RX fifos are not supported\n", __func__); 382a7d2d98cSAlistair Francis } 38359093cc4SAlistair Francis if (value & R_FIFO_CTRL_TXRST_MASK) { 384a7d2d98cSAlistair Francis s->tx_level = 0; 385a7d2d98cSAlistair Francis } 386a7d2d98cSAlistair Francis break; 38759093cc4SAlistair Francis case R_FIFO_STATUS: 388a7d2d98cSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 389a7d2d98cSAlistair Francis "%s: fifo_status is read only\n", __func__); 390a7d2d98cSAlistair Francis break; 391a7d2d98cSAlistair Francis 39259093cc4SAlistair Francis case R_OVRD: 393a7d2d98cSAlistair Francis s->uart_ovrd = value; 394a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 395a7d2d98cSAlistair Francis "%s: ovrd is not supported\n", __func__); 396a7d2d98cSAlistair Francis break; 39759093cc4SAlistair Francis case R_VAL: 398a7d2d98cSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 399a7d2d98cSAlistair Francis "%s: val is read only\n", __func__); 400a7d2d98cSAlistair Francis break; 40159093cc4SAlistair Francis case R_TIMEOUT_CTRL: 402a7d2d98cSAlistair Francis s->uart_timeout_ctrl = value; 403a7d2d98cSAlistair Francis qemu_log_mask(LOG_UNIMP, 404a7d2d98cSAlistair Francis "%s: timeout_ctrl is not supported\n", __func__); 405a7d2d98cSAlistair Francis break; 406a7d2d98cSAlistair Francis default: 407a7d2d98cSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 408a7d2d98cSAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 409a7d2d98cSAlistair Francis } 410a7d2d98cSAlistair Francis } 411a7d2d98cSAlistair Francis 4125ee0abedSPeter Maydell static void ibex_uart_clk_update(void *opaque, ClockEvent event) 413940aabb9SAlistair Francis { 414940aabb9SAlistair Francis IbexUartState *s = opaque; 415940aabb9SAlistair Francis 416940aabb9SAlistair Francis /* recompute uart's speed on clock change */ 417940aabb9SAlistair Francis uint64_t baud = ibex_uart_get_baud(s); 418940aabb9SAlistair Francis 419940aabb9SAlistair Francis s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10; 420940aabb9SAlistair Francis } 421940aabb9SAlistair Francis 422a7d2d98cSAlistair Francis static void fifo_trigger_update(void *opaque) 423a7d2d98cSAlistair Francis { 424a7d2d98cSAlistair Francis IbexUartState *s = opaque; 425a7d2d98cSAlistair Francis 42659093cc4SAlistair Francis if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) { 427a7d2d98cSAlistair Francis ibex_uart_xmit(NULL, G_IO_OUT, s); 428a7d2d98cSAlistair Francis } 429a7d2d98cSAlistair Francis } 430a7d2d98cSAlistair Francis 431a7d2d98cSAlistair Francis static const MemoryRegionOps ibex_uart_ops = { 432a7d2d98cSAlistair Francis .read = ibex_uart_read, 433a7d2d98cSAlistair Francis .write = ibex_uart_write, 434a7d2d98cSAlistair Francis .endianness = DEVICE_NATIVE_ENDIAN, 435a7d2d98cSAlistair Francis .impl.min_access_size = 4, 436a7d2d98cSAlistair Francis .impl.max_access_size = 4, 437a7d2d98cSAlistair Francis }; 438a7d2d98cSAlistair Francis 439a7d2d98cSAlistair Francis static int ibex_uart_post_load(void *opaque, int version_id) 440a7d2d98cSAlistair Francis { 441a7d2d98cSAlistair Francis IbexUartState *s = opaque; 442a7d2d98cSAlistair Francis 443a7d2d98cSAlistair Francis ibex_uart_update_irqs(s); 444a7d2d98cSAlistair Francis return 0; 445a7d2d98cSAlistair Francis } 446a7d2d98cSAlistair Francis 447a7d2d98cSAlistair Francis static const VMStateDescription vmstate_ibex_uart = { 448a7d2d98cSAlistair Francis .name = TYPE_IBEX_UART, 449a7d2d98cSAlistair Francis .version_id = 1, 450a7d2d98cSAlistair Francis .minimum_version_id = 1, 451a7d2d98cSAlistair Francis .post_load = ibex_uart_post_load, 452a7d2d98cSAlistair Francis .fields = (VMStateField[]) { 453a7d2d98cSAlistair Francis VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState, 454a7d2d98cSAlistair Francis IBEX_UART_TX_FIFO_SIZE), 455a7d2d98cSAlistair Francis VMSTATE_UINT32(tx_level, IbexUartState), 456a7d2d98cSAlistair Francis VMSTATE_UINT64(char_tx_time, IbexUartState), 457a7d2d98cSAlistair Francis VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexUartState), 458a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_intr_state, IbexUartState), 459a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_intr_enable, IbexUartState), 460a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_ctrl, IbexUartState), 461a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_status, IbexUartState), 462a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_rdata, IbexUartState), 463a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_fifo_ctrl, IbexUartState), 464a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_fifo_status, IbexUartState), 465a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_ovrd, IbexUartState), 466a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_val, IbexUartState), 467a7d2d98cSAlistair Francis VMSTATE_UINT32(uart_timeout_ctrl, IbexUartState), 468a7d2d98cSAlistair Francis VMSTATE_END_OF_LIST() 469a7d2d98cSAlistair Francis } 470a7d2d98cSAlistair Francis }; 471a7d2d98cSAlistair Francis 472a7d2d98cSAlistair Francis static Property ibex_uart_properties[] = { 473a7d2d98cSAlistair Francis DEFINE_PROP_CHR("chardev", IbexUartState, chr), 474a7d2d98cSAlistair Francis DEFINE_PROP_END_OF_LIST(), 475a7d2d98cSAlistair Francis }; 476a7d2d98cSAlistair Francis 477a7d2d98cSAlistair Francis static void ibex_uart_init(Object *obj) 478a7d2d98cSAlistair Francis { 479a7d2d98cSAlistair Francis IbexUartState *s = IBEX_UART(obj); 480a7d2d98cSAlistair Francis 481940aabb9SAlistair Francis s->f_clk = qdev_init_clock_in(DEVICE(obj), "f_clock", 4825ee0abedSPeter Maydell ibex_uart_clk_update, s, ClockUpdate); 483940aabb9SAlistair Francis clock_set_hz(s->f_clk, IBEX_UART_CLOCK); 484940aabb9SAlistair Francis 485a7d2d98cSAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark); 486a7d2d98cSAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark); 487a7d2d98cSAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty); 488a7d2d98cSAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow); 489a7d2d98cSAlistair Francis 490a7d2d98cSAlistair Francis memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s, 491a7d2d98cSAlistair Francis TYPE_IBEX_UART, 0x400); 492a7d2d98cSAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 493a7d2d98cSAlistair Francis } 494a7d2d98cSAlistair Francis 495a7d2d98cSAlistair Francis static void ibex_uart_realize(DeviceState *dev, Error **errp) 496a7d2d98cSAlistair Francis { 497a7d2d98cSAlistair Francis IbexUartState *s = IBEX_UART(dev); 498a7d2d98cSAlistair Francis 499a7d2d98cSAlistair Francis s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 500a7d2d98cSAlistair Francis fifo_trigger_update, s); 501a7d2d98cSAlistair Francis 502a7d2d98cSAlistair Francis qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive, 503a7d2d98cSAlistair Francis ibex_uart_receive, NULL, NULL, 504a7d2d98cSAlistair Francis s, NULL, true); 505a7d2d98cSAlistair Francis } 506a7d2d98cSAlistair Francis 507a7d2d98cSAlistair Francis static void ibex_uart_class_init(ObjectClass *klass, void *data) 508a7d2d98cSAlistair Francis { 509a7d2d98cSAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 510a7d2d98cSAlistair Francis 511a7d2d98cSAlistair Francis dc->reset = ibex_uart_reset; 512a7d2d98cSAlistair Francis dc->realize = ibex_uart_realize; 513a7d2d98cSAlistair Francis dc->vmsd = &vmstate_ibex_uart; 514a7d2d98cSAlistair Francis device_class_set_props(dc, ibex_uart_properties); 515a7d2d98cSAlistair Francis } 516a7d2d98cSAlistair Francis 517a7d2d98cSAlistair Francis static const TypeInfo ibex_uart_info = { 518a7d2d98cSAlistair Francis .name = TYPE_IBEX_UART, 519a7d2d98cSAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 520a7d2d98cSAlistair Francis .instance_size = sizeof(IbexUartState), 521a7d2d98cSAlistair Francis .instance_init = ibex_uart_init, 522a7d2d98cSAlistair Francis .class_init = ibex_uart_class_init, 523a7d2d98cSAlistair Francis }; 524a7d2d98cSAlistair Francis 525a7d2d98cSAlistair Francis static void ibex_uart_register_types(void) 526a7d2d98cSAlistair Francis { 527a7d2d98cSAlistair Francis type_register_static(&ibex_uart_info); 528a7d2d98cSAlistair Francis } 529a7d2d98cSAlistair Francis 530a7d2d98cSAlistair Francis type_init(ibex_uart_register_types) 531