1 /* 2 * Exynos4210 UART Emulation 3 * 4 * Copyright (C) 2011 Samsung Electronics Co Ltd. 5 * Maksim Kozlov, <m.kozlov@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "qemu/error-report.h" 26 #include "qemu/module.h" 27 #include "sysemu/sysemu.h" 28 #include "chardev/char-fe.h" 29 #include "chardev/char-serial.h" 30 31 #include "hw/arm/exynos4210.h" 32 #include "hw/irq.h" 33 #include "hw/qdev-properties.h" 34 35 #undef DEBUG_UART 36 #undef DEBUG_UART_EXTEND 37 #undef DEBUG_IRQ 38 #undef DEBUG_Rx_DATA 39 #undef DEBUG_Tx_DATA 40 41 #define DEBUG_UART 0 42 #define DEBUG_UART_EXTEND 0 43 #define DEBUG_IRQ 0 44 #define DEBUG_Rx_DATA 0 45 #define DEBUG_Tx_DATA 0 46 47 #if DEBUG_UART 48 #define PRINT_DEBUG(fmt, args...) \ 49 do { \ 50 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 51 } while (0) 52 53 #if DEBUG_UART_EXTEND 54 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 55 do { \ 56 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 57 } while (0) 58 #else 59 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 60 do {} while (0) 61 #endif /* EXTEND */ 62 63 #else 64 #define PRINT_DEBUG(fmt, args...) \ 65 do {} while (0) 66 #define PRINT_DEBUG_EXTEND(fmt, args...) \ 67 do {} while (0) 68 #endif 69 70 #define PRINT_ERROR(fmt, args...) \ 71 do { \ 72 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 73 } while (0) 74 75 /* 76 * Offsets for UART registers relative to SFR base address 77 * for UARTn 78 * 79 */ 80 #define ULCON 0x0000 /* Line Control */ 81 #define UCON 0x0004 /* Control */ 82 #define UFCON 0x0008 /* FIFO Control */ 83 #define UMCON 0x000C /* Modem Control */ 84 #define UTRSTAT 0x0010 /* Tx/Rx Status */ 85 #define UERSTAT 0x0014 /* UART Error Status */ 86 #define UFSTAT 0x0018 /* FIFO Status */ 87 #define UMSTAT 0x001C /* Modem Status */ 88 #define UTXH 0x0020 /* Transmit Buffer */ 89 #define URXH 0x0024 /* Receive Buffer */ 90 #define UBRDIV 0x0028 /* Baud Rate Divisor */ 91 #define UFRACVAL 0x002C /* Divisor Fractional Value */ 92 #define UINTP 0x0030 /* Interrupt Pending */ 93 #define UINTSP 0x0034 /* Interrupt Source Pending */ 94 #define UINTM 0x0038 /* Interrupt Mask */ 95 96 /* 97 * for indexing register in the uint32_t array 98 * 99 * 'reg' - register offset (see offsets definitions above) 100 * 101 */ 102 #define I_(reg) (reg / sizeof(uint32_t)) 103 104 typedef struct Exynos4210UartReg { 105 const char *name; /* the only reason is the debug output */ 106 hwaddr offset; 107 uint32_t reset_value; 108 } Exynos4210UartReg; 109 110 static const Exynos4210UartReg exynos4210_uart_regs[] = { 111 {"ULCON", ULCON, 0x00000000}, 112 {"UCON", UCON, 0x00003000}, 113 {"UFCON", UFCON, 0x00000000}, 114 {"UMCON", UMCON, 0x00000000}, 115 {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */ 116 {"UERSTAT", UERSTAT, 0x00000000}, /* RO */ 117 {"UFSTAT", UFSTAT, 0x00000000}, /* RO */ 118 {"UMSTAT", UMSTAT, 0x00000000}, /* RO */ 119 {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/ 120 {"URXH", URXH, 0x00000000}, /* RO */ 121 {"UBRDIV", UBRDIV, 0x00000000}, 122 {"UFRACVAL", UFRACVAL, 0x00000000}, 123 {"UINTP", UINTP, 0x00000000}, 124 {"UINTSP", UINTSP, 0x00000000}, 125 {"UINTM", UINTM, 0x00000000}, 126 }; 127 128 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C 129 130 /* UART FIFO Control */ 131 #define UFCON_FIFO_ENABLE 0x1 132 #define UFCON_Rx_FIFO_RESET 0x2 133 #define UFCON_Tx_FIFO_RESET 0x4 134 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 135 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) 136 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 137 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) 138 139 /* Uart FIFO Status */ 140 #define UFSTAT_Rx_FIFO_COUNT 0xff 141 #define UFSTAT_Rx_FIFO_FULL 0x100 142 #define UFSTAT_Rx_FIFO_ERROR 0x200 143 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 144 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) 145 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24 146 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) 147 148 /* UART Interrupt Source Pending */ 149 #define UINTSP_RXD 0x1 /* Receive interrupt */ 150 #define UINTSP_ERROR 0x2 /* Error interrupt */ 151 #define UINTSP_TXD 0x4 /* Transmit interrupt */ 152 #define UINTSP_MODEM 0x8 /* Modem interrupt */ 153 154 /* UART Line Control */ 155 #define ULCON_IR_MODE_SHIFT 6 156 #define ULCON_PARITY_SHIFT 3 157 #define ULCON_STOP_BIT_SHIFT 1 158 159 /* UART Tx/Rx Status */ 160 #define UTRSTAT_TRANSMITTER_EMPTY 0x4 161 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2 162 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 163 164 /* UART Error Status */ 165 #define UERSTAT_OVERRUN 0x1 166 #define UERSTAT_PARITY 0x2 167 #define UERSTAT_FRAME 0x4 168 #define UERSTAT_BREAK 0x8 169 170 typedef struct { 171 uint8_t *data; 172 uint32_t sp, rp; /* store and retrieve pointers */ 173 uint32_t size; 174 } Exynos4210UartFIFO; 175 176 #define TYPE_EXYNOS4210_UART "exynos4210.uart" 177 #define EXYNOS4210_UART(obj) \ 178 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART) 179 180 typedef struct Exynos4210UartState { 181 SysBusDevice parent_obj; 182 183 MemoryRegion iomem; 184 185 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; 186 Exynos4210UartFIFO rx; 187 Exynos4210UartFIFO tx; 188 189 CharBackend chr; 190 qemu_irq irq; 191 192 uint32_t channel; 193 194 } Exynos4210UartState; 195 196 197 #if DEBUG_UART 198 /* Used only for debugging inside PRINT_DEBUG_... macros */ 199 static const char *exynos4210_uart_regname(hwaddr offset) 200 { 201 202 int i; 203 204 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 205 if (offset == exynos4210_uart_regs[i].offset) { 206 return exynos4210_uart_regs[i].name; 207 } 208 } 209 210 return NULL; 211 } 212 #endif 213 214 215 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) 216 { 217 q->data[q->sp] = ch; 218 q->sp = (q->sp + 1) % q->size; 219 } 220 221 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q) 222 { 223 uint8_t ret = q->data[q->rp]; 224 q->rp = (q->rp + 1) % q->size; 225 return ret; 226 } 227 228 static int fifo_elements_number(const Exynos4210UartFIFO *q) 229 { 230 if (q->sp < q->rp) { 231 return q->size - q->rp + q->sp; 232 } 233 234 return q->sp - q->rp; 235 } 236 237 static int fifo_empty_elements_number(const Exynos4210UartFIFO *q) 238 { 239 return q->size - fifo_elements_number(q); 240 } 241 242 static void fifo_reset(Exynos4210UartFIFO *q) 243 { 244 g_free(q->data); 245 q->data = NULL; 246 247 q->data = (uint8_t *)g_malloc0(q->size); 248 249 q->sp = 0; 250 q->rp = 0; 251 } 252 253 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s) 254 { 255 uint32_t level = 0; 256 uint32_t reg; 257 258 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> 259 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; 260 261 switch (s->channel) { 262 case 0: 263 level = reg * 32; 264 break; 265 case 1: 266 case 4: 267 level = reg * 8; 268 break; 269 case 2: 270 case 3: 271 level = reg * 2; 272 break; 273 default: 274 level = 0; 275 PRINT_ERROR("Wrong UART channel number: %d\n", s->channel); 276 } 277 278 return level; 279 } 280 281 static void exynos4210_uart_update_irq(Exynos4210UartState *s) 282 { 283 /* 284 * The Tx interrupt is always requested if the number of data in the 285 * transmit FIFO is smaller than the trigger level. 286 */ 287 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 288 289 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> 290 UFSTAT_Tx_FIFO_COUNT_SHIFT; 291 292 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { 293 s->reg[I_(UINTSP)] |= UINTSP_TXD; 294 } 295 } 296 297 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; 298 299 if (s->reg[I_(UINTP)]) { 300 qemu_irq_raise(s->irq); 301 302 #if DEBUG_IRQ 303 fprintf(stderr, "UART%d: IRQ has been raised: %08x\n", 304 s->channel, s->reg[I_(UINTP)]); 305 #endif 306 307 } else { 308 qemu_irq_lower(s->irq); 309 } 310 } 311 312 static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 313 { 314 int speed, parity, data_bits, stop_bits; 315 QEMUSerialSetParams ssp; 316 uint64_t uclk_rate; 317 318 if (s->reg[I_(UBRDIV)] == 0) { 319 return; 320 } 321 322 if (s->reg[I_(ULCON)] & 0x20) { 323 if (s->reg[I_(ULCON)] & 0x28) { 324 parity = 'E'; 325 } else { 326 parity = 'O'; 327 } 328 } else { 329 parity = 'N'; 330 } 331 332 if (s->reg[I_(ULCON)] & 0x4) { 333 stop_bits = 2; 334 } else { 335 stop_bits = 1; 336 } 337 338 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; 339 340 uclk_rate = 24000000; 341 342 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + 343 (s->reg[I_(UFRACVAL)] & 0x7) + 16); 344 345 ssp.speed = speed; 346 ssp.parity = parity; 347 ssp.data_bits = data_bits; 348 ssp.stop_bits = stop_bits; 349 350 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 351 352 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n", 353 s->channel, speed, parity, data_bits, stop_bits); 354 } 355 356 static void exynos4210_uart_write(void *opaque, hwaddr offset, 357 uint64_t val, unsigned size) 358 { 359 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 360 uint8_t ch; 361 362 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel, 363 offset, exynos4210_uart_regname(offset), (long long unsigned int)val); 364 365 switch (offset) { 366 case ULCON: 367 case UBRDIV: 368 case UFRACVAL: 369 s->reg[I_(offset)] = val; 370 exynos4210_uart_update_parameters(s); 371 break; 372 case UFCON: 373 s->reg[I_(UFCON)] = val; 374 if (val & UFCON_Rx_FIFO_RESET) { 375 fifo_reset(&s->rx); 376 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; 377 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel); 378 } 379 if (val & UFCON_Tx_FIFO_RESET) { 380 fifo_reset(&s->tx); 381 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; 382 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel); 383 } 384 break; 385 386 case UTXH: 387 if (qemu_chr_fe_backend_connected(&s->chr)) { 388 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | 389 UTRSTAT_Tx_BUFFER_EMPTY); 390 ch = (uint8_t)val; 391 /* XXX this blocks entire thread. Rewrite to use 392 * qemu_chr_fe_write and background I/O callbacks */ 393 qemu_chr_fe_write_all(&s->chr, &ch, 1); 394 #if DEBUG_Tx_DATA 395 fprintf(stderr, "%c", ch); 396 #endif 397 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | 398 UTRSTAT_Tx_BUFFER_EMPTY; 399 s->reg[I_(UINTSP)] |= UINTSP_TXD; 400 exynos4210_uart_update_irq(s); 401 } 402 break; 403 404 case UINTP: 405 s->reg[I_(UINTP)] &= ~val; 406 s->reg[I_(UINTSP)] &= ~val; 407 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n", 408 s->channel, offset, s->reg[I_(UINTP)]); 409 exynos4210_uart_update_irq(s); 410 break; 411 case UTRSTAT: 412 case UERSTAT: 413 case UFSTAT: 414 case UMSTAT: 415 case URXH: 416 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n", 417 s->channel, exynos4210_uart_regname(offset), offset); 418 break; 419 case UINTSP: 420 s->reg[I_(UINTSP)] &= ~val; 421 break; 422 case UINTM: 423 s->reg[I_(UINTM)] = val; 424 exynos4210_uart_update_irq(s); 425 break; 426 case UCON: 427 case UMCON: 428 default: 429 s->reg[I_(offset)] = val; 430 break; 431 } 432 } 433 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, 434 unsigned size) 435 { 436 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 437 uint32_t res; 438 439 switch (offset) { 440 case UERSTAT: /* Read Only */ 441 res = s->reg[I_(UERSTAT)]; 442 s->reg[I_(UERSTAT)] = 0; 443 return res; 444 case UFSTAT: /* Read Only */ 445 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; 446 if (fifo_empty_elements_number(&s->rx) == 0) { 447 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; 448 s->reg[I_(UFSTAT)] &= ~0xff; 449 } 450 return s->reg[I_(UFSTAT)]; 451 case URXH: 452 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 453 if (fifo_elements_number(&s->rx)) { 454 res = fifo_retrieve(&s->rx); 455 #if DEBUG_Rx_DATA 456 fprintf(stderr, "%c", res); 457 #endif 458 if (!fifo_elements_number(&s->rx)) { 459 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 460 } else { 461 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 462 } 463 } else { 464 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 465 exynos4210_uart_update_irq(s); 466 res = 0; 467 } 468 } else { 469 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 470 res = s->reg[I_(URXH)]; 471 } 472 return res; 473 case UTXH: 474 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n", 475 s->channel, exynos4210_uart_regname(offset), offset); 476 break; 477 default: 478 return s->reg[I_(offset)]; 479 } 480 481 return 0; 482 } 483 484 static const MemoryRegionOps exynos4210_uart_ops = { 485 .read = exynos4210_uart_read, 486 .write = exynos4210_uart_write, 487 .endianness = DEVICE_NATIVE_ENDIAN, 488 .valid = { 489 .max_access_size = 4, 490 .unaligned = false 491 }, 492 }; 493 494 static int exynos4210_uart_can_receive(void *opaque) 495 { 496 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 497 498 return fifo_empty_elements_number(&s->rx); 499 } 500 501 502 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) 503 { 504 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 505 int i; 506 507 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 508 if (fifo_empty_elements_number(&s->rx) < size) { 509 for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) { 510 fifo_store(&s->rx, buf[i]); 511 } 512 s->reg[I_(UINTSP)] |= UINTSP_ERROR; 513 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 514 } else { 515 for (i = 0; i < size; i++) { 516 fifo_store(&s->rx, buf[i]); 517 } 518 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 519 } 520 /* XXX: Around here we maybe should check Rx trigger level */ 521 s->reg[I_(UINTSP)] |= UINTSP_RXD; 522 } else { 523 s->reg[I_(URXH)] = buf[0]; 524 s->reg[I_(UINTSP)] |= UINTSP_RXD; 525 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 526 } 527 528 exynos4210_uart_update_irq(s); 529 } 530 531 532 static void exynos4210_uart_event(void *opaque, int event) 533 { 534 Exynos4210UartState *s = (Exynos4210UartState *)opaque; 535 536 if (event == CHR_EVENT_BREAK) { 537 /* When the RxDn is held in logic 0, then a null byte is pushed into the 538 * fifo */ 539 fifo_store(&s->rx, '\0'); 540 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; 541 exynos4210_uart_update_irq(s); 542 } 543 } 544 545 546 static void exynos4210_uart_reset(DeviceState *dev) 547 { 548 Exynos4210UartState *s = EXYNOS4210_UART(dev); 549 int i; 550 551 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 552 s->reg[I_(exynos4210_uart_regs[i].offset)] = 553 exynos4210_uart_regs[i].reset_value; 554 } 555 556 fifo_reset(&s->rx); 557 fifo_reset(&s->tx); 558 559 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size); 560 } 561 562 static const VMStateDescription vmstate_exynos4210_uart_fifo = { 563 .name = "exynos4210.uart.fifo", 564 .version_id = 1, 565 .minimum_version_id = 1, 566 .fields = (VMStateField[]) { 567 VMSTATE_UINT32(sp, Exynos4210UartFIFO), 568 VMSTATE_UINT32(rp, Exynos4210UartFIFO), 569 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size), 570 VMSTATE_END_OF_LIST() 571 } 572 }; 573 574 static const VMStateDescription vmstate_exynos4210_uart = { 575 .name = "exynos4210.uart", 576 .version_id = 1, 577 .minimum_version_id = 1, 578 .fields = (VMStateField[]) { 579 VMSTATE_STRUCT(rx, Exynos4210UartState, 1, 580 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), 581 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, 582 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)), 583 VMSTATE_END_OF_LIST() 584 } 585 }; 586 587 DeviceState *exynos4210_uart_create(hwaddr addr, 588 int fifo_size, 589 int channel, 590 Chardev *chr, 591 qemu_irq irq) 592 { 593 DeviceState *dev; 594 SysBusDevice *bus; 595 596 dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); 597 598 qdev_prop_set_chr(dev, "chardev", chr); 599 qdev_prop_set_uint32(dev, "channel", channel); 600 qdev_prop_set_uint32(dev, "rx-size", fifo_size); 601 qdev_prop_set_uint32(dev, "tx-size", fifo_size); 602 603 bus = SYS_BUS_DEVICE(dev); 604 qdev_init_nofail(dev); 605 if (addr != (hwaddr)-1) { 606 sysbus_mmio_map(bus, 0, addr); 607 } 608 sysbus_connect_irq(bus, 0, irq); 609 610 return dev; 611 } 612 613 static void exynos4210_uart_init(Object *obj) 614 { 615 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 616 Exynos4210UartState *s = EXYNOS4210_UART(dev); 617 618 /* memory mapping */ 619 memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s, 620 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE); 621 sysbus_init_mmio(dev, &s->iomem); 622 623 sysbus_init_irq(dev, &s->irq); 624 } 625 626 static void exynos4210_uart_realize(DeviceState *dev, Error **errp) 627 { 628 Exynos4210UartState *s = EXYNOS4210_UART(dev); 629 630 qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive, 631 exynos4210_uart_receive, exynos4210_uart_event, 632 NULL, s, NULL, true); 633 } 634 635 static Property exynos4210_uart_properties[] = { 636 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr), 637 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), 638 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), 639 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), 640 DEFINE_PROP_END_OF_LIST(), 641 }; 642 643 static void exynos4210_uart_class_init(ObjectClass *klass, void *data) 644 { 645 DeviceClass *dc = DEVICE_CLASS(klass); 646 647 dc->realize = exynos4210_uart_realize; 648 dc->reset = exynos4210_uart_reset; 649 dc->props = exynos4210_uart_properties; 650 dc->vmsd = &vmstate_exynos4210_uart; 651 } 652 653 static const TypeInfo exynos4210_uart_info = { 654 .name = TYPE_EXYNOS4210_UART, 655 .parent = TYPE_SYS_BUS_DEVICE, 656 .instance_size = sizeof(Exynos4210UartState), 657 .instance_init = exynos4210_uart_init, 658 .class_init = exynos4210_uart_class_init, 659 }; 660 661 static void exynos4210_uart_register(void) 662 { 663 type_register_static(&exynos4210_uart_info); 664 } 665 666 type_init(exynos4210_uart_register) 667