1 /* 2 * HP Diva GSP controller 3 * 4 * The Diva PCI boards are Remote Management cards for PA-RISC machines. 5 * They come with built-in 16550A multi UARTs for serial consoles 6 * and a mailbox-like memory area for hardware auto-reboot functionality. 7 * GSP stands for "Guardian Service Processor". Later products were marketed 8 * "Management Processor" (MP). 9 * 10 * Diva cards are multifunctional cards. The first part, the aux port, 11 * is on physical machines not useable but we still try to mimic it here. 12 * 13 * SPDX-License-Identifier: GPL-2.0-or-later 14 * 15 * Copyright (c) 2025 Helge Deller <deller@gmx.de> 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/units.h" 20 #include "hw/char/serial.h" 21 #include "hw/irq.h" 22 #include "hw/pci/pci_device.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/qdev-properties-system.h" 25 #include "migration/vmstate.h" 26 27 #define PCI_DEVICE_ID_HP_DIVA 0x1048 28 /* various DIVA GSP cards: */ 29 #define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049 30 #define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A 31 #define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B 32 #define PCI_DEVICE_ID_HP_REO_IOC 0x10f1 33 #define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223 34 #define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226 35 #define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227 36 #define PCI_DEVICE_ID_HP_DIVA_EVEREST 0x1282 37 #define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290 38 #define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301 39 #define PCI_DEVICE_ID_HP_DIVA_HURRICANE 0x132a 40 41 42 #define PCI_SERIAL_MAX_PORTS 4 43 44 typedef struct PCIDivaSerialState { 45 PCIDevice dev; 46 MemoryRegion membar; /* for serial ports */ 47 MemoryRegion mailboxbar; /* for hardware mailbox */ 48 uint32_t subvendor; 49 uint32_t ports; 50 char *name[PCI_SERIAL_MAX_PORTS]; 51 SerialState state[PCI_SERIAL_MAX_PORTS]; 52 uint32_t level[PCI_SERIAL_MAX_PORTS]; 53 qemu_irq *irqs; 54 bool disable; 55 } PCIDivaSerialState; 56 57 static void diva_pci_exit(PCIDevice *dev) 58 { 59 PCIDivaSerialState *pci = DO_UPCAST(PCIDivaSerialState, dev, dev); 60 SerialState *s; 61 int i; 62 63 for (i = 0; i < pci->ports; i++) { 64 s = pci->state + i; 65 qdev_unrealize(DEVICE(s)); 66 memory_region_del_subregion(&pci->membar, &s->io); 67 g_free(pci->name[i]); 68 } 69 qemu_free_irqs(pci->irqs, pci->ports); 70 } 71 72 static void multi_serial_irq_mux(void *opaque, int n, int level) 73 { 74 PCIDivaSerialState *pci = opaque; 75 int i, pending = 0; 76 77 pci->level[n] = level; 78 for (i = 0; i < pci->ports; i++) { 79 if (pci->level[i]) { 80 pending = 1; 81 } 82 } 83 pci_set_irq(&pci->dev, pending); 84 } 85 86 struct diva_info { 87 unsigned int nports:4; /* number of serial ports */ 88 unsigned int omask:12; /* offset mask: BIT(1) -> offset 8 */ 89 }; 90 91 static struct diva_info diva_get_diva_info(PCIDeviceClass *pc) 92 { 93 switch (pc->subsystem_id) { 94 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 95 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 96 return (struct diva_info) { .nports = 1, 97 .omask = BIT(0) }; 98 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 99 return (struct diva_info) { .nports = 2, 100 .omask = BIT(0) | BIT(1) }; 101 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 102 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 103 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 104 return (struct diva_info) { .nports = 3, 105 .omask = BIT(0) | BIT(1) | BIT(2) }; 106 case PCI_DEVICE_ID_HP_DIVA_EVEREST: /* e.g. in rp3410 */ 107 return (struct diva_info) { .nports = 3, 108 .omask = BIT(0) | BIT(2) | BIT(7) }; 109 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 110 return (struct diva_info) { .nports = 4, 111 .omask = BIT(0) | BIT(1) | BIT(2) | BIT(7) }; 112 } 113 g_assert_not_reached(); 114 } 115 116 117 static void diva_pci_realize(PCIDevice *dev, Error **errp) 118 { 119 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 120 PCIDivaSerialState *pci = DO_UPCAST(PCIDivaSerialState, dev, dev); 121 SerialState *s; 122 struct diva_info di = diva_get_diva_info(pc); 123 size_t i, offset = 0; 124 size_t portmask = di.omask; 125 126 pci->dev.config[PCI_CLASS_PROG] = 2; /* 16550 compatible */ 127 pci->dev.config[PCI_INTERRUPT_PIN] = 1; 128 memory_region_init(&pci->membar, OBJECT(pci), "serial_ports", 4096); 129 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &pci->membar); 130 pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, di.nports); 131 132 for (i = 0; i < di.nports; i++) { 133 s = pci->state + i; 134 if (!qdev_realize(DEVICE(s), NULL, errp)) { 135 diva_pci_exit(dev); 136 return; 137 } 138 s->irq = pci->irqs[i]; 139 pci->name[i] = g_strdup_printf("uart #%zu", i + 1); 140 memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, 141 pci->name[i], 8); 142 143 /* calculate offset of given port based on bitmask */ 144 while ((portmask & BIT(0)) == 0) { 145 offset += 8; 146 portmask >>= 1; 147 } 148 memory_region_add_subregion(&pci->membar, offset, &s->io); 149 offset += 8; 150 portmask >>= 1; 151 pci->ports++; 152 } 153 154 /* mailbox bar */ 155 memory_region_init(&pci->mailboxbar, OBJECT(pci), "mailbox", 128 * KiB); 156 pci_register_bar(&pci->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY | 157 PCI_BASE_ADDRESS_MEM_PREFETCH, &pci->mailboxbar); 158 } 159 160 static const VMStateDescription vmstate_pci_diva = { 161 .name = "pci-diva-serial", 162 .version_id = 1, 163 .minimum_version_id = 1, 164 .fields = (const VMStateField[]) { 165 VMSTATE_PCI_DEVICE(dev, PCIDivaSerialState), 166 VMSTATE_STRUCT_ARRAY(state, PCIDivaSerialState, PCI_SERIAL_MAX_PORTS, 167 0, vmstate_serial, SerialState), 168 VMSTATE_UINT32_ARRAY(level, PCIDivaSerialState, PCI_SERIAL_MAX_PORTS), 169 VMSTATE_BOOL(disable, PCIDivaSerialState), 170 VMSTATE_END_OF_LIST() 171 } 172 }; 173 174 static const Property diva_serial_properties[] = { 175 DEFINE_PROP_BOOL("disable", PCIDivaSerialState, disable, false), 176 DEFINE_PROP_CHR("chardev1", PCIDivaSerialState, state[0].chr), 177 DEFINE_PROP_CHR("chardev2", PCIDivaSerialState, state[1].chr), 178 DEFINE_PROP_CHR("chardev3", PCIDivaSerialState, state[2].chr), 179 DEFINE_PROP_CHR("chardev4", PCIDivaSerialState, state[3].chr), 180 DEFINE_PROP_UINT32("subvendor", PCIDivaSerialState, subvendor, 181 PCI_DEVICE_ID_HP_DIVA_TOSCA1), 182 }; 183 184 static void diva_serial_class_initfn(ObjectClass *klass, const void *data) 185 { 186 DeviceClass *dc = DEVICE_CLASS(klass); 187 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 188 pc->realize = diva_pci_realize; 189 pc->exit = diva_pci_exit; 190 pc->vendor_id = PCI_VENDOR_ID_HP; 191 pc->device_id = PCI_DEVICE_ID_HP_DIVA; 192 pc->subsystem_vendor_id = PCI_VENDOR_ID_HP; 193 pc->subsystem_id = PCI_DEVICE_ID_HP_DIVA_TOSCA1; 194 pc->revision = 3; 195 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 196 dc->vmsd = &vmstate_pci_diva; 197 device_class_set_props(dc, diva_serial_properties); 198 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 199 } 200 201 static void diva_serial_init(Object *o) 202 { 203 PCIDevice *dev = PCI_DEVICE(o); 204 PCIDivaSerialState *pms = DO_UPCAST(PCIDivaSerialState, dev, dev); 205 struct diva_info di = diva_get_diva_info(PCI_DEVICE_GET_CLASS(dev)); 206 size_t i; 207 208 for (i = 0; i < di.nports; i++) { 209 object_initialize_child(o, "serial[*]", &pms->state[i], TYPE_SERIAL); 210 } 211 } 212 213 214 /* Diva-aux is the driver for portion 0 of the multifunction PCI device */ 215 216 struct DivaAuxState { 217 PCIDevice dev; 218 MemoryRegion mem; 219 qemu_irq irq; 220 }; 221 222 #define TYPE_DIVA_AUX "diva-aux" 223 OBJECT_DECLARE_SIMPLE_TYPE(DivaAuxState, DIVA_AUX) 224 225 static void diva_aux_realize(PCIDevice *dev, Error **errp) 226 { 227 DivaAuxState *pci = DO_UPCAST(DivaAuxState, dev, dev); 228 229 pci->dev.config[PCI_CLASS_PROG] = 0x02; 230 pci->dev.config[PCI_INTERRUPT_PIN] = 0x01; 231 pci->irq = pci_allocate_irq(&pci->dev); 232 233 memory_region_init(&pci->mem, OBJECT(pci), "mem", 16); 234 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &pci->mem); 235 } 236 237 static void diva_aux_exit(PCIDevice *dev) 238 { 239 DivaAuxState *pci = DO_UPCAST(DivaAuxState, dev, dev); 240 qemu_free_irq(pci->irq); 241 } 242 243 static void diva_aux_class_initfn(ObjectClass *klass, const void *data) 244 { 245 DeviceClass *dc = DEVICE_CLASS(klass); 246 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); 247 pc->realize = diva_aux_realize; 248 pc->exit = diva_aux_exit; 249 pc->vendor_id = PCI_VENDOR_ID_HP; 250 pc->device_id = PCI_DEVICE_ID_HP_DIVA_AUX; 251 pc->subsystem_vendor_id = PCI_VENDOR_ID_HP; 252 pc->subsystem_id = 0x1291; 253 pc->revision = 1; 254 pc->class_id = PCI_CLASS_COMMUNICATION_MULTISERIAL; 255 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 256 dc->user_creatable = false; 257 } 258 259 static void diva_aux_init(Object *o) 260 { 261 } 262 263 static const TypeInfo diva_aux_info = { 264 .name = TYPE_DIVA_AUX, 265 .parent = TYPE_PCI_DEVICE, 266 .instance_size = sizeof(DivaAuxState), 267 .instance_init = diva_aux_init, 268 .class_init = diva_aux_class_initfn, 269 .interfaces = (const InterfaceInfo[]) { 270 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 271 { }, 272 }, 273 }; 274 275 276 277 static const TypeInfo diva_serial_pci_info = { 278 .name = "diva-gsp", 279 .parent = TYPE_PCI_DEVICE, 280 .instance_size = sizeof(PCIDivaSerialState), 281 .instance_init = diva_serial_init, 282 .class_init = diva_serial_class_initfn, 283 .interfaces = (const InterfaceInfo[]) { 284 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 285 { }, 286 }, 287 }; 288 289 static void diva_pci_register_type(void) 290 { 291 type_register_static(&diva_serial_pci_info); 292 type_register_static(&diva_aux_info); 293 } 294 295 type_init(diva_pci_register_type) 296