1 /* 2 * Device model for Cadence UART 3 * 4 * Copyright (c) 2010 Xilinx Inc. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 6 * Copyright (c) 2012 PetaLogix Pty Ltd. 7 * Written by Haibing Ma 8 * M.Habib 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "hw/sysbus.h" 20 #include "sysemu/char.h" 21 #include "qemu/timer.h" 22 23 #ifdef CADENCE_UART_ERR_DEBUG 24 #define DB_PRINT(...) do { \ 25 fprintf(stderr, ": %s: ", __func__); \ 26 fprintf(stderr, ## __VA_ARGS__); \ 27 } while (0); 28 #else 29 #define DB_PRINT(...) 30 #endif 31 32 #define UART_SR_INTR_RTRIG 0x00000001 33 #define UART_SR_INTR_REMPTY 0x00000002 34 #define UART_SR_INTR_RFUL 0x00000004 35 #define UART_SR_INTR_TEMPTY 0x00000008 36 #define UART_SR_INTR_TFUL 0x00000010 37 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ 38 #define UART_SR_TTRIG 0x00002000 39 #define UART_INTR_TTRIG 0x00000400 40 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 41 * SR, then the same bit in CISR is set high too */ 42 #define UART_SR_TO_CISR_MASK 0x0000001F 43 44 #define UART_INTR_ROVR 0x00000020 45 #define UART_INTR_FRAME 0x00000040 46 #define UART_INTR_PARE 0x00000080 47 #define UART_INTR_TIMEOUT 0x00000100 48 #define UART_INTR_DMSI 0x00000200 49 #define UART_INTR_TOVR 0x00001000 50 51 #define UART_SR_RACTIVE 0x00000400 52 #define UART_SR_TACTIVE 0x00000800 53 #define UART_SR_FDELT 0x00001000 54 55 #define UART_CR_RXRST 0x00000001 56 #define UART_CR_TXRST 0x00000002 57 #define UART_CR_RX_EN 0x00000004 58 #define UART_CR_RX_DIS 0x00000008 59 #define UART_CR_TX_EN 0x00000010 60 #define UART_CR_TX_DIS 0x00000020 61 #define UART_CR_RST_TO 0x00000040 62 #define UART_CR_STARTBRK 0x00000080 63 #define UART_CR_STOPBRK 0x00000100 64 65 #define UART_MR_CLKS 0x00000001 66 #define UART_MR_CHRL 0x00000006 67 #define UART_MR_CHRL_SH 1 68 #define UART_MR_PAR 0x00000038 69 #define UART_MR_PAR_SH 3 70 #define UART_MR_NBSTOP 0x000000C0 71 #define UART_MR_NBSTOP_SH 6 72 #define UART_MR_CHMODE 0x00000300 73 #define UART_MR_CHMODE_SH 8 74 #define UART_MR_UCLKEN 0x00000400 75 #define UART_MR_IRMODE 0x00000800 76 77 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 78 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 79 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 80 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 81 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 82 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 83 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 84 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 85 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 86 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 87 88 #define CADENCE_UART_RX_FIFO_SIZE 16 89 #define CADENCE_UART_TX_FIFO_SIZE 16 90 #define UART_INPUT_CLK 50000000 91 92 #define R_CR (0x00/4) 93 #define R_MR (0x04/4) 94 #define R_IER (0x08/4) 95 #define R_IDR (0x0C/4) 96 #define R_IMR (0x10/4) 97 #define R_CISR (0x14/4) 98 #define R_BRGR (0x18/4) 99 #define R_RTOR (0x1C/4) 100 #define R_RTRIG (0x20/4) 101 #define R_MCR (0x24/4) 102 #define R_MSR (0x28/4) 103 #define R_SR (0x2C/4) 104 #define R_TX_RX (0x30/4) 105 #define R_BDIV (0x34/4) 106 #define R_FDEL (0x38/4) 107 #define R_PMIN (0x3C/4) 108 #define R_PWID (0x40/4) 109 #define R_TTRIG (0x44/4) 110 111 #define CADENCE_UART_R_MAX (0x48/4) 112 113 #define TYPE_CADENCE_UART "cadence_uart" 114 #define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \ 115 TYPE_CADENCE_UART) 116 117 typedef struct { 118 /*< private >*/ 119 SysBusDevice parent_obj; 120 /*< public >*/ 121 122 MemoryRegion iomem; 123 uint32_t r[CADENCE_UART_R_MAX]; 124 uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE]; 125 uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE]; 126 uint32_t rx_wpos; 127 uint32_t rx_count; 128 uint32_t tx_count; 129 uint64_t char_tx_time; 130 CharDriverState *chr; 131 qemu_irq irq; 132 QEMUTimer *fifo_trigger_handle; 133 } CadenceUARTState; 134 135 static void uart_update_status(CadenceUARTState *s) 136 { 137 s->r[R_SR] = 0; 138 139 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL 140 : 0; 141 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; 142 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; 143 144 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL 145 : 0; 146 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; 147 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; 148 149 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 150 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; 151 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 152 } 153 154 static void fifo_trigger_update(void *opaque) 155 { 156 CadenceUARTState *s = opaque; 157 158 s->r[R_CISR] |= UART_INTR_TIMEOUT; 159 160 uart_update_status(s); 161 } 162 163 static void uart_rx_reset(CadenceUARTState *s) 164 { 165 s->rx_wpos = 0; 166 s->rx_count = 0; 167 if (s->chr) { 168 qemu_chr_accept_input(s->chr); 169 } 170 } 171 172 static void uart_tx_reset(CadenceUARTState *s) 173 { 174 s->tx_count = 0; 175 } 176 177 static void uart_send_breaks(CadenceUARTState *s) 178 { 179 int break_enabled = 1; 180 181 if (s->chr) { 182 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 183 &break_enabled); 184 } 185 } 186 187 static void uart_parameters_setup(CadenceUARTState *s) 188 { 189 QEMUSerialSetParams ssp; 190 unsigned int baud_rate, packet_size; 191 192 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? 193 UART_INPUT_CLK / 8 : UART_INPUT_CLK; 194 195 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 196 packet_size = 1; 197 198 switch (s->r[R_MR] & UART_MR_PAR) { 199 case UART_PARITY_EVEN: 200 ssp.parity = 'E'; 201 packet_size++; 202 break; 203 case UART_PARITY_ODD: 204 ssp.parity = 'O'; 205 packet_size++; 206 break; 207 default: 208 ssp.parity = 'N'; 209 break; 210 } 211 212 switch (s->r[R_MR] & UART_MR_CHRL) { 213 case UART_DATA_BITS_6: 214 ssp.data_bits = 6; 215 break; 216 case UART_DATA_BITS_7: 217 ssp.data_bits = 7; 218 break; 219 default: 220 ssp.data_bits = 8; 221 break; 222 } 223 224 switch (s->r[R_MR] & UART_MR_NBSTOP) { 225 case UART_STOP_BITS_1: 226 ssp.stop_bits = 1; 227 break; 228 default: 229 ssp.stop_bits = 2; 230 break; 231 } 232 233 packet_size += ssp.data_bits + ssp.stop_bits; 234 s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size; 235 if (s->chr) { 236 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 237 } 238 } 239 240 static int uart_can_receive(void *opaque) 241 { 242 CadenceUARTState *s = opaque; 243 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); 244 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 245 246 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 247 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); 248 } 249 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 250 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count); 251 } 252 return ret; 253 } 254 255 static void uart_ctrl_update(CadenceUARTState *s) 256 { 257 if (s->r[R_CR] & UART_CR_TXRST) { 258 uart_tx_reset(s); 259 } 260 261 if (s->r[R_CR] & UART_CR_RXRST) { 262 uart_rx_reset(s); 263 } 264 265 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 266 267 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 268 uart_send_breaks(s); 269 } 270 } 271 272 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 273 { 274 CadenceUARTState *s = opaque; 275 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 276 int i; 277 278 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 279 return; 280 } 281 282 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) { 283 s->r[R_CISR] |= UART_INTR_ROVR; 284 } else { 285 for (i = 0; i < size; i++) { 286 s->rx_fifo[s->rx_wpos] = buf[i]; 287 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE; 288 s->rx_count++; 289 } 290 timer_mod(s->fifo_trigger_handle, new_rx_time + 291 (s->char_tx_time * 4)); 292 } 293 uart_update_status(s); 294 } 295 296 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 297 void *opaque) 298 { 299 CadenceUARTState *s = opaque; 300 int ret; 301 302 /* instant drain the fifo when there's no back-end */ 303 if (!s->chr) { 304 s->tx_count = 0; 305 return FALSE; 306 } 307 308 if (!s->tx_count) { 309 return FALSE; 310 } 311 312 ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count); 313 s->tx_count -= ret; 314 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); 315 316 if (s->tx_count) { 317 int r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP, 318 cadence_uart_xmit, s); 319 assert(r); 320 } 321 322 uart_update_status(s); 323 return FALSE; 324 } 325 326 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, 327 int size) 328 { 329 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 330 return; 331 } 332 333 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) { 334 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; 335 /* 336 * This can only be a guest error via a bad tx fifo register push, 337 * as can_receive() should stop remote loop and echo modes ever getting 338 * us to here. 339 */ 340 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow"); 341 s->r[R_CISR] |= UART_INTR_ROVR; 342 } 343 344 memcpy(s->tx_fifo + s->tx_count, buf, size); 345 s->tx_count += size; 346 347 cadence_uart_xmit(NULL, G_IO_OUT, s); 348 } 349 350 static void uart_receive(void *opaque, const uint8_t *buf, int size) 351 { 352 CadenceUARTState *s = opaque; 353 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 354 355 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 356 uart_write_rx_fifo(opaque, buf, size); 357 } 358 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 359 uart_write_tx_fifo(s, buf, size); 360 } 361 } 362 363 static void uart_event(void *opaque, int event) 364 { 365 CadenceUARTState *s = opaque; 366 uint8_t buf = '\0'; 367 368 if (event == CHR_EVENT_BREAK) { 369 uart_write_rx_fifo(opaque, &buf, 1); 370 } 371 372 uart_update_status(s); 373 } 374 375 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c) 376 { 377 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 378 return; 379 } 380 381 if (s->rx_count) { 382 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos - 383 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE; 384 *c = s->rx_fifo[rx_rpos]; 385 s->rx_count--; 386 387 if (s->chr) { 388 qemu_chr_accept_input(s->chr); 389 } 390 } else { 391 *c = 0; 392 } 393 394 uart_update_status(s); 395 } 396 397 static void uart_write(void *opaque, hwaddr offset, 398 uint64_t value, unsigned size) 399 { 400 CadenceUARTState *s = opaque; 401 402 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); 403 offset >>= 2; 404 switch (offset) { 405 case R_IER: /* ier (wts imr) */ 406 s->r[R_IMR] |= value; 407 break; 408 case R_IDR: /* idr (wtc imr) */ 409 s->r[R_IMR] &= ~value; 410 break; 411 case R_IMR: /* imr (read only) */ 412 break; 413 case R_CISR: /* cisr (wtc) */ 414 s->r[R_CISR] &= ~value; 415 break; 416 case R_TX_RX: /* UARTDR */ 417 switch (s->r[R_MR] & UART_MR_CHMODE) { 418 case NORMAL_MODE: 419 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 420 break; 421 case LOCAL_LOOPBACK: 422 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 423 break; 424 } 425 break; 426 default: 427 s->r[offset] = value; 428 } 429 430 switch (offset) { 431 case R_CR: 432 uart_ctrl_update(s); 433 break; 434 case R_MR: 435 uart_parameters_setup(s); 436 break; 437 } 438 uart_update_status(s); 439 } 440 441 static uint64_t uart_read(void *opaque, hwaddr offset, 442 unsigned size) 443 { 444 CadenceUARTState *s = opaque; 445 uint32_t c = 0; 446 447 offset >>= 2; 448 if (offset >= CADENCE_UART_R_MAX) { 449 c = 0; 450 } else if (offset == R_TX_RX) { 451 uart_read_rx_fifo(s, &c); 452 } else { 453 c = s->r[offset]; 454 } 455 456 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); 457 return c; 458 } 459 460 static const MemoryRegionOps uart_ops = { 461 .read = uart_read, 462 .write = uart_write, 463 .endianness = DEVICE_NATIVE_ENDIAN, 464 }; 465 466 static void cadence_uart_reset(DeviceState *dev) 467 { 468 CadenceUARTState *s = CADENCE_UART(dev); 469 470 s->r[R_CR] = 0x00000128; 471 s->r[R_IMR] = 0; 472 s->r[R_CISR] = 0; 473 s->r[R_RTRIG] = 0x00000020; 474 s->r[R_BRGR] = 0x0000000F; 475 s->r[R_TTRIG] = 0x00000020; 476 477 uart_rx_reset(s); 478 uart_tx_reset(s); 479 480 uart_update_status(s); 481 } 482 483 static void cadence_uart_realize(DeviceState *dev, Error **errp) 484 { 485 CadenceUARTState *s = CADENCE_UART(dev); 486 487 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 488 fifo_trigger_update, s); 489 490 /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */ 491 s->chr = qemu_char_get_next_serial(); 492 493 if (s->chr) { 494 qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive, 495 uart_event, s); 496 } 497 } 498 499 static void cadence_uart_init(Object *obj) 500 { 501 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 502 CadenceUARTState *s = CADENCE_UART(obj); 503 504 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 505 sysbus_init_mmio(sbd, &s->iomem); 506 sysbus_init_irq(sbd, &s->irq); 507 508 s->char_tx_time = (get_ticks_per_sec() / 9600) * 10; 509 } 510 511 static int cadence_uart_post_load(void *opaque, int version_id) 512 { 513 CadenceUARTState *s = opaque; 514 515 uart_parameters_setup(s); 516 uart_update_status(s); 517 return 0; 518 } 519 520 static const VMStateDescription vmstate_cadence_uart = { 521 .name = "cadence_uart", 522 .version_id = 2, 523 .minimum_version_id = 2, 524 .post_load = cadence_uart_post_load, 525 .fields = (VMStateField[]) { 526 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), 527 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState, 528 CADENCE_UART_RX_FIFO_SIZE), 529 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState, 530 CADENCE_UART_TX_FIFO_SIZE), 531 VMSTATE_UINT32(rx_count, CadenceUARTState), 532 VMSTATE_UINT32(tx_count, CadenceUARTState), 533 VMSTATE_UINT32(rx_wpos, CadenceUARTState), 534 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), 535 VMSTATE_END_OF_LIST() 536 } 537 }; 538 539 static void cadence_uart_class_init(ObjectClass *klass, void *data) 540 { 541 DeviceClass *dc = DEVICE_CLASS(klass); 542 543 dc->realize = cadence_uart_realize; 544 dc->vmsd = &vmstate_cadence_uart; 545 dc->reset = cadence_uart_reset; 546 /* Reason: realize() method uses qemu_char_get_next_serial() */ 547 dc->cannot_instantiate_with_device_add_yet = true; 548 } 549 550 static const TypeInfo cadence_uart_info = { 551 .name = TYPE_CADENCE_UART, 552 .parent = TYPE_SYS_BUS_DEVICE, 553 .instance_size = sizeof(CadenceUARTState), 554 .instance_init = cadence_uart_init, 555 .class_init = cadence_uart_class_init, 556 }; 557 558 static void cadence_uart_register_types(void) 559 { 560 type_register_static(&cadence_uart_info); 561 } 562 563 type_init(cadence_uart_register_types) 564