1 /* 2 * Device model for Cadence UART 3 * 4 * Reference: Xilinx Zynq 7000 reference manual 5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf 6 * - Chapter 19 UART Controller 7 * - Appendix B for Register details 8 * 9 * Copyright (c) 2010 Xilinx Inc. 10 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 11 * Copyright (c) 2012 PetaLogix Pty Ltd. 12 * Written by Haibing Ma 13 * M.Habib 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/sysbus.h" 26 #include "migration/vmstate.h" 27 #include "chardev/char-fe.h" 28 #include "chardev/char-serial.h" 29 #include "qemu/timer.h" 30 #include "qemu/log.h" 31 #include "qemu/module.h" 32 #include "hw/char/cadence_uart.h" 33 #include "hw/irq.h" 34 #include "hw/qdev-clock.h" 35 #include "hw/qdev-properties-system.h" 36 #include "trace.h" 37 38 #ifdef CADENCE_UART_ERR_DEBUG 39 #define DB_PRINT(...) do { \ 40 fprintf(stderr, ": %s: ", __func__); \ 41 fprintf(stderr, ## __VA_ARGS__); \ 42 } while (0) 43 #else 44 #define DB_PRINT(...) 45 #endif 46 47 #define UART_SR_INTR_RTRIG 0x00000001 48 #define UART_SR_INTR_REMPTY 0x00000002 49 #define UART_SR_INTR_RFUL 0x00000004 50 #define UART_SR_INTR_TEMPTY 0x00000008 51 #define UART_SR_INTR_TFUL 0x00000010 52 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ 53 #define UART_SR_TTRIG 0x00002000 54 #define UART_INTR_TTRIG 0x00000400 55 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 56 * SR, then the same bit in CISR is set high too */ 57 #define UART_SR_TO_CISR_MASK 0x0000001F 58 59 #define UART_INTR_ROVR 0x00000020 60 #define UART_INTR_FRAME 0x00000040 61 #define UART_INTR_PARE 0x00000080 62 #define UART_INTR_TIMEOUT 0x00000100 63 #define UART_INTR_DMSI 0x00000200 64 #define UART_INTR_TOVR 0x00001000 65 66 #define UART_SR_RACTIVE 0x00000400 67 #define UART_SR_TACTIVE 0x00000800 68 #define UART_SR_FDELT 0x00001000 69 70 #define UART_CR_RXRST 0x00000001 71 #define UART_CR_TXRST 0x00000002 72 #define UART_CR_RX_EN 0x00000004 73 #define UART_CR_RX_DIS 0x00000008 74 #define UART_CR_TX_EN 0x00000010 75 #define UART_CR_TX_DIS 0x00000020 76 #define UART_CR_RST_TO 0x00000040 77 #define UART_CR_STARTBRK 0x00000080 78 #define UART_CR_STOPBRK 0x00000100 79 80 #define UART_MR_CLKS 0x00000001 81 #define UART_MR_CHRL 0x00000006 82 #define UART_MR_CHRL_SH 1 83 #define UART_MR_PAR 0x00000038 84 #define UART_MR_PAR_SH 3 85 #define UART_MR_NBSTOP 0x000000C0 86 #define UART_MR_NBSTOP_SH 6 87 #define UART_MR_CHMODE 0x00000300 88 #define UART_MR_CHMODE_SH 8 89 #define UART_MR_UCLKEN 0x00000400 90 #define UART_MR_IRMODE 0x00000800 91 92 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 93 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 94 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 95 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 96 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 97 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 98 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 99 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 100 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 101 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 102 103 #define UART_DEFAULT_REF_CLK (50 * 1000 * 1000) 104 105 #define R_CR (0x00/4) 106 #define R_MR (0x04/4) 107 #define R_IER (0x08/4) 108 #define R_IDR (0x0C/4) 109 #define R_IMR (0x10/4) 110 #define R_CISR (0x14/4) 111 #define R_BRGR (0x18/4) 112 #define R_RTOR (0x1C/4) 113 #define R_RTRIG (0x20/4) 114 #define R_MCR (0x24/4) 115 #define R_MSR (0x28/4) 116 #define R_SR (0x2C/4) 117 #define R_TX_RX (0x30/4) 118 #define R_BDIV (0x34/4) 119 #define R_FDEL (0x38/4) 120 #define R_PMIN (0x3C/4) 121 #define R_PWID (0x40/4) 122 #define R_TTRIG (0x44/4) 123 124 125 static void uart_update_status(CadenceUARTState *s) 126 { 127 s->r[R_SR] = 0; 128 129 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL 130 : 0; 131 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; 132 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; 133 134 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL 135 : 0; 136 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; 137 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; 138 139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; 141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 142 } 143 144 static void fifo_trigger_update(void *opaque) 145 { 146 CadenceUARTState *s = opaque; 147 148 if (s->r[R_RTOR]) { 149 s->r[R_CISR] |= UART_INTR_TIMEOUT; 150 uart_update_status(s); 151 } 152 } 153 154 static void uart_rx_reset(CadenceUARTState *s) 155 { 156 s->rx_wpos = 0; 157 s->rx_count = 0; 158 qemu_chr_fe_accept_input(&s->chr); 159 } 160 161 static void uart_tx_reset(CadenceUARTState *s) 162 { 163 s->tx_count = 0; 164 } 165 166 static void uart_send_breaks(CadenceUARTState *s) 167 { 168 int break_enabled = 1; 169 170 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 171 &break_enabled); 172 } 173 174 static void uart_parameters_setup(CadenceUARTState *s) 175 { 176 QEMUSerialSetParams ssp; 177 unsigned int baud_rate, packet_size, input_clk; 178 input_clk = clock_get_hz(s->refclk); 179 180 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk; 181 baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 182 trace_cadence_uart_baudrate(baud_rate); 183 184 ssp.speed = baud_rate; 185 186 packet_size = 1; 187 188 switch (s->r[R_MR] & UART_MR_PAR) { 189 case UART_PARITY_EVEN: 190 ssp.parity = 'E'; 191 packet_size++; 192 break; 193 case UART_PARITY_ODD: 194 ssp.parity = 'O'; 195 packet_size++; 196 break; 197 default: 198 ssp.parity = 'N'; 199 break; 200 } 201 202 switch (s->r[R_MR] & UART_MR_CHRL) { 203 case UART_DATA_BITS_6: 204 ssp.data_bits = 6; 205 break; 206 case UART_DATA_BITS_7: 207 ssp.data_bits = 7; 208 break; 209 default: 210 ssp.data_bits = 8; 211 break; 212 } 213 214 switch (s->r[R_MR] & UART_MR_NBSTOP) { 215 case UART_STOP_BITS_1: 216 ssp.stop_bits = 1; 217 break; 218 default: 219 ssp.stop_bits = 2; 220 break; 221 } 222 223 packet_size += ssp.data_bits + ssp.stop_bits; 224 if (ssp.speed == 0) { 225 /* 226 * Avoid division-by-zero below. 227 * TODO: find something better 228 */ 229 ssp.speed = 1; 230 } 231 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; 232 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 233 } 234 235 static int uart_can_receive(void *opaque) 236 { 237 CadenceUARTState *s = opaque; 238 int ret; 239 uint32_t ch_mode; 240 241 /* ignore characters when unclocked or in reset */ 242 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { 243 return 0; 244 } 245 246 ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); 247 ch_mode = s->r[R_MR] & UART_MR_CHMODE; 248 249 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 250 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); 251 } 252 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 253 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count); 254 } 255 return ret; 256 } 257 258 static void uart_ctrl_update(CadenceUARTState *s) 259 { 260 if (s->r[R_CR] & UART_CR_TXRST) { 261 uart_tx_reset(s); 262 } 263 264 if (s->r[R_CR] & UART_CR_RXRST) { 265 uart_rx_reset(s); 266 } 267 268 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 269 270 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 271 uart_send_breaks(s); 272 } 273 } 274 275 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 276 { 277 CadenceUARTState *s = opaque; 278 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 279 int i; 280 281 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 282 return; 283 } 284 285 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) { 286 s->r[R_CISR] |= UART_INTR_ROVR; 287 } else { 288 for (i = 0; i < size; i++) { 289 s->rx_fifo[s->rx_wpos] = buf[i]; 290 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE; 291 s->rx_count++; 292 } 293 timer_mod(s->fifo_trigger_handle, new_rx_time + 294 (s->char_tx_time * 4)); 295 } 296 uart_update_status(s); 297 } 298 299 static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond, 300 void *opaque) 301 { 302 CadenceUARTState *s = opaque; 303 int ret; 304 305 /* instant drain the fifo when there's no back-end */ 306 if (!qemu_chr_fe_backend_connected(&s->chr)) { 307 s->tx_count = 0; 308 return FALSE; 309 } 310 311 if (!s->tx_count) { 312 return FALSE; 313 } 314 315 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); 316 317 if (ret >= 0) { 318 s->tx_count -= ret; 319 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); 320 } 321 322 if (s->tx_count) { 323 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 324 cadence_uart_xmit, s); 325 if (!r) { 326 s->tx_count = 0; 327 return FALSE; 328 } 329 } 330 331 uart_update_status(s); 332 return FALSE; 333 } 334 335 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, 336 int size) 337 { 338 /* ignore characters when unclocked or in reset */ 339 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { 340 return; 341 } 342 343 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 344 return; 345 } 346 347 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) { 348 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; 349 /* 350 * This can only be a guest error via a bad tx fifo register push, 351 * as can_receive() should stop remote loop and echo modes ever getting 352 * us to here. 353 */ 354 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow"); 355 s->r[R_CISR] |= UART_INTR_ROVR; 356 } 357 358 memcpy(s->tx_fifo + s->tx_count, buf, size); 359 s->tx_count += size; 360 361 cadence_uart_xmit(NULL, G_IO_OUT, s); 362 } 363 364 static void uart_receive(void *opaque, const uint8_t *buf, int size) 365 { 366 CadenceUARTState *s = opaque; 367 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 368 369 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 370 uart_write_rx_fifo(opaque, buf, size); 371 } 372 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 373 uart_write_tx_fifo(s, buf, size); 374 } 375 } 376 377 static void uart_event(void *opaque, QEMUChrEvent event) 378 { 379 CadenceUARTState *s = opaque; 380 uint8_t buf = '\0'; 381 382 /* ignore characters when unclocked or in reset */ 383 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { 384 return; 385 } 386 387 if (event == CHR_EVENT_BREAK) { 388 uart_write_rx_fifo(opaque, &buf, 1); 389 } 390 391 uart_update_status(s); 392 } 393 394 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c) 395 { 396 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 397 return; 398 } 399 400 if (s->rx_count) { 401 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos - 402 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE; 403 *c = s->rx_fifo[rx_rpos]; 404 s->rx_count--; 405 406 qemu_chr_fe_accept_input(&s->chr); 407 } else { 408 *c = 0; 409 } 410 411 uart_update_status(s); 412 } 413 414 static MemTxResult uart_write(void *opaque, hwaddr offset, 415 uint64_t value, unsigned size, MemTxAttrs attrs) 416 { 417 CadenceUARTState *s = opaque; 418 419 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); 420 offset >>= 2; 421 if (offset >= CADENCE_UART_R_MAX) { 422 return MEMTX_DECODE_ERROR; 423 } 424 switch (offset) { 425 case R_IER: /* ier (wts imr) */ 426 s->r[R_IMR] |= value; 427 break; 428 case R_IDR: /* idr (wtc imr) */ 429 s->r[R_IMR] &= ~value; 430 break; 431 case R_IMR: /* imr (read only) */ 432 break; 433 case R_CISR: /* cisr (wtc) */ 434 s->r[R_CISR] &= ~value; 435 break; 436 case R_TX_RX: /* UARTDR */ 437 switch (s->r[R_MR] & UART_MR_CHMODE) { 438 case NORMAL_MODE: 439 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 440 break; 441 case LOCAL_LOOPBACK: 442 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 443 break; 444 } 445 break; 446 case R_BRGR: /* Baud rate generator */ 447 if (value >= 0x01) { 448 s->r[offset] = value & 0xFFFF; 449 } 450 break; 451 case R_BDIV: /* Baud rate divider */ 452 if (value >= 0x04) { 453 s->r[offset] = value & 0xFF; 454 } 455 break; 456 default: 457 s->r[offset] = value; 458 } 459 460 switch (offset) { 461 case R_CR: 462 uart_ctrl_update(s); 463 break; 464 case R_MR: 465 uart_parameters_setup(s); 466 break; 467 } 468 uart_update_status(s); 469 470 return MEMTX_OK; 471 } 472 473 static MemTxResult uart_read(void *opaque, hwaddr offset, 474 uint64_t *value, unsigned size, MemTxAttrs attrs) 475 { 476 CadenceUARTState *s = opaque; 477 uint32_t c = 0; 478 479 offset >>= 2; 480 if (offset >= CADENCE_UART_R_MAX) { 481 return MEMTX_DECODE_ERROR; 482 } 483 if (offset == R_TX_RX) { 484 uart_read_rx_fifo(s, &c); 485 } else { 486 c = s->r[offset]; 487 } 488 489 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); 490 *value = c; 491 return MEMTX_OK; 492 } 493 494 static const MemoryRegionOps uart_ops = { 495 .read_with_attrs = uart_read, 496 .write_with_attrs = uart_write, 497 .endianness = DEVICE_NATIVE_ENDIAN, 498 }; 499 500 static void cadence_uart_reset_init(Object *obj, ResetType type) 501 { 502 CadenceUARTState *s = CADENCE_UART(obj); 503 504 s->r[R_CR] = 0x00000128; 505 s->r[R_IMR] = 0; 506 s->r[R_CISR] = 0; 507 s->r[R_RTRIG] = 0x00000020; 508 s->r[R_BRGR] = 0x0000028B; 509 s->r[R_BDIV] = 0x0000000F; 510 s->r[R_TTRIG] = 0x00000020; 511 } 512 513 static void cadence_uart_reset_hold(Object *obj) 514 { 515 CadenceUARTState *s = CADENCE_UART(obj); 516 517 uart_rx_reset(s); 518 uart_tx_reset(s); 519 520 uart_update_status(s); 521 } 522 523 static void cadence_uart_realize(DeviceState *dev, Error **errp) 524 { 525 CadenceUARTState *s = CADENCE_UART(dev); 526 527 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 528 fifo_trigger_update, s); 529 530 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, 531 uart_event, NULL, s, NULL, true); 532 } 533 534 static void cadence_uart_refclk_update(void *opaque, ClockEvent event) 535 { 536 CadenceUARTState *s = opaque; 537 538 /* recompute uart's speed on clock change */ 539 uart_parameters_setup(s); 540 } 541 542 static void cadence_uart_init(Object *obj) 543 { 544 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 545 CadenceUARTState *s = CADENCE_UART(obj); 546 547 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 548 sysbus_init_mmio(sbd, &s->iomem); 549 sysbus_init_irq(sbd, &s->irq); 550 551 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", 552 cadence_uart_refclk_update, s, ClockUpdate); 553 /* initialize the frequency in case the clock remains unconnected */ 554 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); 555 556 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; 557 } 558 559 static int cadence_uart_pre_load(void *opaque) 560 { 561 CadenceUARTState *s = opaque; 562 563 /* the frequency will be overriden if the refclk field is present */ 564 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); 565 return 0; 566 } 567 568 static int cadence_uart_post_load(void *opaque, int version_id) 569 { 570 CadenceUARTState *s = opaque; 571 572 /* Ensure these two aren't invalid numbers */ 573 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF || 574 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) { 575 /* Value is invalid, abort */ 576 return 1; 577 } 578 579 uart_parameters_setup(s); 580 uart_update_status(s); 581 return 0; 582 } 583 584 static const VMStateDescription vmstate_cadence_uart = { 585 .name = "cadence_uart", 586 .version_id = 3, 587 .minimum_version_id = 2, 588 .pre_load = cadence_uart_pre_load, 589 .post_load = cadence_uart_post_load, 590 .fields = (VMStateField[]) { 591 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), 592 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState, 593 CADENCE_UART_RX_FIFO_SIZE), 594 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState, 595 CADENCE_UART_TX_FIFO_SIZE), 596 VMSTATE_UINT32(rx_count, CadenceUARTState), 597 VMSTATE_UINT32(tx_count, CadenceUARTState), 598 VMSTATE_UINT32(rx_wpos, CadenceUARTState), 599 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), 600 VMSTATE_CLOCK_V(refclk, CadenceUARTState, 3), 601 VMSTATE_END_OF_LIST() 602 }, 603 }; 604 605 static Property cadence_uart_properties[] = { 606 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr), 607 DEFINE_PROP_END_OF_LIST(), 608 }; 609 610 static void cadence_uart_class_init(ObjectClass *klass, void *data) 611 { 612 DeviceClass *dc = DEVICE_CLASS(klass); 613 ResettableClass *rc = RESETTABLE_CLASS(klass); 614 615 dc->realize = cadence_uart_realize; 616 dc->vmsd = &vmstate_cadence_uart; 617 rc->phases.enter = cadence_uart_reset_init; 618 rc->phases.hold = cadence_uart_reset_hold; 619 device_class_set_props(dc, cadence_uart_properties); 620 } 621 622 static const TypeInfo cadence_uart_info = { 623 .name = TYPE_CADENCE_UART, 624 .parent = TYPE_SYS_BUS_DEVICE, 625 .instance_size = sizeof(CadenceUARTState), 626 .instance_init = cadence_uart_init, 627 .class_init = cadence_uart_class_init, 628 }; 629 630 static void cadence_uart_register_types(void) 631 { 632 type_register_static(&cadence_uart_info); 633 } 634 635 type_init(cadence_uart_register_types) 636