1 /* 2 * Device model for Cadence UART 3 * 4 * Copyright (c) 2010 Xilinx Inc. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 6 * Copyright (c) 2012 PetaLogix Pty Ltd. 7 * Written by Haibing Ma 8 * M.Habib 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "sysbus.h" 20 #include "qemu-char.h" 21 #include "qemu-timer.h" 22 23 #ifdef CADENCE_UART_ERR_DEBUG 24 #define DB_PRINT(...) do { \ 25 fprintf(stderr, ": %s: ", __func__); \ 26 fprintf(stderr, ## __VA_ARGS__); \ 27 } while (0); 28 #else 29 #define DB_PRINT(...) 30 #endif 31 32 #define UART_SR_INTR_RTRIG 0x00000001 33 #define UART_SR_INTR_REMPTY 0x00000002 34 #define UART_SR_INTR_RFUL 0x00000004 35 #define UART_SR_INTR_TEMPTY 0x00000008 36 #define UART_SR_INTR_TFUL 0x00000010 37 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 38 * SR, then the same bit in CISR is set high too */ 39 #define UART_SR_TO_CISR_MASK 0x0000001F 40 41 #define UART_INTR_ROVR 0x00000020 42 #define UART_INTR_FRAME 0x00000040 43 #define UART_INTR_PARE 0x00000080 44 #define UART_INTR_TIMEOUT 0x00000100 45 #define UART_INTR_DMSI 0x00000200 46 47 #define UART_SR_RACTIVE 0x00000400 48 #define UART_SR_TACTIVE 0x00000800 49 #define UART_SR_FDELT 0x00001000 50 51 #define UART_CR_RXRST 0x00000001 52 #define UART_CR_TXRST 0x00000002 53 #define UART_CR_RX_EN 0x00000004 54 #define UART_CR_RX_DIS 0x00000008 55 #define UART_CR_TX_EN 0x00000010 56 #define UART_CR_TX_DIS 0x00000020 57 #define UART_CR_RST_TO 0x00000040 58 #define UART_CR_STARTBRK 0x00000080 59 #define UART_CR_STOPBRK 0x00000100 60 61 #define UART_MR_CLKS 0x00000001 62 #define UART_MR_CHRL 0x00000006 63 #define UART_MR_CHRL_SH 1 64 #define UART_MR_PAR 0x00000038 65 #define UART_MR_PAR_SH 3 66 #define UART_MR_NBSTOP 0x000000C0 67 #define UART_MR_NBSTOP_SH 6 68 #define UART_MR_CHMODE 0x00000300 69 #define UART_MR_CHMODE_SH 8 70 #define UART_MR_UCLKEN 0x00000400 71 #define UART_MR_IRMODE 0x00000800 72 73 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 74 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 75 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 76 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 77 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 78 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 79 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 80 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 81 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 82 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 83 84 #define RX_FIFO_SIZE 16 85 #define TX_FIFO_SIZE 16 86 #define UART_INPUT_CLK 50000000 87 88 #define R_CR (0x00/4) 89 #define R_MR (0x04/4) 90 #define R_IER (0x08/4) 91 #define R_IDR (0x0C/4) 92 #define R_IMR (0x10/4) 93 #define R_CISR (0x14/4) 94 #define R_BRGR (0x18/4) 95 #define R_RTOR (0x1C/4) 96 #define R_RTRIG (0x20/4) 97 #define R_MCR (0x24/4) 98 #define R_MSR (0x28/4) 99 #define R_SR (0x2C/4) 100 #define R_TX_RX (0x30/4) 101 #define R_BDIV (0x34/4) 102 #define R_FDEL (0x38/4) 103 #define R_PMIN (0x3C/4) 104 #define R_PWID (0x40/4) 105 #define R_TTRIG (0x44/4) 106 107 #define R_MAX (R_TTRIG + 1) 108 109 typedef struct { 110 SysBusDevice busdev; 111 MemoryRegion iomem; 112 uint32_t r[R_MAX]; 113 uint8_t r_fifo[RX_FIFO_SIZE]; 114 uint32_t rx_wpos; 115 uint32_t rx_count; 116 uint64_t char_tx_time; 117 CharDriverState *chr; 118 qemu_irq irq; 119 struct QEMUTimer *fifo_trigger_handle; 120 struct QEMUTimer *tx_time_handle; 121 } UartState; 122 123 static void uart_update_status(UartState *s) 124 { 125 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 126 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 127 } 128 129 static void fifo_trigger_update(void *opaque) 130 { 131 UartState *s = (UartState *)opaque; 132 133 s->r[R_CISR] |= UART_INTR_TIMEOUT; 134 135 uart_update_status(s); 136 } 137 138 static void uart_tx_redo(UartState *s) 139 { 140 uint64_t new_tx_time = qemu_get_clock_ns(vm_clock); 141 142 qemu_mod_timer(s->tx_time_handle, new_tx_time + s->char_tx_time); 143 144 s->r[R_SR] |= UART_SR_INTR_TEMPTY; 145 146 uart_update_status(s); 147 } 148 149 static void uart_tx_write(void *opaque) 150 { 151 UartState *s = (UartState *)opaque; 152 153 uart_tx_redo(s); 154 } 155 156 static void uart_rx_reset(UartState *s) 157 { 158 s->rx_wpos = 0; 159 s->rx_count = 0; 160 161 s->r[R_SR] |= UART_SR_INTR_REMPTY; 162 s->r[R_SR] &= ~UART_SR_INTR_RFUL; 163 } 164 165 static void uart_tx_reset(UartState *s) 166 { 167 s->r[R_SR] |= UART_SR_INTR_TEMPTY; 168 s->r[R_SR] &= ~UART_SR_INTR_TFUL; 169 } 170 171 static void uart_send_breaks(UartState *s) 172 { 173 int break_enabled = 1; 174 175 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 176 &break_enabled); 177 } 178 179 static void uart_parameters_setup(UartState *s) 180 { 181 QEMUSerialSetParams ssp; 182 unsigned int baud_rate, packet_size; 183 184 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? 185 UART_INPUT_CLK / 8 : UART_INPUT_CLK; 186 187 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 188 packet_size = 1; 189 190 switch (s->r[R_MR] & UART_MR_PAR) { 191 case UART_PARITY_EVEN: 192 ssp.parity = 'E'; 193 packet_size++; 194 break; 195 case UART_PARITY_ODD: 196 ssp.parity = 'O'; 197 packet_size++; 198 break; 199 default: 200 ssp.parity = 'N'; 201 break; 202 } 203 204 switch (s->r[R_MR] & UART_MR_CHRL) { 205 case UART_DATA_BITS_6: 206 ssp.data_bits = 6; 207 break; 208 case UART_DATA_BITS_7: 209 ssp.data_bits = 7; 210 break; 211 default: 212 ssp.data_bits = 8; 213 break; 214 } 215 216 switch (s->r[R_MR] & UART_MR_NBSTOP) { 217 case UART_STOP_BITS_1: 218 ssp.stop_bits = 1; 219 break; 220 default: 221 ssp.stop_bits = 2; 222 break; 223 } 224 225 packet_size += ssp.data_bits + ssp.stop_bits; 226 s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size; 227 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 228 } 229 230 static int uart_can_receive(void *opaque) 231 { 232 UartState *s = (UartState *)opaque; 233 234 return RX_FIFO_SIZE - s->rx_count; 235 } 236 237 static void uart_ctrl_update(UartState *s) 238 { 239 if (s->r[R_CR] & UART_CR_TXRST) { 240 uart_tx_reset(s); 241 } 242 243 if (s->r[R_CR] & UART_CR_RXRST) { 244 uart_rx_reset(s); 245 } 246 247 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 248 249 if ((s->r[R_CR] & UART_CR_TX_EN) && !(s->r[R_CR] & UART_CR_TX_DIS)) { 250 uart_tx_redo(s); 251 } 252 253 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 254 uart_send_breaks(s); 255 } 256 } 257 258 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 259 { 260 UartState *s = (UartState *)opaque; 261 uint64_t new_rx_time = qemu_get_clock_ns(vm_clock); 262 int i; 263 264 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 265 return; 266 } 267 268 s->r[R_SR] &= ~UART_SR_INTR_REMPTY; 269 270 if (s->rx_count == RX_FIFO_SIZE) { 271 s->r[R_CISR] |= UART_INTR_ROVR; 272 } else { 273 for (i = 0; i < size; i++) { 274 s->r_fifo[s->rx_wpos] = buf[i]; 275 s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE; 276 s->rx_count++; 277 278 if (s->rx_count == RX_FIFO_SIZE) { 279 s->r[R_SR] |= UART_SR_INTR_RFUL; 280 break; 281 } 282 283 if (s->rx_count >= s->r[R_RTRIG]) { 284 s->r[R_SR] |= UART_SR_INTR_RTRIG; 285 } 286 } 287 qemu_mod_timer(s->fifo_trigger_handle, new_rx_time + 288 (s->char_tx_time * 4)); 289 } 290 uart_update_status(s); 291 } 292 293 static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size) 294 { 295 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 296 return; 297 } 298 299 while (size) { 300 size -= qemu_chr_fe_write(s->chr, buf, size); 301 } 302 } 303 304 static void uart_receive(void *opaque, const uint8_t *buf, int size) 305 { 306 UartState *s = (UartState *)opaque; 307 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 308 309 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 310 uart_write_rx_fifo(opaque, buf, size); 311 } 312 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 313 uart_write_tx_fifo(s, buf, size); 314 } 315 } 316 317 static void uart_event(void *opaque, int event) 318 { 319 UartState *s = (UartState *)opaque; 320 uint8_t buf = '\0'; 321 322 if (event == CHR_EVENT_BREAK) { 323 uart_write_rx_fifo(opaque, &buf, 1); 324 } 325 326 uart_update_status(s); 327 } 328 329 static void uart_read_rx_fifo(UartState *s, uint32_t *c) 330 { 331 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 332 return; 333 } 334 335 s->r[R_SR] &= ~UART_SR_INTR_RFUL; 336 337 if (s->rx_count) { 338 uint32_t rx_rpos = 339 (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE; 340 *c = s->r_fifo[rx_rpos]; 341 s->rx_count--; 342 343 if (!s->rx_count) { 344 s->r[R_SR] |= UART_SR_INTR_REMPTY; 345 } 346 } else { 347 *c = 0; 348 s->r[R_SR] |= UART_SR_INTR_REMPTY; 349 } 350 351 if (s->rx_count < s->r[R_RTRIG]) { 352 s->r[R_SR] &= ~UART_SR_INTR_RTRIG; 353 } 354 uart_update_status(s); 355 } 356 357 static void uart_write(void *opaque, target_phys_addr_t offset, 358 uint64_t value, unsigned size) 359 { 360 UartState *s = (UartState *)opaque; 361 362 DB_PRINT(" offset:%x data:%08x\n", offset, (unsigned)value); 363 offset >>= 2; 364 switch (offset) { 365 case R_IER: /* ier (wts imr) */ 366 s->r[R_IMR] |= value; 367 break; 368 case R_IDR: /* idr (wtc imr) */ 369 s->r[R_IMR] &= ~value; 370 break; 371 case R_IMR: /* imr (read only) */ 372 break; 373 case R_CISR: /* cisr (wtc) */ 374 s->r[R_CISR] &= ~value; 375 break; 376 case R_TX_RX: /* UARTDR */ 377 switch (s->r[R_MR] & UART_MR_CHMODE) { 378 case NORMAL_MODE: 379 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 380 break; 381 case LOCAL_LOOPBACK: 382 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 383 break; 384 } 385 break; 386 default: 387 s->r[offset] = value; 388 } 389 390 switch (offset) { 391 case R_CR: 392 uart_ctrl_update(s); 393 break; 394 case R_MR: 395 uart_parameters_setup(s); 396 break; 397 } 398 } 399 400 static uint64_t uart_read(void *opaque, target_phys_addr_t offset, 401 unsigned size) 402 { 403 UartState *s = (UartState *)opaque; 404 uint32_t c = 0; 405 406 offset >>= 2; 407 if (offset >= R_MAX) { 408 return 0; 409 } else if (offset == R_TX_RX) { 410 uart_read_rx_fifo(s, &c); 411 return c; 412 } 413 return s->r[offset]; 414 } 415 416 static const MemoryRegionOps uart_ops = { 417 .read = uart_read, 418 .write = uart_write, 419 .endianness = DEVICE_NATIVE_ENDIAN, 420 }; 421 422 static void cadence_uart_reset(UartState *s) 423 { 424 s->r[R_CR] = 0x00000128; 425 s->r[R_IMR] = 0; 426 s->r[R_CISR] = 0; 427 s->r[R_RTRIG] = 0x00000020; 428 s->r[R_BRGR] = 0x0000000F; 429 s->r[R_TTRIG] = 0x00000020; 430 431 uart_rx_reset(s); 432 uart_tx_reset(s); 433 434 s->rx_count = 0; 435 s->rx_wpos = 0; 436 } 437 438 static int cadence_uart_init(SysBusDevice *dev) 439 { 440 UartState *s = FROM_SYSBUS(UartState, dev); 441 442 memory_region_init_io(&s->iomem, &uart_ops, s, "uart", 0x1000); 443 sysbus_init_mmio(dev, &s->iomem); 444 sysbus_init_irq(dev, &s->irq); 445 446 s->fifo_trigger_handle = qemu_new_timer_ns(vm_clock, 447 (QEMUTimerCB *)fifo_trigger_update, s); 448 449 s->tx_time_handle = qemu_new_timer_ns(vm_clock, 450 (QEMUTimerCB *)uart_tx_write, s); 451 452 s->char_tx_time = (get_ticks_per_sec() / 9600) * 10; 453 454 s->chr = qemu_char_get_next_serial(); 455 456 cadence_uart_reset(s); 457 458 if (s->chr) { 459 qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive, 460 uart_event, s); 461 } 462 463 return 0; 464 } 465 466 static int cadence_uart_post_load(void *opaque, int version_id) 467 { 468 UartState *s = opaque; 469 470 uart_parameters_setup(s); 471 uart_update_status(s); 472 return 0; 473 } 474 475 static const VMStateDescription vmstate_cadence_uart = { 476 .name = "cadence_uart", 477 .version_id = 1, 478 .minimum_version_id = 1, 479 .minimum_version_id_old = 1, 480 .post_load = cadence_uart_post_load, 481 .fields = (VMStateField[]) { 482 VMSTATE_UINT32_ARRAY(r, UartState, R_MAX), 483 VMSTATE_UINT8_ARRAY(r_fifo, UartState, RX_FIFO_SIZE), 484 VMSTATE_UINT32(rx_count, UartState), 485 VMSTATE_UINT32(rx_wpos, UartState), 486 VMSTATE_TIMER(fifo_trigger_handle, UartState), 487 VMSTATE_TIMER(tx_time_handle, UartState), 488 VMSTATE_END_OF_LIST() 489 } 490 }; 491 492 static void cadence_uart_class_init(ObjectClass *klass, void *data) 493 { 494 DeviceClass *dc = DEVICE_CLASS(klass); 495 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 496 497 sdc->init = cadence_uart_init; 498 dc->vmsd = &vmstate_cadence_uart; 499 } 500 501 static TypeInfo cadence_uart_info = { 502 .name = "cadence_uart", 503 .parent = TYPE_SYS_BUS_DEVICE, 504 .instance_size = sizeof(UartState), 505 .class_init = cadence_uart_class_init, 506 }; 507 508 static void cadence_uart_register_types(void) 509 { 510 type_register_static(&cadence_uart_info); 511 } 512 513 type_init(cadence_uart_register_types) 514