1 /* 2 * Device model for Cadence UART 3 * 4 * Copyright (c) 2010 Xilinx Inc. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 6 * Copyright (c) 2012 PetaLogix Pty Ltd. 7 * Written by Haibing Ma 8 * M.Habib 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "hw/sysbus.h" 20 #include "sysemu/char.h" 21 #include "qemu/timer.h" 22 23 #ifdef CADENCE_UART_ERR_DEBUG 24 #define DB_PRINT(...) do { \ 25 fprintf(stderr, ": %s: ", __func__); \ 26 fprintf(stderr, ## __VA_ARGS__); \ 27 } while (0); 28 #else 29 #define DB_PRINT(...) 30 #endif 31 32 #define UART_SR_INTR_RTRIG 0x00000001 33 #define UART_SR_INTR_REMPTY 0x00000002 34 #define UART_SR_INTR_RFUL 0x00000004 35 #define UART_SR_INTR_TEMPTY 0x00000008 36 #define UART_SR_INTR_TFUL 0x00000010 37 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 38 * SR, then the same bit in CISR is set high too */ 39 #define UART_SR_TO_CISR_MASK 0x0000001F 40 41 #define UART_INTR_ROVR 0x00000020 42 #define UART_INTR_FRAME 0x00000040 43 #define UART_INTR_PARE 0x00000080 44 #define UART_INTR_TIMEOUT 0x00000100 45 #define UART_INTR_DMSI 0x00000200 46 47 #define UART_SR_RACTIVE 0x00000400 48 #define UART_SR_TACTIVE 0x00000800 49 #define UART_SR_FDELT 0x00001000 50 51 #define UART_CR_RXRST 0x00000001 52 #define UART_CR_TXRST 0x00000002 53 #define UART_CR_RX_EN 0x00000004 54 #define UART_CR_RX_DIS 0x00000008 55 #define UART_CR_TX_EN 0x00000010 56 #define UART_CR_TX_DIS 0x00000020 57 #define UART_CR_RST_TO 0x00000040 58 #define UART_CR_STARTBRK 0x00000080 59 #define UART_CR_STOPBRK 0x00000100 60 61 #define UART_MR_CLKS 0x00000001 62 #define UART_MR_CHRL 0x00000006 63 #define UART_MR_CHRL_SH 1 64 #define UART_MR_PAR 0x00000038 65 #define UART_MR_PAR_SH 3 66 #define UART_MR_NBSTOP 0x000000C0 67 #define UART_MR_NBSTOP_SH 6 68 #define UART_MR_CHMODE 0x00000300 69 #define UART_MR_CHMODE_SH 8 70 #define UART_MR_UCLKEN 0x00000400 71 #define UART_MR_IRMODE 0x00000800 72 73 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 74 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 75 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 76 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 77 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 78 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 79 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 80 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 81 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 82 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 83 84 #define RX_FIFO_SIZE 16 85 #define TX_FIFO_SIZE 16 86 #define UART_INPUT_CLK 50000000 87 88 #define R_CR (0x00/4) 89 #define R_MR (0x04/4) 90 #define R_IER (0x08/4) 91 #define R_IDR (0x0C/4) 92 #define R_IMR (0x10/4) 93 #define R_CISR (0x14/4) 94 #define R_BRGR (0x18/4) 95 #define R_RTOR (0x1C/4) 96 #define R_RTRIG (0x20/4) 97 #define R_MCR (0x24/4) 98 #define R_MSR (0x28/4) 99 #define R_SR (0x2C/4) 100 #define R_TX_RX (0x30/4) 101 #define R_BDIV (0x34/4) 102 #define R_FDEL (0x38/4) 103 #define R_PMIN (0x3C/4) 104 #define R_PWID (0x40/4) 105 #define R_TTRIG (0x44/4) 106 107 #define R_MAX (R_TTRIG + 1) 108 109 #define TYPE_CADENCE_UART "cadence_uart" 110 #define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART) 111 112 typedef struct { 113 /*< private >*/ 114 SysBusDevice parent_obj; 115 /*< public >*/ 116 117 MemoryRegion iomem; 118 uint32_t r[R_MAX]; 119 uint8_t r_fifo[RX_FIFO_SIZE]; 120 uint32_t rx_wpos; 121 uint32_t rx_count; 122 uint64_t char_tx_time; 123 CharDriverState *chr; 124 qemu_irq irq; 125 QEMUTimer *fifo_trigger_handle; 126 QEMUTimer *tx_time_handle; 127 } UartState; 128 129 static void uart_update_status(UartState *s) 130 { 131 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 132 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 133 } 134 135 static void fifo_trigger_update(void *opaque) 136 { 137 UartState *s = (UartState *)opaque; 138 139 s->r[R_CISR] |= UART_INTR_TIMEOUT; 140 141 uart_update_status(s); 142 } 143 144 static void uart_tx_redo(UartState *s) 145 { 146 uint64_t new_tx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 147 148 timer_mod(s->tx_time_handle, new_tx_time + s->char_tx_time); 149 150 s->r[R_SR] |= UART_SR_INTR_TEMPTY; 151 152 uart_update_status(s); 153 } 154 155 static void uart_tx_write(void *opaque) 156 { 157 UartState *s = (UartState *)opaque; 158 159 uart_tx_redo(s); 160 } 161 162 static void uart_rx_reset(UartState *s) 163 { 164 s->rx_wpos = 0; 165 s->rx_count = 0; 166 if (s->chr) { 167 qemu_chr_accept_input(s->chr); 168 } 169 170 s->r[R_SR] |= UART_SR_INTR_REMPTY; 171 s->r[R_SR] &= ~UART_SR_INTR_RFUL; 172 } 173 174 static void uart_tx_reset(UartState *s) 175 { 176 s->r[R_SR] |= UART_SR_INTR_TEMPTY; 177 s->r[R_SR] &= ~UART_SR_INTR_TFUL; 178 } 179 180 static void uart_send_breaks(UartState *s) 181 { 182 int break_enabled = 1; 183 184 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 185 &break_enabled); 186 } 187 188 static void uart_parameters_setup(UartState *s) 189 { 190 QEMUSerialSetParams ssp; 191 unsigned int baud_rate, packet_size; 192 193 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? 194 UART_INPUT_CLK / 8 : UART_INPUT_CLK; 195 196 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 197 packet_size = 1; 198 199 switch (s->r[R_MR] & UART_MR_PAR) { 200 case UART_PARITY_EVEN: 201 ssp.parity = 'E'; 202 packet_size++; 203 break; 204 case UART_PARITY_ODD: 205 ssp.parity = 'O'; 206 packet_size++; 207 break; 208 default: 209 ssp.parity = 'N'; 210 break; 211 } 212 213 switch (s->r[R_MR] & UART_MR_CHRL) { 214 case UART_DATA_BITS_6: 215 ssp.data_bits = 6; 216 break; 217 case UART_DATA_BITS_7: 218 ssp.data_bits = 7; 219 break; 220 default: 221 ssp.data_bits = 8; 222 break; 223 } 224 225 switch (s->r[R_MR] & UART_MR_NBSTOP) { 226 case UART_STOP_BITS_1: 227 ssp.stop_bits = 1; 228 break; 229 default: 230 ssp.stop_bits = 2; 231 break; 232 } 233 234 packet_size += ssp.data_bits + ssp.stop_bits; 235 s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size; 236 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 237 } 238 239 static int uart_can_receive(void *opaque) 240 { 241 UartState *s = (UartState *)opaque; 242 243 return RX_FIFO_SIZE - s->rx_count; 244 } 245 246 static void uart_ctrl_update(UartState *s) 247 { 248 if (s->r[R_CR] & UART_CR_TXRST) { 249 uart_tx_reset(s); 250 } 251 252 if (s->r[R_CR] & UART_CR_RXRST) { 253 uart_rx_reset(s); 254 } 255 256 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 257 258 if ((s->r[R_CR] & UART_CR_TX_EN) && !(s->r[R_CR] & UART_CR_TX_DIS)) { 259 uart_tx_redo(s); 260 } 261 262 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 263 uart_send_breaks(s); 264 } 265 } 266 267 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 268 { 269 UartState *s = (UartState *)opaque; 270 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 271 int i; 272 273 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 274 return; 275 } 276 277 s->r[R_SR] &= ~UART_SR_INTR_REMPTY; 278 279 if (s->rx_count == RX_FIFO_SIZE) { 280 s->r[R_CISR] |= UART_INTR_ROVR; 281 } else { 282 for (i = 0; i < size; i++) { 283 s->r_fifo[s->rx_wpos] = buf[i]; 284 s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE; 285 s->rx_count++; 286 287 if (s->rx_count == RX_FIFO_SIZE) { 288 s->r[R_SR] |= UART_SR_INTR_RFUL; 289 break; 290 } 291 292 if (s->rx_count >= s->r[R_RTRIG]) { 293 s->r[R_SR] |= UART_SR_INTR_RTRIG; 294 } 295 } 296 timer_mod(s->fifo_trigger_handle, new_rx_time + 297 (s->char_tx_time * 4)); 298 } 299 uart_update_status(s); 300 } 301 302 static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size) 303 { 304 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 305 return; 306 } 307 308 qemu_chr_fe_write_all(s->chr, buf, size); 309 } 310 311 static void uart_receive(void *opaque, const uint8_t *buf, int size) 312 { 313 UartState *s = (UartState *)opaque; 314 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 315 316 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 317 uart_write_rx_fifo(opaque, buf, size); 318 } 319 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 320 uart_write_tx_fifo(s, buf, size); 321 } 322 } 323 324 static void uart_event(void *opaque, int event) 325 { 326 UartState *s = (UartState *)opaque; 327 uint8_t buf = '\0'; 328 329 if (event == CHR_EVENT_BREAK) { 330 uart_write_rx_fifo(opaque, &buf, 1); 331 } 332 333 uart_update_status(s); 334 } 335 336 static void uart_read_rx_fifo(UartState *s, uint32_t *c) 337 { 338 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 339 return; 340 } 341 342 s->r[R_SR] &= ~UART_SR_INTR_RFUL; 343 344 if (s->rx_count) { 345 uint32_t rx_rpos = 346 (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE; 347 *c = s->r_fifo[rx_rpos]; 348 s->rx_count--; 349 350 if (!s->rx_count) { 351 s->r[R_SR] |= UART_SR_INTR_REMPTY; 352 } 353 qemu_chr_accept_input(s->chr); 354 } else { 355 *c = 0; 356 s->r[R_SR] |= UART_SR_INTR_REMPTY; 357 } 358 359 if (s->rx_count < s->r[R_RTRIG]) { 360 s->r[R_SR] &= ~UART_SR_INTR_RTRIG; 361 } 362 uart_update_status(s); 363 } 364 365 static void uart_write(void *opaque, hwaddr offset, 366 uint64_t value, unsigned size) 367 { 368 UartState *s = (UartState *)opaque; 369 370 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); 371 offset >>= 2; 372 switch (offset) { 373 case R_IER: /* ier (wts imr) */ 374 s->r[R_IMR] |= value; 375 break; 376 case R_IDR: /* idr (wtc imr) */ 377 s->r[R_IMR] &= ~value; 378 break; 379 case R_IMR: /* imr (read only) */ 380 break; 381 case R_CISR: /* cisr (wtc) */ 382 s->r[R_CISR] &= ~value; 383 break; 384 case R_TX_RX: /* UARTDR */ 385 switch (s->r[R_MR] & UART_MR_CHMODE) { 386 case NORMAL_MODE: 387 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 388 break; 389 case LOCAL_LOOPBACK: 390 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 391 break; 392 } 393 break; 394 default: 395 s->r[offset] = value; 396 } 397 398 switch (offset) { 399 case R_CR: 400 uart_ctrl_update(s); 401 break; 402 case R_MR: 403 uart_parameters_setup(s); 404 break; 405 } 406 } 407 408 static uint64_t uart_read(void *opaque, hwaddr offset, 409 unsigned size) 410 { 411 UartState *s = (UartState *)opaque; 412 uint32_t c = 0; 413 414 offset >>= 2; 415 if (offset >= R_MAX) { 416 c = 0; 417 } else if (offset == R_TX_RX) { 418 uart_read_rx_fifo(s, &c); 419 } else { 420 c = s->r[offset]; 421 } 422 423 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); 424 return c; 425 } 426 427 static const MemoryRegionOps uart_ops = { 428 .read = uart_read, 429 .write = uart_write, 430 .endianness = DEVICE_NATIVE_ENDIAN, 431 }; 432 433 static void cadence_uart_reset(UartState *s) 434 { 435 s->r[R_CR] = 0x00000128; 436 s->r[R_IMR] = 0; 437 s->r[R_CISR] = 0; 438 s->r[R_RTRIG] = 0x00000020; 439 s->r[R_BRGR] = 0x0000000F; 440 s->r[R_TTRIG] = 0x00000020; 441 442 uart_rx_reset(s); 443 uart_tx_reset(s); 444 445 s->rx_count = 0; 446 s->rx_wpos = 0; 447 } 448 449 static int cadence_uart_init(SysBusDevice *dev) 450 { 451 UartState *s = CADENCE_UART(dev); 452 453 memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000); 454 sysbus_init_mmio(dev, &s->iomem); 455 sysbus_init_irq(dev, &s->irq); 456 457 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 458 (QEMUTimerCB *)fifo_trigger_update, s); 459 460 s->tx_time_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 461 (QEMUTimerCB *)uart_tx_write, s); 462 463 s->char_tx_time = (get_ticks_per_sec() / 9600) * 10; 464 465 s->chr = qemu_char_get_next_serial(); 466 467 cadence_uart_reset(s); 468 469 if (s->chr) { 470 qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive, 471 uart_event, s); 472 } 473 474 return 0; 475 } 476 477 static int cadence_uart_post_load(void *opaque, int version_id) 478 { 479 UartState *s = opaque; 480 481 uart_parameters_setup(s); 482 uart_update_status(s); 483 return 0; 484 } 485 486 static const VMStateDescription vmstate_cadence_uart = { 487 .name = "cadence_uart", 488 .version_id = 1, 489 .minimum_version_id = 1, 490 .minimum_version_id_old = 1, 491 .post_load = cadence_uart_post_load, 492 .fields = (VMStateField[]) { 493 VMSTATE_UINT32_ARRAY(r, UartState, R_MAX), 494 VMSTATE_UINT8_ARRAY(r_fifo, UartState, RX_FIFO_SIZE), 495 VMSTATE_UINT32(rx_count, UartState), 496 VMSTATE_UINT32(rx_wpos, UartState), 497 VMSTATE_TIMER(fifo_trigger_handle, UartState), 498 VMSTATE_TIMER(tx_time_handle, UartState), 499 VMSTATE_END_OF_LIST() 500 } 501 }; 502 503 static void cadence_uart_class_init(ObjectClass *klass, void *data) 504 { 505 DeviceClass *dc = DEVICE_CLASS(klass); 506 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 507 508 sdc->init = cadence_uart_init; 509 dc->vmsd = &vmstate_cadence_uart; 510 } 511 512 static const TypeInfo cadence_uart_info = { 513 .name = TYPE_CADENCE_UART, 514 .parent = TYPE_SYS_BUS_DEVICE, 515 .instance_size = sizeof(UartState), 516 .class_init = cadence_uart_class_init, 517 }; 518 519 static void cadence_uart_register_types(void) 520 { 521 type_register_static(&cadence_uart_info); 522 } 523 524 type_init(cadence_uart_register_types) 525