xref: /qemu/hw/block/pflash_cfi02.c (revision 65a6d8dd3f322e91efa320f2811bec83dde36b6b)
1 /*
2  *  CFI parallel flash with AMD command set emulation
3  *
4  *  Copyright (c) 2005 Jocelyn Mayer
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 /*
21  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
22  * Supported commands/modes are:
23  * - flash read
24  * - flash write
25  * - flash ID read
26  * - sector erase
27  * - chip erase
28  * - unlock bypass command
29  * - CFI queries
30  *
31  * It does not support flash interleaving.
32  * It does not implement boot blocs with reduced size
33  * It does not implement software data protection as found in many real chips
34  * It does not implement erase suspend/resume commands
35  * It does not implement multiple sectors erase
36  */
37 
38 #include "qemu/osdep.h"
39 #include "hw/hw.h"
40 #include "hw/block/flash.h"
41 #include "qapi/error.h"
42 #include "qemu/timer.h"
43 #include "sysemu/block-backend.h"
44 #include "qemu/host-utils.h"
45 #include "hw/sysbus.h"
46 
47 //#define PFLASH_DEBUG
48 #ifdef PFLASH_DEBUG
49 #define DPRINTF(fmt, ...)                                  \
50 do {                                                       \
51     fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__);       \
52 } while (0)
53 #else
54 #define DPRINTF(fmt, ...) do { } while (0)
55 #endif
56 
57 #define PFLASH_LAZY_ROMD_THRESHOLD 42
58 
59 #define CFI_PFLASH02(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH02)
60 
61 struct pflash_t {
62     /*< private >*/
63     SysBusDevice parent_obj;
64     /*< public >*/
65 
66     BlockBackend *blk;
67     uint32_t sector_len;
68     uint32_t nb_blocs;
69     uint32_t chip_len;
70     uint8_t mappings;
71     uint8_t width;
72     uint8_t be;
73     int wcycle; /* if 0, the flash is read normally */
74     int bypass;
75     int ro;
76     uint8_t cmd;
77     uint8_t status;
78     /* FIXME: implement array device properties */
79     uint16_t ident0;
80     uint16_t ident1;
81     uint16_t ident2;
82     uint16_t ident3;
83     uint16_t unlock_addr0;
84     uint16_t unlock_addr1;
85     uint8_t cfi_table[0x52];
86     QEMUTimer *timer;
87     /* The device replicates the flash memory across its memory space.  Emulate
88      * that by having a container (.mem) filled with an array of aliases
89      * (.mem_mappings) pointing to the flash memory (.orig_mem).
90      */
91     MemoryRegion mem;
92     MemoryRegion *mem_mappings;    /* array; one per mapping */
93     MemoryRegion orig_mem;
94     int rom_mode;
95     int read_counter; /* used for lazy switch-back to rom mode */
96     char *name;
97     void *storage;
98 };
99 
100 /*
101  * Set up replicated mappings of the same region.
102  */
103 static void pflash_setup_mappings(pflash_t *pfl)
104 {
105     unsigned i;
106     hwaddr size = memory_region_size(&pfl->orig_mem);
107 
108     memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
109     pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
110     for (i = 0; i < pfl->mappings; ++i) {
111         memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
112                                  "pflash-alias", &pfl->orig_mem, 0, size);
113         memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
114     }
115 }
116 
117 static void pflash_register_memory(pflash_t *pfl, int rom_mode)
118 {
119     memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
120     pfl->rom_mode = rom_mode;
121 }
122 
123 static void pflash_timer (void *opaque)
124 {
125     pflash_t *pfl = opaque;
126 
127     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
128     /* Reset flash */
129     pfl->status ^= 0x80;
130     if (pfl->bypass) {
131         pfl->wcycle = 2;
132     } else {
133         pflash_register_memory(pfl, 1);
134         pfl->wcycle = 0;
135     }
136     pfl->cmd = 0;
137 }
138 
139 static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
140                              int width, int be)
141 {
142     hwaddr boff;
143     uint32_t ret;
144     uint8_t *p;
145 
146     DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset);
147     ret = -1;
148     /* Lazy reset to ROMD mode after a certain amount of read accesses */
149     if (!pfl->rom_mode && pfl->wcycle == 0 &&
150         ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
151         pflash_register_memory(pfl, 1);
152     }
153     offset &= pfl->chip_len - 1;
154     boff = offset & 0xFF;
155     if (pfl->width == 2)
156         boff = boff >> 1;
157     else if (pfl->width == 4)
158         boff = boff >> 2;
159     switch (pfl->cmd) {
160     default:
161         /* This should never happen : reset state & treat it as a read*/
162         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
163         pfl->wcycle = 0;
164         pfl->cmd = 0;
165         /* fall through to the read code */
166     case 0x80:
167         /* We accept reads during second unlock sequence... */
168     case 0x00:
169     flash_read:
170         /* Flash area read */
171         p = pfl->storage;
172         switch (width) {
173         case 1:
174             ret = p[offset];
175 //            DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
176             break;
177         case 2:
178             if (be) {
179                 ret = p[offset] << 8;
180                 ret |= p[offset + 1];
181             } else {
182                 ret = p[offset];
183                 ret |= p[offset + 1] << 8;
184             }
185 //            DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
186             break;
187         case 4:
188             if (be) {
189                 ret = p[offset] << 24;
190                 ret |= p[offset + 1] << 16;
191                 ret |= p[offset + 2] << 8;
192                 ret |= p[offset + 3];
193             } else {
194                 ret = p[offset];
195                 ret |= p[offset + 1] << 8;
196                 ret |= p[offset + 2] << 16;
197                 ret |= p[offset + 3] << 24;
198             }
199 //            DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
200             break;
201         }
202         break;
203     case 0x90:
204         /* flash ID read */
205         switch (boff) {
206         case 0x00:
207         case 0x01:
208             ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
209             break;
210         case 0x02:
211             ret = 0x00; /* Pretend all sectors are unprotected */
212             break;
213         case 0x0E:
214         case 0x0F:
215             ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
216             if (ret == (uint8_t)-1) {
217                 goto flash_read;
218             }
219             break;
220         default:
221             goto flash_read;
222         }
223         DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret);
224         break;
225     case 0xA0:
226     case 0x10:
227     case 0x30:
228         /* Status register read */
229         ret = pfl->status;
230         DPRINTF("%s: status %x\n", __func__, ret);
231         /* Toggle bit 6 */
232         pfl->status ^= 0x40;
233         break;
234     case 0x98:
235         /* CFI query mode */
236         if (boff < sizeof(pfl->cfi_table)) {
237             ret = pfl->cfi_table[boff];
238         } else {
239             ret = 0;
240         }
241         break;
242     }
243 
244     return ret;
245 }
246 
247 /* update flash content on disk */
248 static void pflash_update(pflash_t *pfl, int offset,
249                           int size)
250 {
251     int offset_end;
252     if (pfl->blk) {
253         offset_end = offset + size;
254         /* widen to sector boundaries */
255         offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
256         offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
257         blk_pwrite(pfl->blk, offset, pfl->storage + offset,
258                    offset_end - offset, 0);
259     }
260 }
261 
262 static void pflash_write (pflash_t *pfl, hwaddr offset,
263                           uint32_t value, int width, int be)
264 {
265     hwaddr boff;
266     uint8_t *p;
267     uint8_t cmd;
268 
269     cmd = value;
270     if (pfl->cmd != 0xA0 && cmd == 0xF0) {
271 #if 0
272         DPRINTF("%s: flash reset asked (%02x %02x)\n",
273                 __func__, pfl->cmd, cmd);
274 #endif
275         goto reset_flash;
276     }
277     DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__,
278             offset, value, width, pfl->wcycle);
279     offset &= pfl->chip_len - 1;
280 
281     DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__,
282             offset, value, width);
283     boff = offset & (pfl->sector_len - 1);
284     if (pfl->width == 2)
285         boff = boff >> 1;
286     else if (pfl->width == 4)
287         boff = boff >> 2;
288     switch (pfl->wcycle) {
289     case 0:
290         /* Set the device in I/O access mode if required */
291         if (pfl->rom_mode)
292             pflash_register_memory(pfl, 0);
293         pfl->read_counter = 0;
294         /* We're in read mode */
295     check_unlock0:
296         if (boff == 0x55 && cmd == 0x98) {
297         enter_CFI_mode:
298             /* Enter CFI query mode */
299             pfl->wcycle = 7;
300             pfl->cmd = 0x98;
301             return;
302         }
303         if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
304             DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
305                     __func__, boff, cmd, pfl->unlock_addr0);
306             goto reset_flash;
307         }
308         DPRINTF("%s: unlock sequence started\n", __func__);
309         break;
310     case 1:
311         /* We started an unlock sequence */
312     check_unlock1:
313         if (boff != pfl->unlock_addr1 || cmd != 0x55) {
314             DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
315                     boff, cmd);
316             goto reset_flash;
317         }
318         DPRINTF("%s: unlock sequence done\n", __func__);
319         break;
320     case 2:
321         /* We finished an unlock sequence */
322         if (!pfl->bypass && boff != pfl->unlock_addr0) {
323             DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
324                     boff, cmd);
325             goto reset_flash;
326         }
327         switch (cmd) {
328         case 0x20:
329             pfl->bypass = 1;
330             goto do_bypass;
331         case 0x80:
332         case 0x90:
333         case 0xA0:
334             pfl->cmd = cmd;
335             DPRINTF("%s: starting command %02x\n", __func__, cmd);
336             break;
337         default:
338             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
339             goto reset_flash;
340         }
341         break;
342     case 3:
343         switch (pfl->cmd) {
344         case 0x80:
345             /* We need another unlock sequence */
346             goto check_unlock0;
347         case 0xA0:
348             DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n",
349                     __func__, offset, value, width);
350             p = pfl->storage;
351             if (!pfl->ro) {
352                 switch (width) {
353                 case 1:
354                     p[offset] &= value;
355                     pflash_update(pfl, offset, 1);
356                     break;
357                 case 2:
358                     if (be) {
359                         p[offset] &= value >> 8;
360                         p[offset + 1] &= value;
361                     } else {
362                         p[offset] &= value;
363                         p[offset + 1] &= value >> 8;
364                     }
365                     pflash_update(pfl, offset, 2);
366                     break;
367                 case 4:
368                     if (be) {
369                         p[offset] &= value >> 24;
370                         p[offset + 1] &= value >> 16;
371                         p[offset + 2] &= value >> 8;
372                         p[offset + 3] &= value;
373                     } else {
374                         p[offset] &= value;
375                         p[offset + 1] &= value >> 8;
376                         p[offset + 2] &= value >> 16;
377                         p[offset + 3] &= value >> 24;
378                     }
379                     pflash_update(pfl, offset, 4);
380                     break;
381                 }
382             }
383             pfl->status = 0x00 | ~(value & 0x80);
384             /* Let's pretend write is immediate */
385             if (pfl->bypass)
386                 goto do_bypass;
387             goto reset_flash;
388         case 0x90:
389             if (pfl->bypass && cmd == 0x00) {
390                 /* Unlock bypass reset */
391                 goto reset_flash;
392             }
393             /* We can enter CFI query mode from autoselect mode */
394             if (boff == 0x55 && cmd == 0x98)
395                 goto enter_CFI_mode;
396             /* No break here */
397         default:
398             DPRINTF("%s: invalid write for command %02x\n",
399                     __func__, pfl->cmd);
400             goto reset_flash;
401         }
402     case 4:
403         switch (pfl->cmd) {
404         case 0xA0:
405             /* Ignore writes while flash data write is occurring */
406             /* As we suppose write is immediate, this should never happen */
407             return;
408         case 0x80:
409             goto check_unlock1;
410         default:
411             /* Should never happen */
412             DPRINTF("%s: invalid command state %02x (wc 4)\n",
413                     __func__, pfl->cmd);
414             goto reset_flash;
415         }
416         break;
417     case 5:
418         switch (cmd) {
419         case 0x10:
420             if (boff != pfl->unlock_addr0) {
421                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
422                         __func__, offset);
423                 goto reset_flash;
424             }
425             /* Chip erase */
426             DPRINTF("%s: start chip erase\n", __func__);
427             if (!pfl->ro) {
428                 memset(pfl->storage, 0xFF, pfl->chip_len);
429                 pflash_update(pfl, 0, pfl->chip_len);
430             }
431             pfl->status = 0x00;
432             /* Let's wait 5 seconds before chip erase is done */
433             timer_mod(pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
434                       (NANOSECONDS_PER_SECOND * 5));
435             break;
436         case 0x30:
437             /* Sector erase */
438             p = pfl->storage;
439             offset &= ~(pfl->sector_len - 1);
440             DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,
441                     offset);
442             if (!pfl->ro) {
443                 memset(p + offset, 0xFF, pfl->sector_len);
444                 pflash_update(pfl, offset, pfl->sector_len);
445             }
446             pfl->status = 0x00;
447             /* Let's wait 1/2 second before sector erase is done */
448             timer_mod(pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
449                       (NANOSECONDS_PER_SECOND / 2));
450             break;
451         default:
452             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
453             goto reset_flash;
454         }
455         pfl->cmd = cmd;
456         break;
457     case 6:
458         switch (pfl->cmd) {
459         case 0x10:
460             /* Ignore writes during chip erase */
461             return;
462         case 0x30:
463             /* Ignore writes during sector erase */
464             return;
465         default:
466             /* Should never happen */
467             DPRINTF("%s: invalid command state %02x (wc 6)\n",
468                     __func__, pfl->cmd);
469             goto reset_flash;
470         }
471         break;
472     case 7: /* Special value for CFI queries */
473         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
474         goto reset_flash;
475     default:
476         /* Should never happen */
477         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
478         goto reset_flash;
479     }
480     pfl->wcycle++;
481 
482     return;
483 
484     /* Reset flash */
485  reset_flash:
486     pfl->bypass = 0;
487     pfl->wcycle = 0;
488     pfl->cmd = 0;
489     return;
490 
491  do_bypass:
492     pfl->wcycle = 2;
493     pfl->cmd = 0;
494 }
495 
496 
497 static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
498 {
499     return pflash_read(opaque, addr, 1, 1);
500 }
501 
502 static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
503 {
504     return pflash_read(opaque, addr, 1, 0);
505 }
506 
507 static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
508 {
509     pflash_t *pfl = opaque;
510 
511     return pflash_read(pfl, addr, 2, 1);
512 }
513 
514 static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
515 {
516     pflash_t *pfl = opaque;
517 
518     return pflash_read(pfl, addr, 2, 0);
519 }
520 
521 static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
522 {
523     pflash_t *pfl = opaque;
524 
525     return pflash_read(pfl, addr, 4, 1);
526 }
527 
528 static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
529 {
530     pflash_t *pfl = opaque;
531 
532     return pflash_read(pfl, addr, 4, 0);
533 }
534 
535 static void pflash_writeb_be(void *opaque, hwaddr addr,
536                              uint32_t value)
537 {
538     pflash_write(opaque, addr, value, 1, 1);
539 }
540 
541 static void pflash_writeb_le(void *opaque, hwaddr addr,
542                              uint32_t value)
543 {
544     pflash_write(opaque, addr, value, 1, 0);
545 }
546 
547 static void pflash_writew_be(void *opaque, hwaddr addr,
548                              uint32_t value)
549 {
550     pflash_t *pfl = opaque;
551 
552     pflash_write(pfl, addr, value, 2, 1);
553 }
554 
555 static void pflash_writew_le(void *opaque, hwaddr addr,
556                              uint32_t value)
557 {
558     pflash_t *pfl = opaque;
559 
560     pflash_write(pfl, addr, value, 2, 0);
561 }
562 
563 static void pflash_writel_be(void *opaque, hwaddr addr,
564                              uint32_t value)
565 {
566     pflash_t *pfl = opaque;
567 
568     pflash_write(pfl, addr, value, 4, 1);
569 }
570 
571 static void pflash_writel_le(void *opaque, hwaddr addr,
572                              uint32_t value)
573 {
574     pflash_t *pfl = opaque;
575 
576     pflash_write(pfl, addr, value, 4, 0);
577 }
578 
579 static const MemoryRegionOps pflash_cfi02_ops_be = {
580     .old_mmio = {
581         .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
582         .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
583     },
584     .endianness = DEVICE_NATIVE_ENDIAN,
585 };
586 
587 static const MemoryRegionOps pflash_cfi02_ops_le = {
588     .old_mmio = {
589         .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
590         .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
591     },
592     .endianness = DEVICE_NATIVE_ENDIAN,
593 };
594 
595 static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
596 {
597     pflash_t *pfl = CFI_PFLASH02(dev);
598     uint32_t chip_len;
599     int ret;
600     Error *local_err = NULL;
601 
602     if (pfl->sector_len == 0) {
603         error_setg(errp, "attribute \"sector-length\" not specified or zero.");
604         return;
605     }
606     if (pfl->nb_blocs == 0) {
607         error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
608         return;
609     }
610     if (pfl->name == NULL) {
611         error_setg(errp, "attribute \"name\" not specified.");
612         return;
613     }
614 
615     chip_len = pfl->sector_len * pfl->nb_blocs;
616     /* XXX: to be fixed */
617 #if 0
618     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
619         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
620         return NULL;
621 #endif
622 
623     memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ?
624                                   &pflash_cfi02_ops_be : &pflash_cfi02_ops_le,
625                                   pfl, pfl->name, chip_len, &local_err);
626     if (local_err) {
627         error_propagate(errp, local_err);
628         return;
629     }
630 
631     pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
632     pfl->chip_len = chip_len;
633 
634     if (pfl->blk) {
635         uint64_t perm;
636         pfl->ro = blk_is_read_only(pfl->blk);
637         perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
638         ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
639         if (ret < 0) {
640             return;
641         }
642     } else {
643         pfl->ro = 0;
644     }
645 
646     if (pfl->blk) {
647         /* read the initial flash content */
648         ret = blk_pread(pfl->blk, 0, pfl->storage, chip_len);
649         if (ret < 0) {
650             vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
651             error_setg(errp, "failed to read the initial flash content");
652             return;
653         }
654     }
655 
656     pflash_setup_mappings(pfl);
657     pfl->rom_mode = 1;
658     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
659 
660     pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
661     pfl->wcycle = 0;
662     pfl->cmd = 0;
663     pfl->status = 0;
664     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
665     /* Standard "QRY" string */
666     pfl->cfi_table[0x10] = 'Q';
667     pfl->cfi_table[0x11] = 'R';
668     pfl->cfi_table[0x12] = 'Y';
669     /* Command set (AMD/Fujitsu) */
670     pfl->cfi_table[0x13] = 0x02;
671     pfl->cfi_table[0x14] = 0x00;
672     /* Primary extended table address */
673     pfl->cfi_table[0x15] = 0x31;
674     pfl->cfi_table[0x16] = 0x00;
675     /* Alternate command set (none) */
676     pfl->cfi_table[0x17] = 0x00;
677     pfl->cfi_table[0x18] = 0x00;
678     /* Alternate extended table (none) */
679     pfl->cfi_table[0x19] = 0x00;
680     pfl->cfi_table[0x1A] = 0x00;
681     /* Vcc min */
682     pfl->cfi_table[0x1B] = 0x27;
683     /* Vcc max */
684     pfl->cfi_table[0x1C] = 0x36;
685     /* Vpp min (no Vpp pin) */
686     pfl->cfi_table[0x1D] = 0x00;
687     /* Vpp max (no Vpp pin) */
688     pfl->cfi_table[0x1E] = 0x00;
689     /* Reserved */
690     pfl->cfi_table[0x1F] = 0x07;
691     /* Timeout for min size buffer write (NA) */
692     pfl->cfi_table[0x20] = 0x00;
693     /* Typical timeout for block erase (512 ms) */
694     pfl->cfi_table[0x21] = 0x09;
695     /* Typical timeout for full chip erase (4096 ms) */
696     pfl->cfi_table[0x22] = 0x0C;
697     /* Reserved */
698     pfl->cfi_table[0x23] = 0x01;
699     /* Max timeout for buffer write (NA) */
700     pfl->cfi_table[0x24] = 0x00;
701     /* Max timeout for block erase */
702     pfl->cfi_table[0x25] = 0x0A;
703     /* Max timeout for chip erase */
704     pfl->cfi_table[0x26] = 0x0D;
705     /* Device size */
706     pfl->cfi_table[0x27] = ctz32(chip_len);
707     /* Flash device interface (8 & 16 bits) */
708     pfl->cfi_table[0x28] = 0x02;
709     pfl->cfi_table[0x29] = 0x00;
710     /* Max number of bytes in multi-bytes write */
711     /* XXX: disable buffered write as it's not supported */
712     //    pfl->cfi_table[0x2A] = 0x05;
713     pfl->cfi_table[0x2A] = 0x00;
714     pfl->cfi_table[0x2B] = 0x00;
715     /* Number of erase block regions (uniform) */
716     pfl->cfi_table[0x2C] = 0x01;
717     /* Erase block region 1 */
718     pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
719     pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
720     pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
721     pfl->cfi_table[0x30] = pfl->sector_len >> 16;
722 
723     /* Extended */
724     pfl->cfi_table[0x31] = 'P';
725     pfl->cfi_table[0x32] = 'R';
726     pfl->cfi_table[0x33] = 'I';
727 
728     pfl->cfi_table[0x34] = '1';
729     pfl->cfi_table[0x35] = '0';
730 
731     pfl->cfi_table[0x36] = 0x00;
732     pfl->cfi_table[0x37] = 0x00;
733     pfl->cfi_table[0x38] = 0x00;
734     pfl->cfi_table[0x39] = 0x00;
735 
736     pfl->cfi_table[0x3a] = 0x00;
737 
738     pfl->cfi_table[0x3b] = 0x00;
739     pfl->cfi_table[0x3c] = 0x00;
740 }
741 
742 static Property pflash_cfi02_properties[] = {
743     DEFINE_PROP_DRIVE("drive", struct pflash_t, blk),
744     DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0),
745     DEFINE_PROP_UINT32("sector-length", struct pflash_t, sector_len, 0),
746     DEFINE_PROP_UINT8("width", struct pflash_t, width, 0),
747     DEFINE_PROP_UINT8("mappings", struct pflash_t, mappings, 0),
748     DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0),
749     DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0),
750     DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0),
751     DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0),
752     DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0),
753     DEFINE_PROP_UINT16("unlock-addr0", struct pflash_t, unlock_addr0, 0),
754     DEFINE_PROP_UINT16("unlock-addr1", struct pflash_t, unlock_addr1, 0),
755     DEFINE_PROP_STRING("name", struct pflash_t, name),
756     DEFINE_PROP_END_OF_LIST(),
757 };
758 
759 static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
760 {
761     DeviceClass *dc = DEVICE_CLASS(klass);
762 
763     dc->realize = pflash_cfi02_realize;
764     dc->props = pflash_cfi02_properties;
765     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
766 }
767 
768 static const TypeInfo pflash_cfi02_info = {
769     .name           = TYPE_CFI_PFLASH02,
770     .parent         = TYPE_SYS_BUS_DEVICE,
771     .instance_size  = sizeof(struct pflash_t),
772     .class_init     = pflash_cfi02_class_init,
773 };
774 
775 static void pflash_cfi02_register_types(void)
776 {
777     type_register_static(&pflash_cfi02_info);
778 }
779 
780 type_init(pflash_cfi02_register_types)
781 
782 pflash_t *pflash_cfi02_register(hwaddr base,
783                                 DeviceState *qdev, const char *name,
784                                 hwaddr size,
785                                 BlockBackend *blk, uint32_t sector_len,
786                                 int nb_blocs, int nb_mappings, int width,
787                                 uint16_t id0, uint16_t id1,
788                                 uint16_t id2, uint16_t id3,
789                                 uint16_t unlock_addr0, uint16_t unlock_addr1,
790                                 int be)
791 {
792     DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH02);
793 
794     if (blk) {
795         qdev_prop_set_drive(dev, "drive", blk, &error_abort);
796     }
797     qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
798     qdev_prop_set_uint32(dev, "sector-length", sector_len);
799     qdev_prop_set_uint8(dev, "width", width);
800     qdev_prop_set_uint8(dev, "mappings", nb_mappings);
801     qdev_prop_set_uint8(dev, "big-endian", !!be);
802     qdev_prop_set_uint16(dev, "id0", id0);
803     qdev_prop_set_uint16(dev, "id1", id1);
804     qdev_prop_set_uint16(dev, "id2", id2);
805     qdev_prop_set_uint16(dev, "id3", id3);
806     qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
807     qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
808     qdev_prop_set_string(dev, "name", name);
809     qdev_init_nofail(dev);
810 
811     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
812     return CFI_PFLASH02(dev);
813 }
814