1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "hw/hw.h" 25 #include "sysemu/blockdev.h" 26 #include "hw/ssi.h" 27 #include "hw/devices.h" 28 29 #ifndef M25P80_ERR_DEBUG 30 #define M25P80_ERR_DEBUG 0 31 #endif 32 33 #define DB_PRINT_L(level, ...) do { \ 34 if (M25P80_ERR_DEBUG > (level)) { \ 35 fprintf(stderr, ": %s: ", __func__); \ 36 fprintf(stderr, ## __VA_ARGS__); \ 37 } \ 38 } while (0); 39 40 /* Fields for FlashPartInfo->flags */ 41 42 /* erase capabilities */ 43 #define ER_4K 1 44 #define ER_32K 2 45 /* set to allow the page program command to write 0s back to 1. Useful for 46 * modelling EEPROM with SPI flash command set 47 */ 48 #define WR_1 0x100 49 50 typedef struct FlashPartInfo { 51 const char *part_name; 52 /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */ 53 uint32_t jedec; 54 /* extended jedec code */ 55 uint16_t ext_jedec; 56 /* there is confusion between manufacturers as to what a sector is. In this 57 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 58 * command (opcode 0xd8). 59 */ 60 uint32_t sector_size; 61 uint32_t n_sectors; 62 uint32_t page_size; 63 uint8_t flags; 64 } FlashPartInfo; 65 66 /* adapted from linux */ 67 68 #define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\ 69 .part_name = (_part_name),\ 70 .jedec = (_jedec),\ 71 .ext_jedec = (_ext_jedec),\ 72 .sector_size = (_sector_size),\ 73 .n_sectors = (_n_sectors),\ 74 .page_size = 256,\ 75 .flags = (_flags),\ 76 77 #define JEDEC_NUMONYX 0x20 78 #define JEDEC_WINBOND 0xEF 79 #define JEDEC_SPANSION 0x01 80 81 static const FlashPartInfo known_devices[] = { 82 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 83 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 84 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 85 86 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 87 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 88 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 89 90 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 91 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 92 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 93 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 94 95 /* EON -- en25xxx */ 96 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 97 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 98 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 99 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 100 101 /* Intel/Numonyx -- xxxs33b */ 102 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 103 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 104 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 105 106 /* Macronix */ 107 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 108 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 109 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 110 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 111 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 112 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 113 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 114 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) }, 115 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 116 117 /* Spansion -- single (large) sector size only, at least 118 * for the chips listed here (without boot sectors). 119 */ 120 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 121 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 122 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 123 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 124 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 125 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 126 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 127 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 128 { INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) }, 129 { INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) }, 130 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 131 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 132 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 133 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 134 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 135 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 136 137 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 138 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 139 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 140 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 141 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 142 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 143 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 144 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 145 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 146 147 /* ST Microelectronics -- newer production may have feature updates */ 148 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 149 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 150 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 151 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 152 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 153 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 154 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 155 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 156 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 157 158 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 159 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 160 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 161 162 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 163 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 164 165 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 166 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 167 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 168 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 169 170 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 171 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 172 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 173 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 174 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 175 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 176 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 177 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 178 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 179 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 180 181 /* Numonyx -- n25q128 */ 182 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 183 }; 184 185 typedef enum { 186 NOP = 0, 187 WRSR = 0x1, 188 WRDI = 0x4, 189 RDSR = 0x5, 190 WREN = 0x6, 191 JEDEC_READ = 0x9f, 192 BULK_ERASE = 0xc7, 193 194 READ = 0x3, 195 FAST_READ = 0xb, 196 DOR = 0x3b, 197 QOR = 0x6b, 198 DIOR = 0xbb, 199 QIOR = 0xeb, 200 201 PP = 0x2, 202 DPP = 0xa2, 203 QPP = 0x32, 204 205 ERASE_4K = 0x20, 206 ERASE_32K = 0x52, 207 ERASE_SECTOR = 0xd8, 208 } FlashCMD; 209 210 typedef enum { 211 STATE_IDLE, 212 STATE_PAGE_PROGRAM, 213 STATE_READ, 214 STATE_COLLECTING_DATA, 215 STATE_READING_DATA, 216 } CMDState; 217 218 typedef struct Flash { 219 SSISlave ssidev; 220 uint32_t r; 221 222 BlockDriverState *bdrv; 223 224 uint8_t *storage; 225 uint32_t size; 226 int page_size; 227 228 uint8_t state; 229 uint8_t data[16]; 230 uint32_t len; 231 uint32_t pos; 232 uint8_t needed_bytes; 233 uint8_t cmd_in_progress; 234 uint64_t cur_addr; 235 bool write_enable; 236 237 int64_t dirty_page; 238 239 const FlashPartInfo *pi; 240 241 } Flash; 242 243 typedef struct M25P80Class { 244 SSISlaveClass parent_class; 245 FlashPartInfo *pi; 246 } M25P80Class; 247 248 #define TYPE_M25P80 "m25p80-generic" 249 #define M25P80(obj) \ 250 OBJECT_CHECK(Flash, (obj), TYPE_M25P80) 251 #define M25P80_CLASS(klass) \ 252 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80) 253 #define M25P80_GET_CLASS(obj) \ 254 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80) 255 256 static void bdrv_sync_complete(void *opaque, int ret) 257 { 258 /* do nothing. Masters do not directly interact with the backing store, 259 * only the working copy so no mutexing required. 260 */ 261 } 262 263 static void flash_sync_page(Flash *s, int page) 264 { 265 if (s->bdrv) { 266 int bdrv_sector, nb_sectors; 267 QEMUIOVector iov; 268 269 bdrv_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE; 270 nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE); 271 qemu_iovec_init(&iov, 1); 272 qemu_iovec_add(&iov, s->storage + bdrv_sector * BDRV_SECTOR_SIZE, 273 nb_sectors * BDRV_SECTOR_SIZE); 274 bdrv_aio_writev(s->bdrv, bdrv_sector, &iov, nb_sectors, 275 bdrv_sync_complete, NULL); 276 } 277 } 278 279 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 280 { 281 int64_t start, end, nb_sectors; 282 QEMUIOVector iov; 283 284 if (!s->bdrv) { 285 return; 286 } 287 288 assert(!(len % BDRV_SECTOR_SIZE)); 289 start = off / BDRV_SECTOR_SIZE; 290 end = (off + len) / BDRV_SECTOR_SIZE; 291 nb_sectors = end - start; 292 qemu_iovec_init(&iov, 1); 293 qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE), 294 nb_sectors * BDRV_SECTOR_SIZE); 295 bdrv_aio_writev(s->bdrv, start, &iov, nb_sectors, bdrv_sync_complete, NULL); 296 } 297 298 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 299 { 300 uint32_t len; 301 uint8_t capa_to_assert = 0; 302 303 switch (cmd) { 304 case ERASE_4K: 305 len = 4 << 10; 306 capa_to_assert = ER_4K; 307 break; 308 case ERASE_32K: 309 len = 32 << 10; 310 capa_to_assert = ER_32K; 311 break; 312 case ERASE_SECTOR: 313 len = s->pi->sector_size; 314 break; 315 case BULK_ERASE: 316 len = s->size; 317 break; 318 default: 319 abort(); 320 } 321 322 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len); 323 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 324 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 325 " device\n", len); 326 } 327 328 if (!s->write_enable) { 329 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 330 return; 331 } 332 memset(s->storage + offset, 0xff, len); 333 flash_sync_area(s, offset, len); 334 } 335 336 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 337 { 338 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 339 flash_sync_page(s, s->dirty_page); 340 s->dirty_page = newpage; 341 } 342 } 343 344 static inline 345 void flash_write8(Flash *s, uint64_t addr, uint8_t data) 346 { 347 int64_t page = addr / s->pi->page_size; 348 uint8_t prev = s->storage[s->cur_addr]; 349 350 if (!s->write_enable) { 351 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 352 } 353 354 if ((prev ^ data) & data) { 355 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8 356 " -> %" PRIx8 "\n", addr, prev, data); 357 } 358 359 if (s->pi->flags & WR_1) { 360 s->storage[s->cur_addr] = data; 361 } else { 362 s->storage[s->cur_addr] &= data; 363 } 364 365 flash_sync_dirty(s, page); 366 s->dirty_page = page; 367 } 368 369 static void complete_collecting_data(Flash *s) 370 { 371 s->cur_addr = s->data[0] << 16; 372 s->cur_addr |= s->data[1] << 8; 373 s->cur_addr |= s->data[2]; 374 375 s->state = STATE_IDLE; 376 377 switch (s->cmd_in_progress) { 378 case DPP: 379 case QPP: 380 case PP: 381 s->state = STATE_PAGE_PROGRAM; 382 break; 383 case READ: 384 case FAST_READ: 385 case DOR: 386 case QOR: 387 case DIOR: 388 case QIOR: 389 s->state = STATE_READ; 390 break; 391 case ERASE_4K: 392 case ERASE_32K: 393 case ERASE_SECTOR: 394 flash_erase(s, s->cur_addr, s->cmd_in_progress); 395 break; 396 case WRSR: 397 if (s->write_enable) { 398 s->write_enable = false; 399 } 400 break; 401 default: 402 break; 403 } 404 } 405 406 static void decode_new_cmd(Flash *s, uint32_t value) 407 { 408 s->cmd_in_progress = value; 409 DB_PRINT_L(0, "decoded new command:%x\n", value); 410 411 switch (value) { 412 413 case ERASE_4K: 414 case ERASE_32K: 415 case ERASE_SECTOR: 416 case READ: 417 case DPP: 418 case QPP: 419 case PP: 420 s->needed_bytes = 3; 421 s->pos = 0; 422 s->len = 0; 423 s->state = STATE_COLLECTING_DATA; 424 break; 425 426 case FAST_READ: 427 case DOR: 428 case QOR: 429 s->needed_bytes = 4; 430 s->pos = 0; 431 s->len = 0; 432 s->state = STATE_COLLECTING_DATA; 433 break; 434 435 case DIOR: 436 switch ((s->pi->jedec >> 16) & 0xFF) { 437 case JEDEC_WINBOND: 438 case JEDEC_SPANSION: 439 s->needed_bytes = 4; 440 break; 441 case JEDEC_NUMONYX: 442 default: 443 s->needed_bytes = 5; 444 } 445 s->pos = 0; 446 s->len = 0; 447 s->state = STATE_COLLECTING_DATA; 448 break; 449 450 case QIOR: 451 switch ((s->pi->jedec >> 16) & 0xFF) { 452 case JEDEC_WINBOND: 453 case JEDEC_SPANSION: 454 s->needed_bytes = 6; 455 break; 456 case JEDEC_NUMONYX: 457 default: 458 s->needed_bytes = 8; 459 } 460 s->pos = 0; 461 s->len = 0; 462 s->state = STATE_COLLECTING_DATA; 463 break; 464 465 case WRSR: 466 if (s->write_enable) { 467 s->needed_bytes = 1; 468 s->pos = 0; 469 s->len = 0; 470 s->state = STATE_COLLECTING_DATA; 471 } 472 break; 473 474 case WRDI: 475 s->write_enable = false; 476 break; 477 case WREN: 478 s->write_enable = true; 479 break; 480 481 case RDSR: 482 s->data[0] = (!!s->write_enable) << 1; 483 s->pos = 0; 484 s->len = 1; 485 s->state = STATE_READING_DATA; 486 break; 487 488 case JEDEC_READ: 489 DB_PRINT_L(0, "populated jedec code\n"); 490 s->data[0] = (s->pi->jedec >> 16) & 0xff; 491 s->data[1] = (s->pi->jedec >> 8) & 0xff; 492 s->data[2] = s->pi->jedec & 0xff; 493 if (s->pi->ext_jedec) { 494 s->data[3] = (s->pi->ext_jedec >> 8) & 0xff; 495 s->data[4] = s->pi->ext_jedec & 0xff; 496 s->len = 5; 497 } else { 498 s->len = 3; 499 } 500 s->pos = 0; 501 s->state = STATE_READING_DATA; 502 break; 503 504 case BULK_ERASE: 505 if (s->write_enable) { 506 DB_PRINT_L(0, "chip erase\n"); 507 flash_erase(s, 0, BULK_ERASE); 508 } else { 509 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 510 "protect!\n"); 511 } 512 break; 513 case NOP: 514 break; 515 default: 516 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 517 break; 518 } 519 } 520 521 static int m25p80_cs(SSISlave *ss, bool select) 522 { 523 Flash *s = FROM_SSI_SLAVE(Flash, ss); 524 525 if (select) { 526 s->len = 0; 527 s->pos = 0; 528 s->state = STATE_IDLE; 529 flash_sync_dirty(s, -1); 530 } 531 532 DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); 533 534 return 0; 535 } 536 537 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) 538 { 539 Flash *s = FROM_SSI_SLAVE(Flash, ss); 540 uint32_t r = 0; 541 542 switch (s->state) { 543 544 case STATE_PAGE_PROGRAM: 545 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n", 546 s->cur_addr, (uint8_t)tx); 547 flash_write8(s, s->cur_addr, (uint8_t)tx); 548 s->cur_addr++; 549 break; 550 551 case STATE_READ: 552 r = s->storage[s->cur_addr]; 553 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr, 554 (uint8_t)r); 555 s->cur_addr = (s->cur_addr + 1) % s->size; 556 break; 557 558 case STATE_COLLECTING_DATA: 559 s->data[s->len] = (uint8_t)tx; 560 s->len++; 561 562 if (s->len == s->needed_bytes) { 563 complete_collecting_data(s); 564 } 565 break; 566 567 case STATE_READING_DATA: 568 r = s->data[s->pos]; 569 s->pos++; 570 if (s->pos == s->len) { 571 s->pos = 0; 572 s->state = STATE_IDLE; 573 } 574 break; 575 576 default: 577 case STATE_IDLE: 578 decode_new_cmd(s, (uint8_t)tx); 579 break; 580 } 581 582 return r; 583 } 584 585 static int m25p80_init(SSISlave *ss) 586 { 587 DriveInfo *dinfo; 588 Flash *s = FROM_SSI_SLAVE(Flash, ss); 589 M25P80Class *mc = M25P80_GET_CLASS(s); 590 591 s->pi = mc->pi; 592 593 s->size = s->pi->sector_size * s->pi->n_sectors; 594 s->dirty_page = -1; 595 s->storage = qemu_blockalign(s->bdrv, s->size); 596 597 dinfo = drive_get_next(IF_MTD); 598 599 if (dinfo && dinfo->bdrv) { 600 DB_PRINT_L(0, "Binding to IF_MTD drive\n"); 601 s->bdrv = dinfo->bdrv; 602 /* FIXME: Move to late init */ 603 if (bdrv_read(s->bdrv, 0, s->storage, DIV_ROUND_UP(s->size, 604 BDRV_SECTOR_SIZE))) { 605 fprintf(stderr, "Failed to initialize SPI flash!\n"); 606 return 1; 607 } 608 } else { 609 DB_PRINT_L(0, "No BDRV - binding to RAM\n"); 610 memset(s->storage, 0xFF, s->size); 611 } 612 613 return 0; 614 } 615 616 static void m25p80_pre_save(void *opaque) 617 { 618 flash_sync_dirty((Flash *)opaque, -1); 619 } 620 621 static const VMStateDescription vmstate_m25p80 = { 622 .name = "xilinx_spi", 623 .version_id = 1, 624 .minimum_version_id = 1, 625 .minimum_version_id_old = 1, 626 .pre_save = m25p80_pre_save, 627 .fields = (VMStateField[]) { 628 VMSTATE_UINT8(state, Flash), 629 VMSTATE_UINT8_ARRAY(data, Flash, 16), 630 VMSTATE_UINT32(len, Flash), 631 VMSTATE_UINT32(pos, Flash), 632 VMSTATE_UINT8(needed_bytes, Flash), 633 VMSTATE_UINT8(cmd_in_progress, Flash), 634 VMSTATE_UINT64(cur_addr, Flash), 635 VMSTATE_BOOL(write_enable, Flash), 636 VMSTATE_END_OF_LIST() 637 } 638 }; 639 640 static void m25p80_class_init(ObjectClass *klass, void *data) 641 { 642 DeviceClass *dc = DEVICE_CLASS(klass); 643 SSISlaveClass *k = SSI_SLAVE_CLASS(klass); 644 M25P80Class *mc = M25P80_CLASS(klass); 645 646 k->init = m25p80_init; 647 k->transfer = m25p80_transfer8; 648 k->set_cs = m25p80_cs; 649 k->cs_polarity = SSI_CS_LOW; 650 dc->vmsd = &vmstate_m25p80; 651 mc->pi = data; 652 } 653 654 static const TypeInfo m25p80_info = { 655 .name = TYPE_M25P80, 656 .parent = TYPE_SSI_SLAVE, 657 .instance_size = sizeof(Flash), 658 .class_size = sizeof(M25P80Class), 659 .abstract = true, 660 }; 661 662 static void m25p80_register_types(void) 663 { 664 int i; 665 666 type_register_static(&m25p80_info); 667 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 668 TypeInfo ti = { 669 .name = known_devices[i].part_name, 670 .parent = TYPE_M25P80, 671 .class_init = m25p80_class_init, 672 .class_data = (void *)&known_devices[i], 673 }; 674 type_register(&ti); 675 } 676 } 677 678 type_init(m25p80_register_types) 679