1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Gerd Hoffmann <kraxel@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/pci/pci.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/timer.h" 25 #include "qemu/bitops.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "qemu/error-report.h" 29 #include "hw/audio/soundhw.h" 30 #include "intel-hda.h" 31 #include "migration/vmstate.h" 32 #include "intel-hda-defs.h" 33 #include "system/dma.h" 34 #include "qapi/error.h" 35 #include "qom/object.h" 36 37 /* --------------------------------------------------------------------- */ 38 /* hda bus */ 39 40 static const Property hda_props[] = { 41 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), 42 }; 43 44 static const TypeInfo hda_codec_bus_info = { 45 .name = TYPE_HDA_BUS, 46 .parent = TYPE_BUS, 47 .instance_size = sizeof(HDACodecBus), 48 }; 49 50 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, 51 hda_codec_response_func response, 52 hda_codec_xfer_func xfer) 53 { 54 qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL); 55 bus->response = response; 56 bus->xfer = xfer; 57 } 58 59 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp) 60 { 61 HDACodecBus *bus = HDA_BUS(qdev->parent_bus); 62 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 63 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 64 65 if (dev->cad == -1) { 66 dev->cad = bus->next_cad; 67 } 68 if (dev->cad >= 15) { 69 error_setg(errp, "HDA audio codec address is full"); 70 return; 71 } 72 bus->next_cad = dev->cad + 1; 73 cdc->init(dev, errp); 74 } 75 76 static void hda_codec_dev_unrealize(DeviceState *qdev) 77 { 78 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 79 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 80 81 if (cdc->exit) { 82 cdc->exit(dev); 83 } 84 } 85 86 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) 87 { 88 BusChild *kid; 89 HDACodecDevice *cdev; 90 91 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { 92 DeviceState *qdev = kid->child; 93 cdev = HDA_CODEC_DEVICE(qdev); 94 if (cdev->cad == cad) { 95 return cdev; 96 } 97 } 98 return NULL; 99 } 100 101 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) 102 { 103 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 104 bus->response(dev, solicited, response); 105 } 106 107 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 108 uint8_t *buf, uint32_t len) 109 { 110 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 111 return bus->xfer(dev, stnr, output, buf, len); 112 } 113 114 /* --------------------------------------------------------------------- */ 115 /* intel hda emulation */ 116 117 typedef struct IntelHDAStream IntelHDAStream; 118 typedef struct IntelHDAState IntelHDAState; 119 typedef struct IntelHDAReg IntelHDAReg; 120 121 typedef struct bpl { 122 uint64_t addr; 123 uint32_t len; 124 uint32_t flags; 125 } bpl; 126 127 struct IntelHDAStream { 128 /* registers */ 129 uint32_t ctl; 130 uint32_t lpib; 131 uint32_t cbl; 132 uint32_t lvi; 133 uint32_t fmt; 134 uint32_t bdlp_lbase; 135 uint32_t bdlp_ubase; 136 137 /* state */ 138 bpl *bpl; 139 uint32_t bentries; 140 uint32_t bsize, be, bp; 141 }; 142 143 struct IntelHDAState { 144 PCIDevice pci; 145 const char *name; 146 HDACodecBus codecs; 147 148 /* registers */ 149 uint32_t g_ctl; 150 uint32_t wake_en; 151 uint32_t state_sts; 152 uint32_t int_ctl; 153 uint32_t int_sts; 154 uint32_t wall_clk; 155 156 uint32_t corb_lbase; 157 uint32_t corb_ubase; 158 uint32_t corb_rp; 159 uint32_t corb_wp; 160 uint32_t corb_ctl; 161 uint32_t corb_sts; 162 uint32_t corb_size; 163 164 uint32_t rirb_lbase; 165 uint32_t rirb_ubase; 166 uint32_t rirb_wp; 167 uint32_t rirb_cnt; 168 uint32_t rirb_ctl; 169 uint32_t rirb_sts; 170 uint32_t rirb_size; 171 172 uint32_t dp_lbase; 173 uint32_t dp_ubase; 174 175 uint32_t icw; 176 uint32_t irr; 177 uint32_t ics; 178 179 /* streams */ 180 IntelHDAStream st[8]; 181 182 /* state */ 183 MemoryRegion container; 184 MemoryRegion mmio; 185 MemoryRegion alias; 186 uint32_t rirb_count; 187 int64_t wall_base_ns; 188 189 /* debug logging */ 190 const IntelHDAReg *last_reg; 191 uint32_t last_val; 192 uint32_t last_write; 193 uint32_t last_sec; 194 uint32_t repeat_count; 195 196 /* properties */ 197 uint32_t debug; 198 OnOffAuto msi; 199 bool old_msi_addr; 200 }; 201 202 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic" 203 204 DECLARE_INSTANCE_CHECKER(IntelHDAState, INTEL_HDA, 205 TYPE_INTEL_HDA_GENERIC) 206 207 struct IntelHDAReg { 208 const char *name; /* register name */ 209 uint32_t size; /* size in bytes */ 210 uint32_t reset; /* reset value */ 211 uint32_t wmask; /* write mask */ 212 uint32_t wclear; /* write 1 to clear bits */ 213 uint32_t offset; /* location in IntelHDAState */ 214 uint32_t shift; /* byte access entries for dwords */ 215 uint32_t stream; 216 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); 217 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); 218 }; 219 220 /* --------------------------------------------------------------------- */ 221 222 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) 223 { 224 return ((uint64_t)ubase << 32) | lbase; 225 } 226 227 static void intel_hda_update_int_sts(IntelHDAState *d) 228 { 229 uint32_t sts = 0; 230 uint32_t i; 231 232 /* update controller status */ 233 if (d->rirb_sts & ICH6_RBSTS_IRQ) { 234 sts |= (1 << 30); 235 } 236 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { 237 sts |= (1 << 30); 238 } 239 if (d->state_sts & d->wake_en) { 240 sts |= (1 << 30); 241 } 242 243 /* update stream status */ 244 for (i = 0; i < 8; i++) { 245 /* buffer completion interrupt */ 246 if (d->st[i].ctl & (1 << 26)) { 247 sts |= (1 << i); 248 } 249 } 250 251 /* update global status */ 252 if (sts & d->int_ctl) { 253 sts |= (1U << 31); 254 } 255 256 d->int_sts = sts; 257 } 258 259 static void intel_hda_update_irq(IntelHDAState *d) 260 { 261 bool msi = msi_enabled(&d->pci); 262 int level; 263 264 intel_hda_update_int_sts(d); 265 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { 266 level = 1; 267 } else { 268 level = 0; 269 } 270 dprint(d, 2, "%s: level %d [%s]\n", __func__, 271 level, msi ? "msi" : "intx"); 272 if (msi) { 273 if (level) { 274 msi_notify(&d->pci, 0); 275 } 276 } else { 277 pci_set_irq(&d->pci, level); 278 } 279 } 280 281 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) 282 { 283 uint32_t cad, nid, data; 284 HDACodecDevice *codec; 285 HDACodecDeviceClass *cdc; 286 287 cad = (verb >> 28) & 0x0f; 288 if (verb & (1 << 27)) { 289 /* indirect node addressing, not specified in HDA 1.0 */ 290 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__); 291 return -1; 292 } 293 nid = (verb >> 20) & 0x7f; 294 data = verb & 0xfffff; 295 296 codec = hda_codec_find(&d->codecs, cad); 297 if (codec == NULL) { 298 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); 299 return -1; 300 } 301 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); 302 cdc->command(codec, nid, data); 303 return 0; 304 } 305 306 static void intel_hda_corb_run(IntelHDAState *d) 307 { 308 hwaddr addr; 309 uint32_t rp, verb; 310 311 if (d->ics & ICH6_IRS_BUSY) { 312 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); 313 intel_hda_send_command(d, d->icw); 314 return; 315 } 316 317 for (;;) { 318 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { 319 dprint(d, 2, "%s: !run\n", __func__); 320 return; 321 } 322 if ((d->corb_rp & 0xff) == d->corb_wp) { 323 dprint(d, 2, "%s: corb ring empty\n", __func__); 324 return; 325 } 326 if (d->rirb_count == d->rirb_cnt) { 327 dprint(d, 2, "%s: rirb count reached\n", __func__); 328 return; 329 } 330 331 rp = (d->corb_rp + 1) & 0xff; 332 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); 333 ldl_le_pci_dma(&d->pci, addr + 4 * rp, &verb, MEMTXATTRS_UNSPECIFIED); 334 d->corb_rp = rp; 335 336 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); 337 intel_hda_send_command(d, verb); 338 } 339 } 340 341 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) 342 { 343 const MemTxAttrs attrs = { .memory = true }; 344 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 345 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 346 hwaddr addr; 347 uint32_t wp, ex; 348 MemTxResult res = MEMTX_OK; 349 350 if (d->ics & ICH6_IRS_BUSY) { 351 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", 352 __func__, response, dev->cad); 353 d->irr = response; 354 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); 355 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); 356 return; 357 } 358 359 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { 360 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__); 361 return; 362 } 363 364 ex = (solicited ? 0 : (1 << 4)) | dev->cad; 365 wp = (d->rirb_wp + 1) & 0xff; 366 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); 367 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs); 368 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs); 369 if (res != MEMTX_OK && (d->rirb_ctl & ICH6_RBCTL_OVERRUN_EN)) { 370 d->rirb_sts |= ICH6_RBSTS_OVERRUN; 371 intel_hda_update_irq(d); 372 } 373 d->rirb_wp = wp; 374 375 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", 376 __func__, wp, response, ex); 377 378 d->rirb_count++; 379 if (d->rirb_count == d->rirb_cnt) { 380 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); 381 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 382 d->rirb_sts |= ICH6_RBSTS_IRQ; 383 intel_hda_update_irq(d); 384 } 385 } else if ((d->corb_rp & 0xff) == d->corb_wp) { 386 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__, 387 d->rirb_count, d->rirb_cnt); 388 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 389 d->rirb_sts |= ICH6_RBSTS_IRQ; 390 intel_hda_update_irq(d); 391 } 392 } 393 } 394 395 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 396 uint8_t *buf, uint32_t len) 397 { 398 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 399 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 400 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 401 hwaddr addr; 402 uint32_t s, copy, left; 403 IntelHDAStream *st; 404 bool irq = false; 405 406 st = output ? d->st + 4 : d->st; 407 for (s = 0; s < 4; s++) { 408 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { 409 st = st + s; 410 break; 411 } 412 } 413 if (s == 4) { 414 return false; 415 } 416 if (st->bpl == NULL) { 417 return false; 418 } 419 420 left = len; 421 s = st->bentries; 422 while (left > 0 && s-- > 0) { 423 copy = left; 424 if (copy > st->bsize - st->lpib) 425 copy = st->bsize - st->lpib; 426 if (copy > st->bpl[st->be].len - st->bp) 427 copy = st->bpl[st->be].len - st->bp; 428 429 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", 430 st->be, st->bp, st->bpl[st->be].len, copy); 431 432 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output, 433 attrs); 434 st->lpib += copy; 435 st->bp += copy; 436 buf += copy; 437 left -= copy; 438 439 if (st->bpl[st->be].len == st->bp) { 440 /* bpl entry filled */ 441 if (st->bpl[st->be].flags & 0x01) { 442 irq = true; 443 } 444 st->bp = 0; 445 st->be++; 446 if (st->be == st->bentries) { 447 /* bpl wrap around */ 448 st->be = 0; 449 st->lpib = 0; 450 } 451 } 452 } 453 if (d->dp_lbase & 0x01) { 454 s = st - d->st; 455 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); 456 stl_le_pci_dma(&d->pci, addr + 8 * s, st->lpib, attrs); 457 } 458 dprint(d, 3, "dma: --\n"); 459 460 if (irq) { 461 st->ctl |= (1 << 26); /* buffer completion interrupt */ 462 intel_hda_update_irq(d); 463 } 464 return true; 465 } 466 467 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) 468 { 469 hwaddr addr; 470 uint8_t buf[16]; 471 uint32_t i; 472 473 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); 474 st->bentries = st->lvi +1; 475 g_free(st->bpl); 476 st->bpl = g_new(bpl, st->bentries); 477 for (i = 0; i < st->bentries; i++, addr += 16) { 478 pci_dma_read(&d->pci, addr, buf, 16); 479 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); 480 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); 481 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); 482 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", 483 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); 484 } 485 486 st->bsize = st->cbl; 487 st->lpib = 0; 488 st->be = 0; 489 st->bp = 0; 490 } 491 492 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) 493 { 494 BusChild *kid; 495 HDACodecDevice *cdev; 496 497 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 498 DeviceState *qdev = kid->child; 499 HDACodecDeviceClass *cdc; 500 501 cdev = HDA_CODEC_DEVICE(qdev); 502 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); 503 if (cdc->stream) { 504 cdc->stream(cdev, stream, running, output); 505 } 506 } 507 } 508 509 /* --------------------------------------------------------------------- */ 510 511 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 512 { 513 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { 514 device_cold_reset(DEVICE(d)); 515 } 516 } 517 518 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 519 { 520 intel_hda_update_irq(d); 521 } 522 523 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 524 { 525 intel_hda_update_irq(d); 526 } 527 528 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 529 { 530 intel_hda_update_irq(d); 531 } 532 533 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) 534 { 535 int64_t ns; 536 537 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; 538 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ 539 } 540 541 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 542 { 543 intel_hda_corb_run(d); 544 } 545 546 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 547 { 548 intel_hda_corb_run(d); 549 } 550 551 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 552 { 553 if (d->rirb_wp & ICH6_RIRBWP_RST) { 554 d->rirb_wp = 0; 555 } 556 } 557 558 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 559 { 560 intel_hda_update_irq(d); 561 562 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { 563 /* cleared ICH6_RBSTS_IRQ */ 564 d->rirb_count = 0; 565 intel_hda_corb_run(d); 566 } 567 } 568 569 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 570 { 571 if (d->ics & ICH6_IRS_BUSY) { 572 intel_hda_corb_run(d); 573 } 574 } 575 576 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 577 { 578 bool output = reg->stream >= 4; 579 IntelHDAStream *st = d->st + reg->stream; 580 581 if (st->ctl & 0x01) { 582 /* reset */ 583 dprint(d, 1, "st #%d: reset\n", reg->stream); 584 st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET; 585 } 586 if ((st->ctl & 0x02) != (old & 0x02)) { 587 uint32_t stnr = (st->ctl >> 20) & 0x0f; 588 /* run bit flipped */ 589 if (st->ctl & 0x02) { 590 /* start */ 591 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", 592 reg->stream, stnr, st->cbl); 593 intel_hda_parse_bdl(d, st); 594 intel_hda_notify_codecs(d, stnr, true, output); 595 } else { 596 /* stop */ 597 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); 598 intel_hda_notify_codecs(d, stnr, false, output); 599 } 600 } 601 intel_hda_update_irq(d); 602 } 603 604 /* --------------------------------------------------------------------- */ 605 606 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) 607 608 static const struct IntelHDAReg regtab[] = { 609 /* global */ 610 [ ICH6_REG_GCAP ] = { 611 .name = "GCAP", 612 .size = 2, 613 .reset = 0x4401, 614 }, 615 [ ICH6_REG_VMIN ] = { 616 .name = "VMIN", 617 .size = 1, 618 }, 619 [ ICH6_REG_VMAJ ] = { 620 .name = "VMAJ", 621 .size = 1, 622 .reset = 1, 623 }, 624 [ ICH6_REG_OUTPAY ] = { 625 .name = "OUTPAY", 626 .size = 2, 627 .reset = 0x3c, 628 }, 629 [ ICH6_REG_INPAY ] = { 630 .name = "INPAY", 631 .size = 2, 632 .reset = 0x1d, 633 }, 634 [ ICH6_REG_GCTL ] = { 635 .name = "GCTL", 636 .size = 4, 637 .wmask = 0x0103, 638 .offset = offsetof(IntelHDAState, g_ctl), 639 .whandler = intel_hda_set_g_ctl, 640 }, 641 [ ICH6_REG_WAKEEN ] = { 642 .name = "WAKEEN", 643 .size = 2, 644 .wmask = 0x7fff, 645 .offset = offsetof(IntelHDAState, wake_en), 646 .whandler = intel_hda_set_wake_en, 647 }, 648 [ ICH6_REG_STATESTS ] = { 649 .name = "STATESTS", 650 .size = 2, 651 .wmask = 0x7fff, 652 .wclear = 0x7fff, 653 .offset = offsetof(IntelHDAState, state_sts), 654 .whandler = intel_hda_set_state_sts, 655 }, 656 657 /* interrupts */ 658 [ ICH6_REG_INTCTL ] = { 659 .name = "INTCTL", 660 .size = 4, 661 .wmask = 0xc00000ff, 662 .offset = offsetof(IntelHDAState, int_ctl), 663 .whandler = intel_hda_set_int_ctl, 664 }, 665 [ ICH6_REG_INTSTS ] = { 666 .name = "INTSTS", 667 .size = 4, 668 .wmask = 0xc00000ff, 669 .wclear = 0xc00000ff, 670 .offset = offsetof(IntelHDAState, int_sts), 671 }, 672 673 /* misc */ 674 [ ICH6_REG_WALLCLK ] = { 675 .name = "WALLCLK", 676 .size = 4, 677 .offset = offsetof(IntelHDAState, wall_clk), 678 .rhandler = intel_hda_get_wall_clk, 679 }, 680 681 /* dma engine */ 682 [ ICH6_REG_CORBLBASE ] = { 683 .name = "CORBLBASE", 684 .size = 4, 685 .wmask = 0xffffff80, 686 .offset = offsetof(IntelHDAState, corb_lbase), 687 }, 688 [ ICH6_REG_CORBUBASE ] = { 689 .name = "CORBUBASE", 690 .size = 4, 691 .wmask = 0xffffffff, 692 .offset = offsetof(IntelHDAState, corb_ubase), 693 }, 694 [ ICH6_REG_CORBWP ] = { 695 .name = "CORBWP", 696 .size = 2, 697 .wmask = 0xff, 698 .offset = offsetof(IntelHDAState, corb_wp), 699 .whandler = intel_hda_set_corb_wp, 700 }, 701 [ ICH6_REG_CORBRP ] = { 702 .name = "CORBRP", 703 .size = 2, 704 .wmask = 0x80ff, 705 .offset = offsetof(IntelHDAState, corb_rp), 706 }, 707 [ ICH6_REG_CORBCTL ] = { 708 .name = "CORBCTL", 709 .size = 1, 710 .wmask = 0x03, 711 .offset = offsetof(IntelHDAState, corb_ctl), 712 .whandler = intel_hda_set_corb_ctl, 713 }, 714 [ ICH6_REG_CORBSTS ] = { 715 .name = "CORBSTS", 716 .size = 1, 717 .wmask = 0x01, 718 .wclear = 0x01, 719 .offset = offsetof(IntelHDAState, corb_sts), 720 }, 721 [ ICH6_REG_CORBSIZE ] = { 722 .name = "CORBSIZE", 723 .size = 1, 724 .reset = 0x42, 725 .offset = offsetof(IntelHDAState, corb_size), 726 }, 727 [ ICH6_REG_RIRBLBASE ] = { 728 .name = "RIRBLBASE", 729 .size = 4, 730 .wmask = 0xffffff80, 731 .offset = offsetof(IntelHDAState, rirb_lbase), 732 }, 733 [ ICH6_REG_RIRBUBASE ] = { 734 .name = "RIRBUBASE", 735 .size = 4, 736 .wmask = 0xffffffff, 737 .offset = offsetof(IntelHDAState, rirb_ubase), 738 }, 739 [ ICH6_REG_RIRBWP ] = { 740 .name = "RIRBWP", 741 .size = 2, 742 .wmask = 0x8000, 743 .offset = offsetof(IntelHDAState, rirb_wp), 744 .whandler = intel_hda_set_rirb_wp, 745 }, 746 [ ICH6_REG_RINTCNT ] = { 747 .name = "RINTCNT", 748 .size = 2, 749 .wmask = 0xff, 750 .offset = offsetof(IntelHDAState, rirb_cnt), 751 }, 752 [ ICH6_REG_RIRBCTL ] = { 753 .name = "RIRBCTL", 754 .size = 1, 755 .wmask = 0x07, 756 .offset = offsetof(IntelHDAState, rirb_ctl), 757 }, 758 [ ICH6_REG_RIRBSTS ] = { 759 .name = "RIRBSTS", 760 .size = 1, 761 .wmask = 0x05, 762 .wclear = 0x05, 763 .offset = offsetof(IntelHDAState, rirb_sts), 764 .whandler = intel_hda_set_rirb_sts, 765 }, 766 [ ICH6_REG_RIRBSIZE ] = { 767 .name = "RIRBSIZE", 768 .size = 1, 769 .reset = 0x42, 770 .offset = offsetof(IntelHDAState, rirb_size), 771 }, 772 773 [ ICH6_REG_DPLBASE ] = { 774 .name = "DPLBASE", 775 .size = 4, 776 .wmask = 0xffffff81, 777 .offset = offsetof(IntelHDAState, dp_lbase), 778 }, 779 [ ICH6_REG_DPUBASE ] = { 780 .name = "DPUBASE", 781 .size = 4, 782 .wmask = 0xffffffff, 783 .offset = offsetof(IntelHDAState, dp_ubase), 784 }, 785 786 [ ICH6_REG_IC ] = { 787 .name = "ICW", 788 .size = 4, 789 .wmask = 0xffffffff, 790 .offset = offsetof(IntelHDAState, icw), 791 }, 792 [ ICH6_REG_IR ] = { 793 .name = "IRR", 794 .size = 4, 795 .offset = offsetof(IntelHDAState, irr), 796 }, 797 [ ICH6_REG_IRS ] = { 798 .name = "ICS", 799 .size = 2, 800 .wmask = 0x0003, 801 .wclear = 0x0002, 802 .offset = offsetof(IntelHDAState, ics), 803 .whandler = intel_hda_set_ics, 804 }, 805 806 #define HDA_STREAM(_t, _i) \ 807 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ 808 .stream = _i, \ 809 .name = _t stringify(_i) " CTL", \ 810 .size = 4, \ 811 .wmask = 0x1cff001f, \ 812 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 813 .whandler = intel_hda_set_st_ctl, \ 814 }, \ 815 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ 816 .stream = _i, \ 817 .name = _t stringify(_i) " CTL(stnr)", \ 818 .size = 1, \ 819 .shift = 16, \ 820 .wmask = 0x00ff0000, \ 821 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 822 .whandler = intel_hda_set_st_ctl, \ 823 }, \ 824 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ 825 .stream = _i, \ 826 .name = _t stringify(_i) " CTL(sts)", \ 827 .size = 1, \ 828 .shift = 24, \ 829 .wmask = 0x1c000000, \ 830 .wclear = 0x1c000000, \ 831 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 832 .whandler = intel_hda_set_st_ctl, \ 833 .reset = SD_STS_FIFO_READY << 24 \ 834 }, \ 835 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ 836 .stream = _i, \ 837 .name = _t stringify(_i) " LPIB", \ 838 .size = 4, \ 839 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 840 }, \ 841 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ 842 .stream = _i, \ 843 .name = _t stringify(_i) " CBL", \ 844 .size = 4, \ 845 .wmask = 0xffffffff, \ 846 .offset = offsetof(IntelHDAState, st[_i].cbl), \ 847 }, \ 848 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ 849 .stream = _i, \ 850 .name = _t stringify(_i) " LVI", \ 851 .size = 2, \ 852 .wmask = 0x00ff, \ 853 .offset = offsetof(IntelHDAState, st[_i].lvi), \ 854 }, \ 855 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ 856 .stream = _i, \ 857 .name = _t stringify(_i) " FIFOS", \ 858 .size = 2, \ 859 .reset = HDA_BUFFER_SIZE, \ 860 }, \ 861 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ 862 .stream = _i, \ 863 .name = _t stringify(_i) " FMT", \ 864 .size = 2, \ 865 .wmask = 0x7f7f, \ 866 .offset = offsetof(IntelHDAState, st[_i].fmt), \ 867 }, \ 868 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ 869 .stream = _i, \ 870 .name = _t stringify(_i) " BDLPL", \ 871 .size = 4, \ 872 .wmask = 0xffffff80, \ 873 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ 874 }, \ 875 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ 876 .stream = _i, \ 877 .name = _t stringify(_i) " BDLPU", \ 878 .size = 4, \ 879 .wmask = 0xffffffff, \ 880 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ 881 }, \ 882 883 HDA_STREAM("IN", 0) 884 HDA_STREAM("IN", 1) 885 HDA_STREAM("IN", 2) 886 HDA_STREAM("IN", 3) 887 888 HDA_STREAM("OUT", 4) 889 HDA_STREAM("OUT", 5) 890 HDA_STREAM("OUT", 6) 891 HDA_STREAM("OUT", 7) 892 893 }; 894 895 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) 896 { 897 const IntelHDAReg *reg; 898 899 if (addr >= ARRAY_SIZE(regtab)) { 900 goto noreg; 901 } 902 reg = regtab+addr; 903 if (reg->name == NULL) { 904 goto noreg; 905 } 906 return reg; 907 908 noreg: 909 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); 910 return NULL; 911 } 912 913 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) 914 { 915 uint8_t *addr = (void*)d; 916 917 addr += reg->offset; 918 return (uint32_t*)addr; 919 } 920 921 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, 922 uint32_t wmask) 923 { 924 uint32_t *addr; 925 uint32_t old; 926 927 if (!reg) { 928 return; 929 } 930 if (!reg->wmask) { 931 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n", 932 reg->name); 933 return; 934 } 935 936 if (d->debug) { 937 time_t now = time(NULL); 938 if (d->last_write && d->last_reg == reg && d->last_val == val) { 939 d->repeat_count++; 940 if (d->last_sec != now) { 941 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 942 d->last_sec = now; 943 d->repeat_count = 0; 944 } 945 } else { 946 if (d->repeat_count) { 947 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 948 } 949 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); 950 d->last_write = 1; 951 d->last_reg = reg; 952 d->last_val = val; 953 d->last_sec = now; 954 d->repeat_count = 0; 955 } 956 } 957 assert(reg->offset != 0); 958 959 addr = intel_hda_reg_addr(d, reg); 960 old = *addr; 961 962 if (reg->shift) { 963 val <<= reg->shift; 964 wmask <<= reg->shift; 965 } 966 wmask &= reg->wmask; 967 *addr &= ~wmask; 968 *addr |= wmask & val; 969 *addr &= ~(val & reg->wclear); 970 971 if (reg->whandler) { 972 reg->whandler(d, reg, old); 973 } 974 } 975 976 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, 977 uint32_t rmask) 978 { 979 uint32_t *addr, ret; 980 981 if (!reg) { 982 return 0; 983 } 984 985 if (reg->rhandler) { 986 reg->rhandler(d, reg); 987 } 988 989 if (reg->offset == 0) { 990 /* constant read-only register */ 991 ret = reg->reset; 992 } else { 993 addr = intel_hda_reg_addr(d, reg); 994 ret = *addr; 995 if (reg->shift) { 996 ret >>= reg->shift; 997 } 998 ret &= rmask; 999 } 1000 if (d->debug) { 1001 time_t now = time(NULL); 1002 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { 1003 d->repeat_count++; 1004 if (d->last_sec != now) { 1005 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1006 d->last_sec = now; 1007 d->repeat_count = 0; 1008 } 1009 } else { 1010 if (d->repeat_count) { 1011 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1012 } 1013 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); 1014 d->last_write = 0; 1015 d->last_reg = reg; 1016 d->last_val = ret; 1017 d->last_sec = now; 1018 d->repeat_count = 0; 1019 } 1020 } 1021 return ret; 1022 } 1023 1024 static void intel_hda_regs_reset(IntelHDAState *d) 1025 { 1026 uint32_t *addr; 1027 int i; 1028 1029 for (i = 0; i < ARRAY_SIZE(regtab); i++) { 1030 if (regtab[i].name == NULL) { 1031 continue; 1032 } 1033 if (regtab[i].offset == 0) { 1034 continue; 1035 } 1036 addr = intel_hda_reg_addr(d, regtab + i); 1037 *addr = regtab[i].reset; 1038 } 1039 } 1040 1041 /* --------------------------------------------------------------------- */ 1042 1043 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val, 1044 unsigned size) 1045 { 1046 IntelHDAState *d = opaque; 1047 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1048 1049 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8)); 1050 } 1051 1052 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size) 1053 { 1054 IntelHDAState *d = opaque; 1055 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1056 1057 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8)); 1058 } 1059 1060 static const MemoryRegionOps intel_hda_mmio_ops = { 1061 .read = intel_hda_mmio_read, 1062 .write = intel_hda_mmio_write, 1063 .impl = { 1064 .min_access_size = 1, 1065 .max_access_size = 4, 1066 }, 1067 .endianness = DEVICE_NATIVE_ENDIAN, 1068 }; 1069 1070 /* --------------------------------------------------------------------- */ 1071 1072 static void intel_hda_reset(DeviceState *dev) 1073 { 1074 BusChild *kid; 1075 IntelHDAState *d = INTEL_HDA(dev); 1076 HDACodecDevice *cdev; 1077 1078 intel_hda_regs_reset(d); 1079 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1080 1081 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 1082 DeviceState *qdev = kid->child; 1083 cdev = HDA_CODEC_DEVICE(qdev); 1084 d->state_sts |= (1 << cdev->cad); 1085 } 1086 intel_hda_update_irq(d); 1087 } 1088 1089 static void intel_hda_realize(PCIDevice *pci, Error **errp) 1090 { 1091 IntelHDAState *d = INTEL_HDA(pci); 1092 uint8_t *conf = d->pci.config; 1093 Error *err = NULL; 1094 int ret; 1095 1096 d->name = object_get_typename(OBJECT(d)); 1097 1098 pci_config_set_interrupt_pin(conf, 1); 1099 1100 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ 1101 conf[0x40] = 0x01; 1102 1103 if (d->msi != ON_OFF_AUTO_OFF) { 1104 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1105 1, true, false, &err); 1106 /* Any error other than -ENOTSUP(board's MSI support is broken) 1107 * is a programming error */ 1108 assert(!ret || ret == -ENOTSUP); 1109 if (ret && d->msi == ON_OFF_AUTO_ON) { 1110 /* Can't satisfy user's explicit msi=on request, fail */ 1111 error_append_hint(&err, "You have to use msi=auto (default) or " 1112 "msi=off with this machine type.\n"); 1113 error_propagate(errp, err); 1114 return; 1115 } 1116 assert(!err || d->msi == ON_OFF_AUTO_AUTO); 1117 /* With msi=auto, we fall back to MSI off silently */ 1118 error_free(err); 1119 } 1120 1121 memory_region_init(&d->container, OBJECT(d), 1122 "intel-hda-container", 0x4000); 1123 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, 1124 "intel-hda", 0x2000); 1125 memory_region_add_subregion(&d->container, 0x0000, &d->mmio); 1126 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias", 1127 &d->mmio, 0, 0x2000); 1128 memory_region_add_subregion(&d->container, 0x2000, &d->alias); 1129 pci_register_bar(&d->pci, 0, 0, &d->container); 1130 1131 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), 1132 intel_hda_response, intel_hda_xfer); 1133 } 1134 1135 static void intel_hda_exit(PCIDevice *pci) 1136 { 1137 IntelHDAState *d = INTEL_HDA(pci); 1138 1139 msi_uninit(&d->pci); 1140 } 1141 1142 static int intel_hda_post_load(void *opaque, int version) 1143 { 1144 IntelHDAState* d = opaque; 1145 int i; 1146 1147 dprint(d, 1, "%s\n", __func__); 1148 for (i = 0; i < ARRAY_SIZE(d->st); i++) { 1149 if (d->st[i].ctl & 0x02) { 1150 intel_hda_parse_bdl(d, &d->st[i]); 1151 } 1152 } 1153 intel_hda_update_irq(d); 1154 return 0; 1155 } 1156 1157 static const VMStateDescription vmstate_intel_hda_stream = { 1158 .name = "intel-hda-stream", 1159 .version_id = 1, 1160 .fields = (const VMStateField[]) { 1161 VMSTATE_UINT32(ctl, IntelHDAStream), 1162 VMSTATE_UINT32(lpib, IntelHDAStream), 1163 VMSTATE_UINT32(cbl, IntelHDAStream), 1164 VMSTATE_UINT32(lvi, IntelHDAStream), 1165 VMSTATE_UINT32(fmt, IntelHDAStream), 1166 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), 1167 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), 1168 VMSTATE_END_OF_LIST() 1169 } 1170 }; 1171 1172 static const VMStateDescription vmstate_intel_hda = { 1173 .name = "intel-hda", 1174 .version_id = 1, 1175 .post_load = intel_hda_post_load, 1176 .fields = (const VMStateField[]) { 1177 VMSTATE_PCI_DEVICE(pci, IntelHDAState), 1178 1179 /* registers */ 1180 VMSTATE_UINT32(g_ctl, IntelHDAState), 1181 VMSTATE_UINT32(wake_en, IntelHDAState), 1182 VMSTATE_UINT32(state_sts, IntelHDAState), 1183 VMSTATE_UINT32(int_ctl, IntelHDAState), 1184 VMSTATE_UINT32(int_sts, IntelHDAState), 1185 VMSTATE_UINT32(wall_clk, IntelHDAState), 1186 VMSTATE_UINT32(corb_lbase, IntelHDAState), 1187 VMSTATE_UINT32(corb_ubase, IntelHDAState), 1188 VMSTATE_UINT32(corb_rp, IntelHDAState), 1189 VMSTATE_UINT32(corb_wp, IntelHDAState), 1190 VMSTATE_UINT32(corb_ctl, IntelHDAState), 1191 VMSTATE_UINT32(corb_sts, IntelHDAState), 1192 VMSTATE_UINT32(corb_size, IntelHDAState), 1193 VMSTATE_UINT32(rirb_lbase, IntelHDAState), 1194 VMSTATE_UINT32(rirb_ubase, IntelHDAState), 1195 VMSTATE_UINT32(rirb_wp, IntelHDAState), 1196 VMSTATE_UINT32(rirb_cnt, IntelHDAState), 1197 VMSTATE_UINT32(rirb_ctl, IntelHDAState), 1198 VMSTATE_UINT32(rirb_sts, IntelHDAState), 1199 VMSTATE_UINT32(rirb_size, IntelHDAState), 1200 VMSTATE_UINT32(dp_lbase, IntelHDAState), 1201 VMSTATE_UINT32(dp_ubase, IntelHDAState), 1202 VMSTATE_UINT32(icw, IntelHDAState), 1203 VMSTATE_UINT32(irr, IntelHDAState), 1204 VMSTATE_UINT32(ics, IntelHDAState), 1205 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, 1206 vmstate_intel_hda_stream, 1207 IntelHDAStream), 1208 1209 /* additional state info */ 1210 VMSTATE_UINT32(rirb_count, IntelHDAState), 1211 VMSTATE_INT64(wall_base_ns, IntelHDAState), 1212 1213 VMSTATE_END_OF_LIST() 1214 } 1215 }; 1216 1217 static const Property intel_hda_properties[] = { 1218 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), 1219 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO), 1220 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), 1221 }; 1222 1223 static void intel_hda_class_init(ObjectClass *klass, void *data) 1224 { 1225 DeviceClass *dc = DEVICE_CLASS(klass); 1226 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1227 1228 k->realize = intel_hda_realize; 1229 k->exit = intel_hda_exit; 1230 k->vendor_id = PCI_VENDOR_ID_INTEL; 1231 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1232 device_class_set_legacy_reset(dc, intel_hda_reset); 1233 dc->vmsd = &vmstate_intel_hda; 1234 device_class_set_props(dc, intel_hda_properties); 1235 } 1236 1237 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) 1238 { 1239 DeviceClass *dc = DEVICE_CLASS(klass); 1240 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1241 1242 k->device_id = 0x2668; 1243 k->revision = 1; 1244 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1245 dc->desc = "Intel HD Audio Controller (ich6)"; 1246 } 1247 1248 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) 1249 { 1250 DeviceClass *dc = DEVICE_CLASS(klass); 1251 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1252 1253 k->device_id = 0x293e; 1254 k->revision = 3; 1255 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1256 dc->desc = "Intel HD Audio Controller (ich9)"; 1257 } 1258 1259 static const TypeInfo intel_hda_info = { 1260 .name = TYPE_INTEL_HDA_GENERIC, 1261 .parent = TYPE_PCI_DEVICE, 1262 .instance_size = sizeof(IntelHDAState), 1263 .class_init = intel_hda_class_init, 1264 .abstract = true, 1265 .interfaces = (InterfaceInfo[]) { 1266 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1267 { }, 1268 }, 1269 }; 1270 1271 static const TypeInfo intel_hda_info_ich6 = { 1272 .name = "intel-hda", 1273 .parent = TYPE_INTEL_HDA_GENERIC, 1274 .class_init = intel_hda_class_init_ich6, 1275 }; 1276 1277 static const TypeInfo intel_hda_info_ich9 = { 1278 .name = "ich9-intel-hda", 1279 .parent = TYPE_INTEL_HDA_GENERIC, 1280 .class_init = intel_hda_class_init_ich9, 1281 }; 1282 1283 static void hda_codec_device_class_init(ObjectClass *klass, void *data) 1284 { 1285 DeviceClass *k = DEVICE_CLASS(klass); 1286 k->realize = hda_codec_dev_realize; 1287 k->unrealize = hda_codec_dev_unrealize; 1288 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1289 k->bus_type = TYPE_HDA_BUS; 1290 device_class_set_props(k, hda_props); 1291 } 1292 1293 static const TypeInfo hda_codec_device_type_info = { 1294 .name = TYPE_HDA_CODEC_DEVICE, 1295 .parent = TYPE_DEVICE, 1296 .instance_size = sizeof(HDACodecDevice), 1297 .abstract = true, 1298 .class_size = sizeof(HDACodecDeviceClass), 1299 .class_init = hda_codec_device_class_init, 1300 }; 1301 1302 /* 1303 * create intel hda controller with codec attached to it, 1304 * so '-soundhw hda' works. 1305 */ 1306 static int intel_hda_and_codec_init(PCIBus *bus, const char *audiodev) 1307 { 1308 DeviceState *controller; 1309 BusState *hdabus; 1310 DeviceState *codec; 1311 1312 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1313 hdabus = QLIST_FIRST(&controller->child_bus); 1314 codec = qdev_new("hda-duplex"); 1315 qdev_prop_set_string(codec, "audiodev", audiodev); 1316 qdev_realize_and_unref(codec, hdabus, &error_fatal); 1317 return 0; 1318 } 1319 1320 static void intel_hda_register_types(void) 1321 { 1322 type_register_static(&hda_codec_bus_info); 1323 type_register_static(&intel_hda_info); 1324 type_register_static(&intel_hda_info_ich6); 1325 type_register_static(&intel_hda_info_ich9); 1326 type_register_static(&hda_codec_device_type_info); 1327 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init); 1328 } 1329 1330 type_init(intel_hda_register_types) 1331