1e5c9a13eSbalrog /* 2e5c9a13eSbalrog * Copyright (C) 2006 InnoTek Systemberatung GmbH 3e5c9a13eSbalrog * 4e5c9a13eSbalrog * This file is part of VirtualBox Open Source Edition (OSE), as 5e5c9a13eSbalrog * available from http://www.virtualbox.org. This file is free software; 6e5c9a13eSbalrog * you can redistribute it and/or modify it under the terms of the GNU 7e5c9a13eSbalrog * General Public License as published by the Free Software Foundation, 8e5c9a13eSbalrog * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE 9e5c9a13eSbalrog * distribution. VirtualBox OSE is distributed in the hope that it will 10e5c9a13eSbalrog * be useful, but WITHOUT ANY WARRANTY of any kind. 11e5c9a13eSbalrog * 12e5c9a13eSbalrog * If you received this file as part of a commercial VirtualBox 13e5c9a13eSbalrog * distribution, then only the terms of your commercial VirtualBox 14e5c9a13eSbalrog * license agreement apply instead of the previous paragraph. 156b620ca3SPaolo Bonzini * 166b620ca3SPaolo Bonzini * Contributions after 2012-01-13 are licensed under the terms of the 176b620ca3SPaolo Bonzini * GNU GPL, version 2 or (at your option) any later version. 18e5c9a13eSbalrog */ 19e5c9a13eSbalrog 206086a565SPeter Maydell #include "qemu/osdep.h" 2183c9f4caSPaolo Bonzini #include "hw/hw.h" 228a824e4dSEduardo Habkost #include "hw/audio/soundhw.h" 23e5c9a13eSbalrog #include "audio/audio.h" 2483c9f4caSPaolo Bonzini #include "hw/pci/pci.h" 259c17d615SPaolo Bonzini #include "sysemu/dma.h" 26e5c9a13eSbalrog 27e5c9a13eSbalrog enum { 28e5c9a13eSbalrog AC97_Reset = 0x00, 29e5c9a13eSbalrog AC97_Master_Volume_Mute = 0x02, 30e5c9a13eSbalrog AC97_Headphone_Volume_Mute = 0x04, 31e5c9a13eSbalrog AC97_Master_Volume_Mono_Mute = 0x06, 32e5c9a13eSbalrog AC97_Master_Tone_RL = 0x08, 33e5c9a13eSbalrog AC97_PC_BEEP_Volume_Mute = 0x0A, 34e5c9a13eSbalrog AC97_Phone_Volume_Mute = 0x0C, 35e5c9a13eSbalrog AC97_Mic_Volume_Mute = 0x0E, 36e5c9a13eSbalrog AC97_Line_In_Volume_Mute = 0x10, 37e5c9a13eSbalrog AC97_CD_Volume_Mute = 0x12, 38e5c9a13eSbalrog AC97_Video_Volume_Mute = 0x14, 39e5c9a13eSbalrog AC97_Aux_Volume_Mute = 0x16, 40e5c9a13eSbalrog AC97_PCM_Out_Volume_Mute = 0x18, 41e5c9a13eSbalrog AC97_Record_Select = 0x1A, 42e5c9a13eSbalrog AC97_Record_Gain_Mute = 0x1C, 43e5c9a13eSbalrog AC97_Record_Gain_Mic_Mute = 0x1E, 44e5c9a13eSbalrog AC97_General_Purpose = 0x20, 45e5c9a13eSbalrog AC97_3D_Control = 0x22, 46e5c9a13eSbalrog AC97_AC_97_RESERVED = 0x24, 47e5c9a13eSbalrog AC97_Powerdown_Ctrl_Stat = 0x26, 48e5c9a13eSbalrog AC97_Extended_Audio_ID = 0x28, 49e5c9a13eSbalrog AC97_Extended_Audio_Ctrl_Stat = 0x2A, 50e5c9a13eSbalrog AC97_PCM_Front_DAC_Rate = 0x2C, 51e5c9a13eSbalrog AC97_PCM_Surround_DAC_Rate = 0x2E, 52e5c9a13eSbalrog AC97_PCM_LFE_DAC_Rate = 0x30, 53e5c9a13eSbalrog AC97_PCM_LR_ADC_Rate = 0x32, 54e5c9a13eSbalrog AC97_MIC_ADC_Rate = 0x34, 55e5c9a13eSbalrog AC97_6Ch_Vol_C_LFE_Mute = 0x36, 56e5c9a13eSbalrog AC97_6Ch_Vol_L_R_Surround_Mute = 0x38, 57e5c9a13eSbalrog AC97_Vendor_Reserved = 0x58, 58d044be37SHans de Goede AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */ 59d044be37SHans de Goede AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */ 60e5c9a13eSbalrog AC97_Vendor_ID1 = 0x7c, 61e5c9a13eSbalrog AC97_Vendor_ID2 = 0x7e 62e5c9a13eSbalrog }; 63e5c9a13eSbalrog 64e5c9a13eSbalrog #define SOFT_VOLUME 65e5c9a13eSbalrog #define SR_FIFOE 16 /* rwc */ 66e5c9a13eSbalrog #define SR_BCIS 8 /* rwc */ 67e5c9a13eSbalrog #define SR_LVBCI 4 /* rwc */ 68e5c9a13eSbalrog #define SR_CELV 2 /* ro */ 69e5c9a13eSbalrog #define SR_DCH 1 /* ro */ 70e5c9a13eSbalrog #define SR_VALID_MASK ((1 << 5) - 1) 71e5c9a13eSbalrog #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 72e5c9a13eSbalrog #define SR_RO_MASK (SR_DCH | SR_CELV) 73e5c9a13eSbalrog #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 74e5c9a13eSbalrog 75e5c9a13eSbalrog #define CR_IOCE 16 /* rw */ 76e5c9a13eSbalrog #define CR_FEIE 8 /* rw */ 77e5c9a13eSbalrog #define CR_LVBIE 4 /* rw */ 78e5c9a13eSbalrog #define CR_RR 2 /* rw */ 79e5c9a13eSbalrog #define CR_RPBM 1 /* rw */ 80e5c9a13eSbalrog #define CR_VALID_MASK ((1 << 5) - 1) 81e5c9a13eSbalrog #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE) 82e5c9a13eSbalrog 83e5c9a13eSbalrog #define GC_WR 4 /* rw */ 84e5c9a13eSbalrog #define GC_CR 2 /* rw */ 85e5c9a13eSbalrog #define GC_VALID_MASK ((1 << 6) - 1) 86e5c9a13eSbalrog 87e5c9a13eSbalrog #define GS_MD3 (1<<17) /* rw */ 88e5c9a13eSbalrog #define GS_AD3 (1<<16) /* rw */ 89e5c9a13eSbalrog #define GS_RCS (1<<15) /* rwc */ 90e5c9a13eSbalrog #define GS_B3S12 (1<<14) /* ro */ 91e5c9a13eSbalrog #define GS_B2S12 (1<<13) /* ro */ 92e5c9a13eSbalrog #define GS_B1S12 (1<<12) /* ro */ 93e5c9a13eSbalrog #define GS_S1R1 (1<<11) /* rwc */ 94e5c9a13eSbalrog #define GS_S0R1 (1<<10) /* rwc */ 95e5c9a13eSbalrog #define GS_S1CR (1<<9) /* ro */ 96e5c9a13eSbalrog #define GS_S0CR (1<<8) /* ro */ 97e5c9a13eSbalrog #define GS_MINT (1<<7) /* ro */ 98e5c9a13eSbalrog #define GS_POINT (1<<6) /* ro */ 99e5c9a13eSbalrog #define GS_PIINT (1<<5) /* ro */ 100e5c9a13eSbalrog #define GS_RSRVD ((1<<4)|(1<<3)) 101e5c9a13eSbalrog #define GS_MOINT (1<<2) /* ro */ 102e5c9a13eSbalrog #define GS_MIINT (1<<1) /* ro */ 103e5c9a13eSbalrog #define GS_GSCI 1 /* rwc */ 104e5c9a13eSbalrog #define GS_RO_MASK (GS_B3S12| \ 105e5c9a13eSbalrog GS_B2S12| \ 106e5c9a13eSbalrog GS_B1S12| \ 107e5c9a13eSbalrog GS_S1CR| \ 108e5c9a13eSbalrog GS_S0CR| \ 109e5c9a13eSbalrog GS_MINT| \ 110e5c9a13eSbalrog GS_POINT| \ 111e5c9a13eSbalrog GS_PIINT| \ 112e5c9a13eSbalrog GS_RSRVD| \ 113e5c9a13eSbalrog GS_MOINT| \ 114e5c9a13eSbalrog GS_MIINT) 115e5c9a13eSbalrog #define GS_VALID_MASK ((1 << 18) - 1) 116e5c9a13eSbalrog #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI) 117e5c9a13eSbalrog 118e5c9a13eSbalrog #define BD_IOC (1<<31) 119e5c9a13eSbalrog #define BD_BUP (1<<30) 120e5c9a13eSbalrog 121e5c9a13eSbalrog #define EACS_VRA 1 122e5c9a13eSbalrog #define EACS_VRM 8 123e5c9a13eSbalrog 124e5c9a13eSbalrog #define MUTE_SHIFT 15 125e5c9a13eSbalrog 126*417d430eSLi Qiang #define TYPE_AC97 "AC97" 127*417d430eSLi Qiang #define AC97(obj) \ 128*417d430eSLi Qiang OBJECT_CHECK(AC97LinkState, (obj), TYPE_AC97) 129*417d430eSLi Qiang 130e5c9a13eSbalrog #define REC_MASK 7 131e5c9a13eSbalrog enum { 132e5c9a13eSbalrog REC_MIC = 0, 133e5c9a13eSbalrog REC_CD, 134e5c9a13eSbalrog REC_VIDEO, 135e5c9a13eSbalrog REC_AUX, 136e5c9a13eSbalrog REC_LINE_IN, 137e5c9a13eSbalrog REC_STEREO_MIX, 138e5c9a13eSbalrog REC_MONO_MIX, 139e5c9a13eSbalrog REC_PHONE 140e5c9a13eSbalrog }; 141e5c9a13eSbalrog 142e5c9a13eSbalrog typedef struct BD { 143e5c9a13eSbalrog uint32_t addr; 144e5c9a13eSbalrog uint32_t ctl_len; 145e5c9a13eSbalrog } BD; 146e5c9a13eSbalrog 147e5c9a13eSbalrog typedef struct AC97BusMasterRegs { 148e5c9a13eSbalrog uint32_t bdbar; /* rw 0 */ 149e5c9a13eSbalrog uint8_t civ; /* ro 0 */ 150e5c9a13eSbalrog uint8_t lvi; /* rw 0 */ 151e5c9a13eSbalrog uint16_t sr; /* rw 1 */ 152e5c9a13eSbalrog uint16_t picb; /* ro 0 */ 153e5c9a13eSbalrog uint8_t piv; /* ro 0 */ 154e5c9a13eSbalrog uint8_t cr; /* rw 0 */ 155e5c9a13eSbalrog unsigned int bd_valid; 156e5c9a13eSbalrog BD bd; 157e5c9a13eSbalrog } AC97BusMasterRegs; 158e5c9a13eSbalrog 159e5c9a13eSbalrog typedef struct AC97LinkState { 16010ee2aaaSJuan Quintela PCIDevice dev; 161e5c9a13eSbalrog QEMUSoundCard card; 16225a21c94SGerd Hoffmann uint32_t use_broken_id; 163e5c9a13eSbalrog uint32_t glob_cnt; 164e5c9a13eSbalrog uint32_t glob_sta; 165e5c9a13eSbalrog uint32_t cas; 166e5c9a13eSbalrog uint32_t last_samp; 167e5c9a13eSbalrog AC97BusMasterRegs bm_regs[3]; 168e5c9a13eSbalrog uint8_t mixer_data[256]; 169e5c9a13eSbalrog SWVoiceIn *voice_pi; 170e5c9a13eSbalrog SWVoiceOut *voice_po; 171e5c9a13eSbalrog SWVoiceIn *voice_mc; 1722c44375dSmalc int invalid_freq[3]; 173e5c9a13eSbalrog uint8_t silence[128]; 174e5c9a13eSbalrog int bup_flag; 17583c406d9SAvi Kivity MemoryRegion io_nam; 17683c406d9SAvi Kivity MemoryRegion io_nabm; 177e5c9a13eSbalrog } AC97LinkState; 178e5c9a13eSbalrog 179e5c9a13eSbalrog enum { 180e5c9a13eSbalrog BUP_SET = 1, 181e5c9a13eSbalrog BUP_LAST = 2 182e5c9a13eSbalrog }; 183e5c9a13eSbalrog 184e5c9a13eSbalrog #ifdef DEBUG_AC97 185e5c9a13eSbalrog #define dolog(...) AUD_log ("ac97", __VA_ARGS__) 186e5c9a13eSbalrog #else 187e5c9a13eSbalrog #define dolog(...) 188e5c9a13eSbalrog #endif 189e5c9a13eSbalrog 190e5c9a13eSbalrog #define MKREGS(prefix, start) \ 191e5c9a13eSbalrog enum { \ 192e5c9a13eSbalrog prefix ## _BDBAR = start, \ 193e5c9a13eSbalrog prefix ## _CIV = start + 4, \ 194e5c9a13eSbalrog prefix ## _LVI = start + 5, \ 195e5c9a13eSbalrog prefix ## _SR = start + 6, \ 196e5c9a13eSbalrog prefix ## _PICB = start + 8, \ 197e5c9a13eSbalrog prefix ## _PIV = start + 10, \ 198e5c9a13eSbalrog prefix ## _CR = start + 11 \ 199e5c9a13eSbalrog } 200e5c9a13eSbalrog 201e5c9a13eSbalrog enum { 202e5c9a13eSbalrog PI_INDEX = 0, 203e5c9a13eSbalrog PO_INDEX, 204e5c9a13eSbalrog MC_INDEX, 205e5c9a13eSbalrog LAST_INDEX 206e5c9a13eSbalrog }; 207e5c9a13eSbalrog 208e5c9a13eSbalrog MKREGS (PI, PI_INDEX * 16); 209e5c9a13eSbalrog MKREGS (PO, PO_INDEX * 16); 210e5c9a13eSbalrog MKREGS (MC, MC_INDEX * 16); 211e5c9a13eSbalrog 212e5c9a13eSbalrog enum { 213e5c9a13eSbalrog GLOB_CNT = 0x2c, 214e5c9a13eSbalrog GLOB_STA = 0x30, 215e5c9a13eSbalrog CAS = 0x34 216e5c9a13eSbalrog }; 217e5c9a13eSbalrog 218e5c9a13eSbalrog #define GET_BM(index) (((index) >> 4) & 3) 219e5c9a13eSbalrog 220e5c9a13eSbalrog static void po_callback (void *opaque, int free); 221e5c9a13eSbalrog static void pi_callback (void *opaque, int avail); 222e5c9a13eSbalrog static void mc_callback (void *opaque, int avail); 223e5c9a13eSbalrog 224e5c9a13eSbalrog static void warm_reset (AC97LinkState *s) 225e5c9a13eSbalrog { 226e5c9a13eSbalrog (void) s; 227e5c9a13eSbalrog } 228e5c9a13eSbalrog 229e5c9a13eSbalrog static void cold_reset (AC97LinkState * s) 230e5c9a13eSbalrog { 231e5c9a13eSbalrog (void) s; 232e5c9a13eSbalrog } 233e5c9a13eSbalrog 234e5c9a13eSbalrog static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r) 235e5c9a13eSbalrog { 236e5c9a13eSbalrog uint8_t b[8]; 237e5c9a13eSbalrog 23893f43c48SEduard - Gabriel Munteanu pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8); 239e5c9a13eSbalrog r->bd_valid = 1; 240e5c9a13eSbalrog r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3; 241e5c9a13eSbalrog r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]); 242e5c9a13eSbalrog r->picb = r->bd.ctl_len & 0xffff; 243e5c9a13eSbalrog dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n", 244e5c9a13eSbalrog r->civ, r->bd.addr, r->bd.ctl_len >> 16, 245e5c9a13eSbalrog r->bd.ctl_len & 0xffff, 246e5c9a13eSbalrog (r->bd.ctl_len & 0xffff) << 1); 247e5c9a13eSbalrog } 248e5c9a13eSbalrog 249e5c9a13eSbalrog static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr) 250e5c9a13eSbalrog { 251e5c9a13eSbalrog int event = 0; 252e5c9a13eSbalrog int level = 0; 253e5c9a13eSbalrog uint32_t new_mask = new_sr & SR_INT_MASK; 254e5c9a13eSbalrog uint32_t old_mask = r->sr & SR_INT_MASK; 255e5c9a13eSbalrog uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT}; 256e5c9a13eSbalrog 257e5c9a13eSbalrog if (new_mask ^ old_mask) { 258e5c9a13eSbalrog /** @todo is IRQ deasserted when only one of status bits is cleared? */ 259e5c9a13eSbalrog if (!new_mask) { 260e5c9a13eSbalrog event = 1; 261e5c9a13eSbalrog level = 0; 262e5c9a13eSbalrog } 263e5c9a13eSbalrog else { 264e5c9a13eSbalrog if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) { 265e5c9a13eSbalrog event = 1; 266e5c9a13eSbalrog level = 1; 267e5c9a13eSbalrog } 268e5c9a13eSbalrog if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) { 269e5c9a13eSbalrog event = 1; 270e5c9a13eSbalrog level = 1; 271e5c9a13eSbalrog } 272e5c9a13eSbalrog } 273e5c9a13eSbalrog } 274e5c9a13eSbalrog 275e5c9a13eSbalrog r->sr = new_sr; 276e5c9a13eSbalrog 277e5c9a13eSbalrog dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n", 278e5c9a13eSbalrog r->sr & SR_BCIS, r->sr & SR_LVBCI, 279e5c9a13eSbalrog r->sr, 280e5c9a13eSbalrog event, level); 281e5c9a13eSbalrog 282e5c9a13eSbalrog if (!event) 283e5c9a13eSbalrog return; 284e5c9a13eSbalrog 285e5c9a13eSbalrog if (level) { 286e5c9a13eSbalrog s->glob_sta |= masks[r - s->bm_regs]; 287e5c9a13eSbalrog dolog ("set irq level=1\n"); 2889e64f8a3SMarcel Apfelbaum pci_irq_assert(&s->dev); 289e5c9a13eSbalrog } 290e5c9a13eSbalrog else { 291e5c9a13eSbalrog s->glob_sta &= ~masks[r - s->bm_regs]; 292e5c9a13eSbalrog dolog ("set irq level=0\n"); 2939e64f8a3SMarcel Apfelbaum pci_irq_deassert(&s->dev); 294e5c9a13eSbalrog } 295e5c9a13eSbalrog } 296e5c9a13eSbalrog 297e5c9a13eSbalrog static void voice_set_active (AC97LinkState *s, int bm_index, int on) 298e5c9a13eSbalrog { 299e5c9a13eSbalrog switch (bm_index) { 300e5c9a13eSbalrog case PI_INDEX: 301e5c9a13eSbalrog AUD_set_active_in (s->voice_pi, on); 302e5c9a13eSbalrog break; 303e5c9a13eSbalrog 304e5c9a13eSbalrog case PO_INDEX: 305e5c9a13eSbalrog AUD_set_active_out (s->voice_po, on); 306e5c9a13eSbalrog break; 307e5c9a13eSbalrog 308e5c9a13eSbalrog case MC_INDEX: 309e5c9a13eSbalrog AUD_set_active_in (s->voice_mc, on); 310e5c9a13eSbalrog break; 311e5c9a13eSbalrog 312e5c9a13eSbalrog default: 313e5c9a13eSbalrog AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index); 314e5c9a13eSbalrog break; 315e5c9a13eSbalrog } 316e5c9a13eSbalrog } 317e5c9a13eSbalrog 318e5c9a13eSbalrog static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r) 319e5c9a13eSbalrog { 320e5c9a13eSbalrog dolog ("reset_bm_regs\n"); 321e5c9a13eSbalrog r->bdbar = 0; 322e5c9a13eSbalrog r->civ = 0; 323e5c9a13eSbalrog r->lvi = 0; 324e5c9a13eSbalrog /** todo do we need to do that? */ 325e5c9a13eSbalrog update_sr (s, r, SR_DCH); 326e5c9a13eSbalrog r->picb = 0; 327e5c9a13eSbalrog r->piv = 0; 328e5c9a13eSbalrog r->cr = r->cr & CR_DONT_CLEAR_MASK; 329e5c9a13eSbalrog r->bd_valid = 0; 330e5c9a13eSbalrog 331e5c9a13eSbalrog voice_set_active (s, r - s->bm_regs, 0); 332e5c9a13eSbalrog memset (s->silence, 0, sizeof (s->silence)); 333e5c9a13eSbalrog } 334e5c9a13eSbalrog 335e5c9a13eSbalrog static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v) 336e5c9a13eSbalrog { 337e5c9a13eSbalrog if (i + 2 > sizeof (s->mixer_data)) { 3380148d177SJuan Quintela dolog ("mixer_store: index %d out of bounds %zd\n", 339e5c9a13eSbalrog i, sizeof (s->mixer_data)); 340e5c9a13eSbalrog return; 341e5c9a13eSbalrog } 342e5c9a13eSbalrog 343e5c9a13eSbalrog s->mixer_data[i + 0] = v & 0xff; 344e5c9a13eSbalrog s->mixer_data[i + 1] = v >> 8; 345e5c9a13eSbalrog } 346e5c9a13eSbalrog 347e5c9a13eSbalrog static uint16_t mixer_load (AC97LinkState *s, uint32_t i) 348e5c9a13eSbalrog { 349e5c9a13eSbalrog uint16_t val = 0xffff; 350e5c9a13eSbalrog 351e5c9a13eSbalrog if (i + 2 > sizeof (s->mixer_data)) { 352a4e652ebSHans de Goede dolog ("mixer_load: index %d out of bounds %zd\n", 353e5c9a13eSbalrog i, sizeof (s->mixer_data)); 354e5c9a13eSbalrog } 355e5c9a13eSbalrog else { 356e5c9a13eSbalrog val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8); 357e5c9a13eSbalrog } 358e5c9a13eSbalrog 359e5c9a13eSbalrog return val; 360e5c9a13eSbalrog } 361e5c9a13eSbalrog 362e5c9a13eSbalrog static void open_voice (AC97LinkState *s, int index, int freq) 363e5c9a13eSbalrog { 3641ea879e5Smalc struct audsettings as; 365e5c9a13eSbalrog 366e5c9a13eSbalrog as.freq = freq; 367e5c9a13eSbalrog as.nchannels = 2; 368e5c9a13eSbalrog as.fmt = AUD_FMT_S16; 369e5c9a13eSbalrog as.endianness = 0; 370e5c9a13eSbalrog 3712c44375dSmalc if (freq > 0) { 3722c44375dSmalc s->invalid_freq[index] = 0; 373e5c9a13eSbalrog switch (index) { 374e5c9a13eSbalrog case PI_INDEX: 375e5c9a13eSbalrog s->voice_pi = AUD_open_in ( 376e5c9a13eSbalrog &s->card, 377e5c9a13eSbalrog s->voice_pi, 378e5c9a13eSbalrog "ac97.pi", 379e5c9a13eSbalrog s, 380e5c9a13eSbalrog pi_callback, 381e5c9a13eSbalrog &as 382e5c9a13eSbalrog ); 383e5c9a13eSbalrog break; 384e5c9a13eSbalrog 385e5c9a13eSbalrog case PO_INDEX: 386e5c9a13eSbalrog s->voice_po = AUD_open_out ( 387e5c9a13eSbalrog &s->card, 388e5c9a13eSbalrog s->voice_po, 389e5c9a13eSbalrog "ac97.po", 390e5c9a13eSbalrog s, 391e5c9a13eSbalrog po_callback, 392e5c9a13eSbalrog &as 393e5c9a13eSbalrog ); 394e5c9a13eSbalrog break; 395e5c9a13eSbalrog 396e5c9a13eSbalrog case MC_INDEX: 397e5c9a13eSbalrog s->voice_mc = AUD_open_in ( 398e5c9a13eSbalrog &s->card, 399e5c9a13eSbalrog s->voice_mc, 400e5c9a13eSbalrog "ac97.mc", 401e5c9a13eSbalrog s, 402e5c9a13eSbalrog mc_callback, 403e5c9a13eSbalrog &as 404e5c9a13eSbalrog ); 405e5c9a13eSbalrog break; 406e5c9a13eSbalrog } 407e5c9a13eSbalrog } 4082c44375dSmalc else { 4092c44375dSmalc s->invalid_freq[index] = freq; 4102c44375dSmalc switch (index) { 4112c44375dSmalc case PI_INDEX: 4122c44375dSmalc AUD_close_in (&s->card, s->voice_pi); 4132c44375dSmalc s->voice_pi = NULL; 4142c44375dSmalc break; 4152c44375dSmalc 4162c44375dSmalc case PO_INDEX: 4172c44375dSmalc AUD_close_out (&s->card, s->voice_po); 4182c44375dSmalc s->voice_po = NULL; 4192c44375dSmalc break; 4202c44375dSmalc 4212c44375dSmalc case MC_INDEX: 4222c44375dSmalc AUD_close_in (&s->card, s->voice_mc); 4232c44375dSmalc s->voice_mc = NULL; 4242c44375dSmalc break; 4252c44375dSmalc } 4262c44375dSmalc } 4272c44375dSmalc } 428e5c9a13eSbalrog 429e5c9a13eSbalrog static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX]) 430e5c9a13eSbalrog { 431e5c9a13eSbalrog uint16_t freq; 432e5c9a13eSbalrog 433e5c9a13eSbalrog freq = mixer_load (s, AC97_PCM_LR_ADC_Rate); 434e5c9a13eSbalrog open_voice (s, PI_INDEX, freq); 435e5c9a13eSbalrog AUD_set_active_in (s->voice_pi, active[PI_INDEX]); 436e5c9a13eSbalrog 437e5c9a13eSbalrog freq = mixer_load (s, AC97_PCM_Front_DAC_Rate); 438e5c9a13eSbalrog open_voice (s, PO_INDEX, freq); 439e5c9a13eSbalrog AUD_set_active_out (s->voice_po, active[PO_INDEX]); 440e5c9a13eSbalrog 441e5c9a13eSbalrog freq = mixer_load (s, AC97_MIC_ADC_Rate); 442e5c9a13eSbalrog open_voice (s, MC_INDEX, freq); 443e5c9a13eSbalrog AUD_set_active_in (s->voice_mc, active[MC_INDEX]); 444e5c9a13eSbalrog } 445e5c9a13eSbalrog 44619677a38SMarc-André Lureau static void get_volume (uint16_t vol, uint16_t mask, int inverse, 44719677a38SMarc-André Lureau int *mute, uint8_t *lvol, uint8_t *rvol) 44819677a38SMarc-André Lureau { 44919677a38SMarc-André Lureau *mute = (vol >> MUTE_SHIFT) & 1; 45019677a38SMarc-André Lureau *rvol = (255 * (vol & mask)) / mask; 45119677a38SMarc-André Lureau *lvol = (255 * ((vol >> 8) & mask)) / mask; 45219677a38SMarc-André Lureau 45319677a38SMarc-André Lureau if (inverse) { 45419677a38SMarc-André Lureau *rvol = 255 - *rvol; 45519677a38SMarc-André Lureau *lvol = 255 - *lvol; 45619677a38SMarc-André Lureau } 45719677a38SMarc-André Lureau } 45819677a38SMarc-André Lureau 45919677a38SMarc-André Lureau static void update_combined_volume_out (AC97LinkState *s) 46019677a38SMarc-André Lureau { 46119677a38SMarc-André Lureau uint8_t lvol, rvol, plvol, prvol; 46219677a38SMarc-André Lureau int mute, pmute; 46319677a38SMarc-André Lureau 46419677a38SMarc-André Lureau get_volume (mixer_load (s, AC97_Master_Volume_Mute), 0x3f, 1, 46519677a38SMarc-André Lureau &mute, &lvol, &rvol); 4667873bfb8SHans de Goede get_volume (mixer_load (s, AC97_PCM_Out_Volume_Mute), 0x1f, 1, 46719677a38SMarc-André Lureau &pmute, &plvol, &prvol); 46819677a38SMarc-André Lureau 46919677a38SMarc-André Lureau mute = mute | pmute; 47019677a38SMarc-André Lureau lvol = (lvol * plvol) / 255; 47119677a38SMarc-André Lureau rvol = (rvol * prvol) / 255; 47219677a38SMarc-André Lureau 47319677a38SMarc-André Lureau AUD_set_volume_out (s->voice_po, mute, lvol, rvol); 47419677a38SMarc-André Lureau } 47519677a38SMarc-André Lureau 47619677a38SMarc-André Lureau static void update_volume_in (AC97LinkState *s) 47719677a38SMarc-André Lureau { 47819677a38SMarc-André Lureau uint8_t lvol, rvol; 47919677a38SMarc-André Lureau int mute; 48019677a38SMarc-André Lureau 48119677a38SMarc-André Lureau get_volume (mixer_load (s, AC97_Record_Gain_Mute), 0x0f, 0, 48219677a38SMarc-André Lureau &mute, &lvol, &rvol); 48319677a38SMarc-André Lureau 48419677a38SMarc-André Lureau AUD_set_volume_in (s->voice_pi, mute, lvol, rvol); 48519677a38SMarc-André Lureau } 48619677a38SMarc-André Lureau 48719677a38SMarc-André Lureau static void set_volume (AC97LinkState *s, int index, uint32_t val) 48819677a38SMarc-André Lureau { 4897873bfb8SHans de Goede switch (index) { 4907873bfb8SHans de Goede case AC97_Master_Volume_Mute: 4917873bfb8SHans de Goede val &= 0xbf3f; 49219677a38SMarc-André Lureau mixer_store (s, index, val); 49319677a38SMarc-André Lureau update_combined_volume_out (s); 4947873bfb8SHans de Goede break; 4957873bfb8SHans de Goede case AC97_PCM_Out_Volume_Mute: 4967873bfb8SHans de Goede val &= 0x9f1f; 4977873bfb8SHans de Goede mixer_store (s, index, val); 4987873bfb8SHans de Goede update_combined_volume_out (s); 4997873bfb8SHans de Goede break; 5007873bfb8SHans de Goede case AC97_Record_Gain_Mute: 5017873bfb8SHans de Goede val &= 0x8f0f; 5027873bfb8SHans de Goede mixer_store (s, index, val); 50319677a38SMarc-André Lureau update_volume_in (s); 5047873bfb8SHans de Goede break; 50519677a38SMarc-André Lureau } 50619677a38SMarc-André Lureau } 50719677a38SMarc-André Lureau 50819677a38SMarc-André Lureau static void record_select (AC97LinkState *s, uint32_t val) 50919677a38SMarc-André Lureau { 51019677a38SMarc-André Lureau uint8_t rs = val & REC_MASK; 51119677a38SMarc-André Lureau uint8_t ls = (val >> 8) & REC_MASK; 51219677a38SMarc-André Lureau mixer_store (s, AC97_Record_Select, rs | (ls << 8)); 51319677a38SMarc-André Lureau } 51419677a38SMarc-André Lureau 515e5c9a13eSbalrog static void mixer_reset (AC97LinkState *s) 516e5c9a13eSbalrog { 517e5c9a13eSbalrog uint8_t active[LAST_INDEX]; 518e5c9a13eSbalrog 519e5c9a13eSbalrog dolog ("mixer_reset\n"); 520e5c9a13eSbalrog memset (s->mixer_data, 0, sizeof (s->mixer_data)); 521e5c9a13eSbalrog memset (active, 0, sizeof (active)); 522e5c9a13eSbalrog mixer_store (s, AC97_Reset , 0x0000); /* 6940 */ 523d044be37SHans de Goede mixer_store (s, AC97_Headphone_Volume_Mute , 0x0000); 524d044be37SHans de Goede mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x0000); 525d044be37SHans de Goede mixer_store (s, AC97_Master_Tone_RL, 0x0000); 526e5c9a13eSbalrog mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000); 527d044be37SHans de Goede mixer_store (s, AC97_Phone_Volume_Mute , 0x0000); 528d044be37SHans de Goede mixer_store (s, AC97_Mic_Volume_Mute , 0x0000); 529f94e9b9bSHans de Goede mixer_store (s, AC97_Line_In_Volume_Mute , 0x0000); 530d044be37SHans de Goede mixer_store (s, AC97_CD_Volume_Mute , 0x0000); 531d044be37SHans de Goede mixer_store (s, AC97_Video_Volume_Mute , 0x0000); 532d044be37SHans de Goede mixer_store (s, AC97_Aux_Volume_Mute , 0x0000); 533d044be37SHans de Goede mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x0000); 534e5c9a13eSbalrog mixer_store (s, AC97_General_Purpose , 0x0000); 535e5c9a13eSbalrog mixer_store (s, AC97_3D_Control , 0x0000); 536e5c9a13eSbalrog mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f); 537e5c9a13eSbalrog 538e5c9a13eSbalrog /* 539e5c9a13eSbalrog * Sigmatel 9700 (STAC9700) 540e5c9a13eSbalrog */ 541e5c9a13eSbalrog mixer_store (s, AC97_Vendor_ID1 , 0x8384); 542e5c9a13eSbalrog mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */ 543e5c9a13eSbalrog 544e5c9a13eSbalrog mixer_store (s, AC97_Extended_Audio_ID , 0x0809); 545e5c9a13eSbalrog mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009); 546e5c9a13eSbalrog mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80); 547e5c9a13eSbalrog mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80); 548e5c9a13eSbalrog mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80); 549e5c9a13eSbalrog mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80); 550e5c9a13eSbalrog mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80); 551e5c9a13eSbalrog 55219677a38SMarc-André Lureau record_select (s, 0); 55319677a38SMarc-André Lureau set_volume (s, AC97_Master_Volume_Mute, 0x8000); 55419677a38SMarc-André Lureau set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808); 555f94e9b9bSHans de Goede set_volume (s, AC97_Record_Gain_Mute, 0x8808); 55619677a38SMarc-André Lureau 557e5c9a13eSbalrog reset_voices (s, active); 558e5c9a13eSbalrog } 559e5c9a13eSbalrog 560e5c9a13eSbalrog /** 561e5c9a13eSbalrog * Native audio mixer 562e5c9a13eSbalrog * I/O Reads 563e5c9a13eSbalrog */ 564e5c9a13eSbalrog static uint32_t nam_readb (void *opaque, uint32_t addr) 565e5c9a13eSbalrog { 56610ee2aaaSJuan Quintela AC97LinkState *s = opaque; 567e5c9a13eSbalrog dolog ("U nam readb %#x\n", addr); 568e5c9a13eSbalrog s->cas = 0; 569e5c9a13eSbalrog return ~0U; 570e5c9a13eSbalrog } 571e5c9a13eSbalrog 572e5c9a13eSbalrog static uint32_t nam_readw (void *opaque, uint32_t addr) 573e5c9a13eSbalrog { 57410ee2aaaSJuan Quintela AC97LinkState *s = opaque; 575e5c9a13eSbalrog uint32_t val = ~0U; 57683c406d9SAvi Kivity uint32_t index = addr; 577e5c9a13eSbalrog s->cas = 0; 578e5c9a13eSbalrog val = mixer_load (s, index); 579e5c9a13eSbalrog return val; 580e5c9a13eSbalrog } 581e5c9a13eSbalrog 582e5c9a13eSbalrog static uint32_t nam_readl (void *opaque, uint32_t addr) 583e5c9a13eSbalrog { 58410ee2aaaSJuan Quintela AC97LinkState *s = opaque; 585e5c9a13eSbalrog dolog ("U nam readl %#x\n", addr); 586e5c9a13eSbalrog s->cas = 0; 587e5c9a13eSbalrog return ~0U; 588e5c9a13eSbalrog } 589e5c9a13eSbalrog 590e5c9a13eSbalrog /** 591e5c9a13eSbalrog * Native audio mixer 592e5c9a13eSbalrog * I/O Writes 593e5c9a13eSbalrog */ 594e5c9a13eSbalrog static void nam_writeb (void *opaque, uint32_t addr, uint32_t val) 595e5c9a13eSbalrog { 59610ee2aaaSJuan Quintela AC97LinkState *s = opaque; 597e5c9a13eSbalrog dolog ("U nam writeb %#x <- %#x\n", addr, val); 598e5c9a13eSbalrog s->cas = 0; 599e5c9a13eSbalrog } 600e5c9a13eSbalrog 601e5c9a13eSbalrog static void nam_writew (void *opaque, uint32_t addr, uint32_t val) 602e5c9a13eSbalrog { 60310ee2aaaSJuan Quintela AC97LinkState *s = opaque; 60483c406d9SAvi Kivity uint32_t index = addr; 605e5c9a13eSbalrog s->cas = 0; 606e5c9a13eSbalrog switch (index) { 607e5c9a13eSbalrog case AC97_Reset: 608e5c9a13eSbalrog mixer_reset (s); 609e5c9a13eSbalrog break; 610e5c9a13eSbalrog case AC97_Powerdown_Ctrl_Stat: 611847c25d0SHans de Goede val &= ~0x800f; 612e5c9a13eSbalrog val |= mixer_load (s, index) & 0xf; 613e5c9a13eSbalrog mixer_store (s, index, val); 614e5c9a13eSbalrog break; 61519677a38SMarc-André Lureau case AC97_PCM_Out_Volume_Mute: 61619677a38SMarc-André Lureau case AC97_Master_Volume_Mute: 61719677a38SMarc-André Lureau case AC97_Record_Gain_Mute: 61819677a38SMarc-André Lureau set_volume (s, index, val); 61919677a38SMarc-André Lureau break; 62019677a38SMarc-André Lureau case AC97_Record_Select: 62119677a38SMarc-André Lureau record_select (s, val); 62219677a38SMarc-André Lureau break; 623e5c9a13eSbalrog case AC97_Vendor_ID1: 624e5c9a13eSbalrog case AC97_Vendor_ID2: 625e5c9a13eSbalrog dolog ("Attempt to write vendor ID to %#x\n", val); 626e5c9a13eSbalrog break; 627e5c9a13eSbalrog case AC97_Extended_Audio_ID: 628e5c9a13eSbalrog dolog ("Attempt to write extended audio ID to %#x\n", val); 629e5c9a13eSbalrog break; 630e5c9a13eSbalrog case AC97_Extended_Audio_Ctrl_Stat: 631e5c9a13eSbalrog if (!(val & EACS_VRA)) { 632e5c9a13eSbalrog mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80); 633e5c9a13eSbalrog mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80); 634e5c9a13eSbalrog open_voice (s, PI_INDEX, 48000); 635e5c9a13eSbalrog open_voice (s, PO_INDEX, 48000); 636e5c9a13eSbalrog } 637e5c9a13eSbalrog if (!(val & EACS_VRM)) { 638e5c9a13eSbalrog mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80); 639e5c9a13eSbalrog open_voice (s, MC_INDEX, 48000); 640e5c9a13eSbalrog } 641e5c9a13eSbalrog dolog ("Setting extended audio control to %#x\n", val); 642e5c9a13eSbalrog mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val); 643e5c9a13eSbalrog break; 644e5c9a13eSbalrog case AC97_PCM_Front_DAC_Rate: 645e5c9a13eSbalrog if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { 646e5c9a13eSbalrog mixer_store (s, index, val); 647e5c9a13eSbalrog dolog ("Set front DAC rate to %d\n", val); 648e5c9a13eSbalrog open_voice (s, PO_INDEX, val); 649e5c9a13eSbalrog } 650e5c9a13eSbalrog else { 651e5c9a13eSbalrog dolog ("Attempt to set front DAC rate to %d, " 652e5c9a13eSbalrog "but VRA is not set\n", 653e5c9a13eSbalrog val); 654e5c9a13eSbalrog } 655e5c9a13eSbalrog break; 656e5c9a13eSbalrog case AC97_MIC_ADC_Rate: 657e5c9a13eSbalrog if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) { 658e5c9a13eSbalrog mixer_store (s, index, val); 659e5c9a13eSbalrog dolog ("Set MIC ADC rate to %d\n", val); 660e5c9a13eSbalrog open_voice (s, MC_INDEX, val); 661e5c9a13eSbalrog } 662e5c9a13eSbalrog else { 663e5c9a13eSbalrog dolog ("Attempt to set MIC ADC rate to %d, " 664e5c9a13eSbalrog "but VRM is not set\n", 665e5c9a13eSbalrog val); 666e5c9a13eSbalrog } 667e5c9a13eSbalrog break; 668e5c9a13eSbalrog case AC97_PCM_LR_ADC_Rate: 669e5c9a13eSbalrog if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { 670e5c9a13eSbalrog mixer_store (s, index, val); 671e5c9a13eSbalrog dolog ("Set front LR ADC rate to %d\n", val); 672e5c9a13eSbalrog open_voice (s, PI_INDEX, val); 673e5c9a13eSbalrog } 674e5c9a13eSbalrog else { 675e5c9a13eSbalrog dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n", 676e5c9a13eSbalrog val); 677e5c9a13eSbalrog } 678e5c9a13eSbalrog break; 679d044be37SHans de Goede case AC97_Headphone_Volume_Mute: 680d044be37SHans de Goede case AC97_Master_Volume_Mono_Mute: 681d044be37SHans de Goede case AC97_Master_Tone_RL: 682d044be37SHans de Goede case AC97_PC_BEEP_Volume_Mute: 683d044be37SHans de Goede case AC97_Phone_Volume_Mute: 684d044be37SHans de Goede case AC97_Mic_Volume_Mute: 685f94e9b9bSHans de Goede case AC97_Line_In_Volume_Mute: 686d044be37SHans de Goede case AC97_CD_Volume_Mute: 687d044be37SHans de Goede case AC97_Video_Volume_Mute: 688d044be37SHans de Goede case AC97_Aux_Volume_Mute: 689d044be37SHans de Goede case AC97_Record_Gain_Mic_Mute: 690d044be37SHans de Goede case AC97_General_Purpose: 691d044be37SHans de Goede case AC97_3D_Control: 692d044be37SHans de Goede case AC97_Sigmatel_Analog: 693d044be37SHans de Goede case AC97_Sigmatel_Dac2Invert: 694d044be37SHans de Goede /* None of the features in these regs are emulated, so they are RO */ 695d044be37SHans de Goede break; 696e5c9a13eSbalrog default: 697e5c9a13eSbalrog dolog ("U nam writew %#x <- %#x\n", addr, val); 698e5c9a13eSbalrog mixer_store (s, index, val); 699e5c9a13eSbalrog break; 700e5c9a13eSbalrog } 701e5c9a13eSbalrog } 702e5c9a13eSbalrog 703e5c9a13eSbalrog static void nam_writel (void *opaque, uint32_t addr, uint32_t val) 704e5c9a13eSbalrog { 70510ee2aaaSJuan Quintela AC97LinkState *s = opaque; 706e5c9a13eSbalrog dolog ("U nam writel %#x <- %#x\n", addr, val); 707e5c9a13eSbalrog s->cas = 0; 708e5c9a13eSbalrog } 709e5c9a13eSbalrog 710e5c9a13eSbalrog /** 711e5c9a13eSbalrog * Native audio bus master 712e5c9a13eSbalrog * I/O Reads 713e5c9a13eSbalrog */ 714e5c9a13eSbalrog static uint32_t nabm_readb (void *opaque, uint32_t addr) 715e5c9a13eSbalrog { 71610ee2aaaSJuan Quintela AC97LinkState *s = opaque; 717e5c9a13eSbalrog AC97BusMasterRegs *r = NULL; 71883c406d9SAvi Kivity uint32_t index = addr; 719e5c9a13eSbalrog uint32_t val = ~0U; 720e5c9a13eSbalrog 721e5c9a13eSbalrog switch (index) { 722e5c9a13eSbalrog case CAS: 723e5c9a13eSbalrog dolog ("CAS %d\n", s->cas); 724e5c9a13eSbalrog val = s->cas; 725e5c9a13eSbalrog s->cas = 1; 726e5c9a13eSbalrog break; 727e5c9a13eSbalrog case PI_CIV: 728e5c9a13eSbalrog case PO_CIV: 729e5c9a13eSbalrog case MC_CIV: 730e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 731e5c9a13eSbalrog val = r->civ; 732e5c9a13eSbalrog dolog ("CIV[%d] -> %#x\n", GET_BM (index), val); 733e5c9a13eSbalrog break; 734e5c9a13eSbalrog case PI_LVI: 735e5c9a13eSbalrog case PO_LVI: 736e5c9a13eSbalrog case MC_LVI: 737e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 738e5c9a13eSbalrog val = r->lvi; 739e5c9a13eSbalrog dolog ("LVI[%d] -> %#x\n", GET_BM (index), val); 740e5c9a13eSbalrog break; 741e5c9a13eSbalrog case PI_PIV: 742e5c9a13eSbalrog case PO_PIV: 743e5c9a13eSbalrog case MC_PIV: 744e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 745e5c9a13eSbalrog val = r->piv; 746e5c9a13eSbalrog dolog ("PIV[%d] -> %#x\n", GET_BM (index), val); 747e5c9a13eSbalrog break; 748e5c9a13eSbalrog case PI_CR: 749e5c9a13eSbalrog case PO_CR: 750e5c9a13eSbalrog case MC_CR: 751e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 752e5c9a13eSbalrog val = r->cr; 753e5c9a13eSbalrog dolog ("CR[%d] -> %#x\n", GET_BM (index), val); 754e5c9a13eSbalrog break; 755e5c9a13eSbalrog case PI_SR: 756e5c9a13eSbalrog case PO_SR: 757e5c9a13eSbalrog case MC_SR: 758e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 759e5c9a13eSbalrog val = r->sr & 0xff; 760e5c9a13eSbalrog dolog ("SRb[%d] -> %#x\n", GET_BM (index), val); 761e5c9a13eSbalrog break; 762e5c9a13eSbalrog default: 763e5c9a13eSbalrog dolog ("U nabm readb %#x -> %#x\n", addr, val); 764e5c9a13eSbalrog break; 765e5c9a13eSbalrog } 766e5c9a13eSbalrog return val; 767e5c9a13eSbalrog } 768e5c9a13eSbalrog 769e5c9a13eSbalrog static uint32_t nabm_readw (void *opaque, uint32_t addr) 770e5c9a13eSbalrog { 77110ee2aaaSJuan Quintela AC97LinkState *s = opaque; 772e5c9a13eSbalrog AC97BusMasterRegs *r = NULL; 77383c406d9SAvi Kivity uint32_t index = addr; 774e5c9a13eSbalrog uint32_t val = ~0U; 775e5c9a13eSbalrog 776e5c9a13eSbalrog switch (index) { 777e5c9a13eSbalrog case PI_SR: 778e5c9a13eSbalrog case PO_SR: 779e5c9a13eSbalrog case MC_SR: 780e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 781e5c9a13eSbalrog val = r->sr; 782e5c9a13eSbalrog dolog ("SR[%d] -> %#x\n", GET_BM (index), val); 783e5c9a13eSbalrog break; 784e5c9a13eSbalrog case PI_PICB: 785e5c9a13eSbalrog case PO_PICB: 786e5c9a13eSbalrog case MC_PICB: 787e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 788e5c9a13eSbalrog val = r->picb; 789e5c9a13eSbalrog dolog ("PICB[%d] -> %#x\n", GET_BM (index), val); 790e5c9a13eSbalrog break; 791e5c9a13eSbalrog default: 792e5c9a13eSbalrog dolog ("U nabm readw %#x -> %#x\n", addr, val); 793e5c9a13eSbalrog break; 794e5c9a13eSbalrog } 795e5c9a13eSbalrog return val; 796e5c9a13eSbalrog } 797e5c9a13eSbalrog 798e5c9a13eSbalrog static uint32_t nabm_readl (void *opaque, uint32_t addr) 799e5c9a13eSbalrog { 80010ee2aaaSJuan Quintela AC97LinkState *s = opaque; 801e5c9a13eSbalrog AC97BusMasterRegs *r = NULL; 80283c406d9SAvi Kivity uint32_t index = addr; 803e5c9a13eSbalrog uint32_t val = ~0U; 804e5c9a13eSbalrog 805e5c9a13eSbalrog switch (index) { 806e5c9a13eSbalrog case PI_BDBAR: 807e5c9a13eSbalrog case PO_BDBAR: 808e5c9a13eSbalrog case MC_BDBAR: 809e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 810e5c9a13eSbalrog val = r->bdbar; 811e5c9a13eSbalrog dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val); 812e5c9a13eSbalrog break; 813e5c9a13eSbalrog case PI_CIV: 814e5c9a13eSbalrog case PO_CIV: 815e5c9a13eSbalrog case MC_CIV: 816e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 817e5c9a13eSbalrog val = r->civ | (r->lvi << 8) | (r->sr << 16); 818e5c9a13eSbalrog dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index), 819e5c9a13eSbalrog r->civ, r->lvi, r->sr); 820e5c9a13eSbalrog break; 821e5c9a13eSbalrog case PI_PICB: 822e5c9a13eSbalrog case PO_PICB: 823e5c9a13eSbalrog case MC_PICB: 824e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 825e5c9a13eSbalrog val = r->picb | (r->piv << 16) | (r->cr << 24); 826e5c9a13eSbalrog dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index), 827e5c9a13eSbalrog val, r->picb, r->piv, r->cr); 828e5c9a13eSbalrog break; 829e5c9a13eSbalrog case GLOB_CNT: 830e5c9a13eSbalrog val = s->glob_cnt; 831e5c9a13eSbalrog dolog ("glob_cnt -> %#x\n", val); 832e5c9a13eSbalrog break; 833e5c9a13eSbalrog case GLOB_STA: 834e5c9a13eSbalrog val = s->glob_sta | GS_S0CR; 835e5c9a13eSbalrog dolog ("glob_sta -> %#x\n", val); 836e5c9a13eSbalrog break; 837e5c9a13eSbalrog default: 838e5c9a13eSbalrog dolog ("U nabm readl %#x -> %#x\n", addr, val); 839e5c9a13eSbalrog break; 840e5c9a13eSbalrog } 841e5c9a13eSbalrog return val; 842e5c9a13eSbalrog } 843e5c9a13eSbalrog 844e5c9a13eSbalrog /** 845e5c9a13eSbalrog * Native audio bus master 846e5c9a13eSbalrog * I/O Writes 847e5c9a13eSbalrog */ 848e5c9a13eSbalrog static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val) 849e5c9a13eSbalrog { 85010ee2aaaSJuan Quintela AC97LinkState *s = opaque; 851e5c9a13eSbalrog AC97BusMasterRegs *r = NULL; 85283c406d9SAvi Kivity uint32_t index = addr; 853e5c9a13eSbalrog switch (index) { 854e5c9a13eSbalrog case PI_LVI: 855e5c9a13eSbalrog case PO_LVI: 856e5c9a13eSbalrog case MC_LVI: 857e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 858e5c9a13eSbalrog if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) { 859e5c9a13eSbalrog r->sr &= ~(SR_DCH | SR_CELV); 860e5c9a13eSbalrog r->civ = r->piv; 861e5c9a13eSbalrog r->piv = (r->piv + 1) % 32; 862e5c9a13eSbalrog fetch_bd (s, r); 863e5c9a13eSbalrog } 864e5c9a13eSbalrog r->lvi = val % 32; 865e5c9a13eSbalrog dolog ("LVI[%d] <- %#x\n", GET_BM (index), val); 866e5c9a13eSbalrog break; 867e5c9a13eSbalrog case PI_CR: 868e5c9a13eSbalrog case PO_CR: 869e5c9a13eSbalrog case MC_CR: 870e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 871e5c9a13eSbalrog if (val & CR_RR) { 872e5c9a13eSbalrog reset_bm_regs (s, r); 873e5c9a13eSbalrog } 874e5c9a13eSbalrog else { 875e5c9a13eSbalrog r->cr = val & CR_VALID_MASK; 876e5c9a13eSbalrog if (!(r->cr & CR_RPBM)) { 877e5c9a13eSbalrog voice_set_active (s, r - s->bm_regs, 0); 878e5c9a13eSbalrog r->sr |= SR_DCH; 879e5c9a13eSbalrog } 880e5c9a13eSbalrog else { 881e5c9a13eSbalrog r->civ = r->piv; 882e5c9a13eSbalrog r->piv = (r->piv + 1) % 32; 883e5c9a13eSbalrog fetch_bd (s, r); 884e5c9a13eSbalrog r->sr &= ~SR_DCH; 885e5c9a13eSbalrog voice_set_active (s, r - s->bm_regs, 1); 886e5c9a13eSbalrog } 887e5c9a13eSbalrog } 888e5c9a13eSbalrog dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr); 889e5c9a13eSbalrog break; 890e5c9a13eSbalrog case PI_SR: 891e5c9a13eSbalrog case PO_SR: 892e5c9a13eSbalrog case MC_SR: 893e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 894e5c9a13eSbalrog r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); 895e5c9a13eSbalrog update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); 896e5c9a13eSbalrog dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr); 897e5c9a13eSbalrog break; 898e5c9a13eSbalrog default: 899e5c9a13eSbalrog dolog ("U nabm writeb %#x <- %#x\n", addr, val); 900e5c9a13eSbalrog break; 901e5c9a13eSbalrog } 902e5c9a13eSbalrog } 903e5c9a13eSbalrog 904e5c9a13eSbalrog static void nabm_writew (void *opaque, uint32_t addr, uint32_t val) 905e5c9a13eSbalrog { 90610ee2aaaSJuan Quintela AC97LinkState *s = opaque; 907e5c9a13eSbalrog AC97BusMasterRegs *r = NULL; 90883c406d9SAvi Kivity uint32_t index = addr; 909e5c9a13eSbalrog switch (index) { 910e5c9a13eSbalrog case PI_SR: 911e5c9a13eSbalrog case PO_SR: 912e5c9a13eSbalrog case MC_SR: 913e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 914e5c9a13eSbalrog r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); 915e5c9a13eSbalrog update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); 916e5c9a13eSbalrog dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr); 917e5c9a13eSbalrog break; 918e5c9a13eSbalrog default: 919e5c9a13eSbalrog dolog ("U nabm writew %#x <- %#x\n", addr, val); 920e5c9a13eSbalrog break; 921e5c9a13eSbalrog } 922e5c9a13eSbalrog } 923e5c9a13eSbalrog 924e5c9a13eSbalrog static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) 925e5c9a13eSbalrog { 92610ee2aaaSJuan Quintela AC97LinkState *s = opaque; 927e5c9a13eSbalrog AC97BusMasterRegs *r = NULL; 92883c406d9SAvi Kivity uint32_t index = addr; 929e5c9a13eSbalrog switch (index) { 930e5c9a13eSbalrog case PI_BDBAR: 931e5c9a13eSbalrog case PO_BDBAR: 932e5c9a13eSbalrog case MC_BDBAR: 933e5c9a13eSbalrog r = &s->bm_regs[GET_BM (index)]; 934e5c9a13eSbalrog r->bdbar = val & ~3; 935e5c9a13eSbalrog dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n", 936e5c9a13eSbalrog GET_BM (index), val, r->bdbar); 937e5c9a13eSbalrog break; 938e5c9a13eSbalrog case GLOB_CNT: 939e5c9a13eSbalrog if (val & GC_WR) 940e5c9a13eSbalrog warm_reset (s); 941e5c9a13eSbalrog if (val & GC_CR) 942e5c9a13eSbalrog cold_reset (s); 943e5c9a13eSbalrog if (!(val & (GC_WR | GC_CR))) 944e5c9a13eSbalrog s->glob_cnt = val & GC_VALID_MASK; 945e5c9a13eSbalrog dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt); 946e5c9a13eSbalrog break; 947e5c9a13eSbalrog case GLOB_STA: 948e5c9a13eSbalrog s->glob_sta &= ~(val & GS_WCLEAR_MASK); 949e5c9a13eSbalrog s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK; 950e5c9a13eSbalrog dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta); 951e5c9a13eSbalrog break; 952e5c9a13eSbalrog default: 953e5c9a13eSbalrog dolog ("U nabm writel %#x <- %#x\n", addr, val); 954e5c9a13eSbalrog break; 955e5c9a13eSbalrog } 956e5c9a13eSbalrog } 957e5c9a13eSbalrog 958e5c9a13eSbalrog static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r, 959e5c9a13eSbalrog int max, int *stop) 960e5c9a13eSbalrog { 961e5c9a13eSbalrog uint8_t tmpbuf[4096]; 962e5c9a13eSbalrog uint32_t addr = r->bd.addr; 963e5c9a13eSbalrog uint32_t temp = r->picb << 1; 964e5c9a13eSbalrog uint32_t written = 0; 965e5c9a13eSbalrog int to_copy = 0; 966e5c9a13eSbalrog temp = audio_MIN (temp, max); 967e5c9a13eSbalrog 968e5c9a13eSbalrog if (!temp) { 969e5c9a13eSbalrog *stop = 1; 970e5c9a13eSbalrog return 0; 971e5c9a13eSbalrog } 972e5c9a13eSbalrog 973e5c9a13eSbalrog while (temp) { 974e5c9a13eSbalrog int copied; 975e5c9a13eSbalrog to_copy = audio_MIN (temp, sizeof (tmpbuf)); 97693f43c48SEduard - Gabriel Munteanu pci_dma_read (&s->dev, addr, tmpbuf, to_copy); 977e5c9a13eSbalrog copied = AUD_write (s->voice_po, tmpbuf, to_copy); 978e5c9a13eSbalrog dolog ("write_audio max=%x to_copy=%x copied=%x\n", 979e5c9a13eSbalrog max, to_copy, copied); 980e5c9a13eSbalrog if (!copied) { 981e5c9a13eSbalrog *stop = 1; 982e5c9a13eSbalrog break; 983e5c9a13eSbalrog } 984e5c9a13eSbalrog temp -= copied; 985e5c9a13eSbalrog addr += copied; 986e5c9a13eSbalrog written += copied; 987e5c9a13eSbalrog } 988e5c9a13eSbalrog 989e5c9a13eSbalrog if (!temp) { 990e5c9a13eSbalrog if (to_copy < 4) { 991e5c9a13eSbalrog dolog ("whoops\n"); 992e5c9a13eSbalrog s->last_samp = 0; 993e5c9a13eSbalrog } 994e5c9a13eSbalrog else { 995e5c9a13eSbalrog s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4]; 996e5c9a13eSbalrog } 997e5c9a13eSbalrog } 998e5c9a13eSbalrog 999e5c9a13eSbalrog r->bd.addr = addr; 1000e5c9a13eSbalrog return written; 1001e5c9a13eSbalrog } 1002e5c9a13eSbalrog 1003e5c9a13eSbalrog static void write_bup (AC97LinkState *s, int elapsed) 1004e5c9a13eSbalrog { 1005e5c9a13eSbalrog dolog ("write_bup\n"); 1006e5c9a13eSbalrog if (!(s->bup_flag & BUP_SET)) { 1007e5c9a13eSbalrog if (s->bup_flag & BUP_LAST) { 1008e5c9a13eSbalrog int i; 1009e5c9a13eSbalrog uint8_t *p = s->silence; 1010e5c9a13eSbalrog for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) { 1011e5c9a13eSbalrog *(uint32_t *) p = s->last_samp; 1012e5c9a13eSbalrog } 1013e5c9a13eSbalrog } 1014e5c9a13eSbalrog else { 1015e5c9a13eSbalrog memset (s->silence, 0, sizeof (s->silence)); 1016e5c9a13eSbalrog } 1017e5c9a13eSbalrog s->bup_flag |= BUP_SET; 1018e5c9a13eSbalrog } 1019e5c9a13eSbalrog 1020e5c9a13eSbalrog while (elapsed) { 1021e5c9a13eSbalrog int temp = audio_MIN (elapsed, sizeof (s->silence)); 1022e5c9a13eSbalrog while (temp) { 1023e5c9a13eSbalrog int copied = AUD_write (s->voice_po, s->silence, temp); 1024e5c9a13eSbalrog if (!copied) 1025e5c9a13eSbalrog return; 1026e5c9a13eSbalrog temp -= copied; 1027e5c9a13eSbalrog elapsed -= copied; 1028e5c9a13eSbalrog } 1029e5c9a13eSbalrog } 1030e5c9a13eSbalrog } 1031e5c9a13eSbalrog 1032e5c9a13eSbalrog static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r, 1033e5c9a13eSbalrog int max, int *stop) 1034e5c9a13eSbalrog { 1035e5c9a13eSbalrog uint8_t tmpbuf[4096]; 1036e5c9a13eSbalrog uint32_t addr = r->bd.addr; 1037e5c9a13eSbalrog uint32_t temp = r->picb << 1; 1038e5c9a13eSbalrog uint32_t nread = 0; 1039e5c9a13eSbalrog int to_copy = 0; 1040e5c9a13eSbalrog SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi; 1041e5c9a13eSbalrog 1042e5c9a13eSbalrog temp = audio_MIN (temp, max); 1043e5c9a13eSbalrog 1044e5c9a13eSbalrog if (!temp) { 1045e5c9a13eSbalrog *stop = 1; 1046e5c9a13eSbalrog return 0; 1047e5c9a13eSbalrog } 1048e5c9a13eSbalrog 1049e5c9a13eSbalrog while (temp) { 1050e5c9a13eSbalrog int acquired; 1051e5c9a13eSbalrog to_copy = audio_MIN (temp, sizeof (tmpbuf)); 1052e5c9a13eSbalrog acquired = AUD_read (voice, tmpbuf, to_copy); 1053e5c9a13eSbalrog if (!acquired) { 1054e5c9a13eSbalrog *stop = 1; 1055e5c9a13eSbalrog break; 1056e5c9a13eSbalrog } 105793f43c48SEduard - Gabriel Munteanu pci_dma_write (&s->dev, addr, tmpbuf, acquired); 1058e5c9a13eSbalrog temp -= acquired; 1059e5c9a13eSbalrog addr += acquired; 1060e5c9a13eSbalrog nread += acquired; 1061e5c9a13eSbalrog } 1062e5c9a13eSbalrog 1063e5c9a13eSbalrog r->bd.addr = addr; 1064e5c9a13eSbalrog return nread; 1065e5c9a13eSbalrog } 1066e5c9a13eSbalrog 1067e5c9a13eSbalrog static void transfer_audio (AC97LinkState *s, int index, int elapsed) 1068e5c9a13eSbalrog { 1069e5c9a13eSbalrog AC97BusMasterRegs *r = &s->bm_regs[index]; 10707ba4cbbfSStefan Weil int stop = 0; 1071e5c9a13eSbalrog 10722c44375dSmalc if (s->invalid_freq[index]) { 10732c44375dSmalc AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n", 10742c44375dSmalc index, s->invalid_freq[index]); 10752c44375dSmalc return; 10762c44375dSmalc } 10772c44375dSmalc 1078e5c9a13eSbalrog if (r->sr & SR_DCH) { 1079e5c9a13eSbalrog if (r->cr & CR_RPBM) { 1080e5c9a13eSbalrog switch (index) { 1081e5c9a13eSbalrog case PO_INDEX: 1082e5c9a13eSbalrog write_bup (s, elapsed); 1083e5c9a13eSbalrog break; 1084e5c9a13eSbalrog } 1085e5c9a13eSbalrog } 1086e5c9a13eSbalrog return; 1087e5c9a13eSbalrog } 1088e5c9a13eSbalrog 1089e5c9a13eSbalrog while ((elapsed >> 1) && !stop) { 1090e5c9a13eSbalrog int temp; 1091e5c9a13eSbalrog 1092e5c9a13eSbalrog if (!r->bd_valid) { 1093e5c9a13eSbalrog dolog ("invalid bd\n"); 1094e5c9a13eSbalrog fetch_bd (s, r); 1095e5c9a13eSbalrog } 1096e5c9a13eSbalrog 1097e5c9a13eSbalrog if (!r->picb) { 1098e5c9a13eSbalrog dolog ("fresh bd %d is empty %#x %#x\n", 1099e5c9a13eSbalrog r->civ, r->bd.addr, r->bd.ctl_len); 1100e5c9a13eSbalrog if (r->civ == r->lvi) { 1101e5c9a13eSbalrog r->sr |= SR_DCH; /* CELV? */ 1102e5c9a13eSbalrog s->bup_flag = 0; 1103e5c9a13eSbalrog break; 1104e5c9a13eSbalrog } 1105e5c9a13eSbalrog r->sr &= ~SR_CELV; 1106e5c9a13eSbalrog r->civ = r->piv; 1107e5c9a13eSbalrog r->piv = (r->piv + 1) % 32; 1108e5c9a13eSbalrog fetch_bd (s, r); 1109e5c9a13eSbalrog return; 1110e5c9a13eSbalrog } 1111e5c9a13eSbalrog 1112e5c9a13eSbalrog switch (index) { 1113e5c9a13eSbalrog case PO_INDEX: 1114e5c9a13eSbalrog temp = write_audio (s, r, elapsed, &stop); 1115e5c9a13eSbalrog elapsed -= temp; 1116e5c9a13eSbalrog r->picb -= (temp >> 1); 1117e5c9a13eSbalrog break; 1118e5c9a13eSbalrog 1119e5c9a13eSbalrog case PI_INDEX: 1120e5c9a13eSbalrog case MC_INDEX: 1121e5c9a13eSbalrog temp = read_audio (s, r, elapsed, &stop); 1122e5c9a13eSbalrog elapsed -= temp; 1123e5c9a13eSbalrog r->picb -= (temp >> 1); 1124e5c9a13eSbalrog break; 1125e5c9a13eSbalrog } 1126e5c9a13eSbalrog 1127e5c9a13eSbalrog if (!r->picb) { 1128e5c9a13eSbalrog uint32_t new_sr = r->sr & ~SR_CELV; 1129e5c9a13eSbalrog 1130e5c9a13eSbalrog if (r->bd.ctl_len & BD_IOC) { 1131e5c9a13eSbalrog new_sr |= SR_BCIS; 1132e5c9a13eSbalrog } 1133e5c9a13eSbalrog 1134e5c9a13eSbalrog if (r->civ == r->lvi) { 1135e5c9a13eSbalrog dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi); 1136e5c9a13eSbalrog 1137e5c9a13eSbalrog new_sr |= SR_LVBCI | SR_DCH | SR_CELV; 1138e5c9a13eSbalrog stop = 1; 1139e5c9a13eSbalrog s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0; 1140e5c9a13eSbalrog } 1141e5c9a13eSbalrog else { 1142e5c9a13eSbalrog r->civ = r->piv; 1143e5c9a13eSbalrog r->piv = (r->piv + 1) % 32; 1144e5c9a13eSbalrog fetch_bd (s, r); 1145e5c9a13eSbalrog } 1146e5c9a13eSbalrog 1147e5c9a13eSbalrog update_sr (s, r, new_sr); 1148e5c9a13eSbalrog } 1149e5c9a13eSbalrog } 1150e5c9a13eSbalrog } 1151e5c9a13eSbalrog 1152e5c9a13eSbalrog static void pi_callback (void *opaque, int avail) 1153e5c9a13eSbalrog { 1154e5c9a13eSbalrog transfer_audio (opaque, PI_INDEX, avail); 1155e5c9a13eSbalrog } 1156e5c9a13eSbalrog 1157e5c9a13eSbalrog static void mc_callback (void *opaque, int avail) 1158e5c9a13eSbalrog { 1159e5c9a13eSbalrog transfer_audio (opaque, MC_INDEX, avail); 1160e5c9a13eSbalrog } 1161e5c9a13eSbalrog 1162e5c9a13eSbalrog static void po_callback (void *opaque, int free) 1163e5c9a13eSbalrog { 1164e5c9a13eSbalrog transfer_audio (opaque, PO_INDEX, free); 1165e5c9a13eSbalrog } 1166e5c9a13eSbalrog 1167a90ffa49SJuan Quintela static const VMStateDescription vmstate_ac97_bm_regs = { 1168a90ffa49SJuan Quintela .name = "ac97_bm_regs", 1169a90ffa49SJuan Quintela .version_id = 1, 1170a90ffa49SJuan Quintela .minimum_version_id = 1, 1171a90ffa49SJuan Quintela .fields = (VMStateField[]) { 1172a90ffa49SJuan Quintela VMSTATE_UINT32 (bdbar, AC97BusMasterRegs), 1173a90ffa49SJuan Quintela VMSTATE_UINT8 (civ, AC97BusMasterRegs), 1174a90ffa49SJuan Quintela VMSTATE_UINT8 (lvi, AC97BusMasterRegs), 1175a90ffa49SJuan Quintela VMSTATE_UINT16 (sr, AC97BusMasterRegs), 1176a90ffa49SJuan Quintela VMSTATE_UINT16 (picb, AC97BusMasterRegs), 1177a90ffa49SJuan Quintela VMSTATE_UINT8 (piv, AC97BusMasterRegs), 1178a90ffa49SJuan Quintela VMSTATE_UINT8 (cr, AC97BusMasterRegs), 1179a90ffa49SJuan Quintela VMSTATE_UINT32 (bd_valid, AC97BusMasterRegs), 1180a90ffa49SJuan Quintela VMSTATE_UINT32 (bd.addr, AC97BusMasterRegs), 1181a90ffa49SJuan Quintela VMSTATE_UINT32 (bd.ctl_len, AC97BusMasterRegs), 1182a90ffa49SJuan Quintela VMSTATE_END_OF_LIST () 1183e5c9a13eSbalrog } 1184a90ffa49SJuan Quintela }; 1185e5c9a13eSbalrog 1186a90ffa49SJuan Quintela static int ac97_post_load (void *opaque, int version_id) 1187e5c9a13eSbalrog { 1188e5c9a13eSbalrog uint8_t active[LAST_INDEX]; 1189e5c9a13eSbalrog AC97LinkState *s = opaque; 1190e5c9a13eSbalrog 119119677a38SMarc-André Lureau record_select (s, mixer_load (s, AC97_Record_Select)); 119219677a38SMarc-André Lureau set_volume (s, AC97_Master_Volume_Mute, 119319677a38SMarc-André Lureau mixer_load (s, AC97_Master_Volume_Mute)); 119419677a38SMarc-André Lureau set_volume (s, AC97_PCM_Out_Volume_Mute, 119519677a38SMarc-André Lureau mixer_load (s, AC97_PCM_Out_Volume_Mute)); 1196f94e9b9bSHans de Goede set_volume (s, AC97_Record_Gain_Mute, 1197f94e9b9bSHans de Goede mixer_load (s, AC97_Record_Gain_Mute)); 119819677a38SMarc-André Lureau 11997626f39fSJuan Quintela active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM); 12007626f39fSJuan Quintela active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM); 12017626f39fSJuan Quintela active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM); 1202e5c9a13eSbalrog reset_voices (s, active); 1203e5c9a13eSbalrog 1204e5c9a13eSbalrog s->bup_flag = 0; 1205e5c9a13eSbalrog s->last_samp = 0; 1206e5c9a13eSbalrog return 0; 1207e5c9a13eSbalrog } 1208e5c9a13eSbalrog 1209a90ffa49SJuan Quintela static bool is_version_2 (void *opaque, int version_id) 1210a90ffa49SJuan Quintela { 1211a90ffa49SJuan Quintela return version_id == 2; 1212a90ffa49SJuan Quintela } 1213a90ffa49SJuan Quintela 1214a90ffa49SJuan Quintela static const VMStateDescription vmstate_ac97 = { 1215a90ffa49SJuan Quintela .name = "ac97", 1216a90ffa49SJuan Quintela .version_id = 3, 1217a90ffa49SJuan Quintela .minimum_version_id = 2, 1218a90ffa49SJuan Quintela .post_load = ac97_post_load, 1219a90ffa49SJuan Quintela .fields = (VMStateField[]) { 1220a90ffa49SJuan Quintela VMSTATE_PCI_DEVICE (dev, AC97LinkState), 1221a90ffa49SJuan Quintela VMSTATE_UINT32 (glob_cnt, AC97LinkState), 1222a90ffa49SJuan Quintela VMSTATE_UINT32 (glob_sta, AC97LinkState), 1223a90ffa49SJuan Quintela VMSTATE_UINT32 (cas, AC97LinkState), 1224a90ffa49SJuan Quintela VMSTATE_STRUCT_ARRAY (bm_regs, AC97LinkState, 3, 1, 1225a90ffa49SJuan Quintela vmstate_ac97_bm_regs, AC97BusMasterRegs), 1226a90ffa49SJuan Quintela VMSTATE_BUFFER (mixer_data, AC97LinkState), 1227a90ffa49SJuan Quintela VMSTATE_UNUSED_TEST (is_version_2, 3), 1228a90ffa49SJuan Quintela VMSTATE_END_OF_LIST () 1229a90ffa49SJuan Quintela } 1230a90ffa49SJuan Quintela }; 1231a90ffa49SJuan Quintela 1232d6a6d362SAlexander Graf static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size) 1233d6a6d362SAlexander Graf { 1234d6a6d362SAlexander Graf if ((addr / size) > 256) { 1235d6a6d362SAlexander Graf return -1; 1236d6a6d362SAlexander Graf } 1237d6a6d362SAlexander Graf 1238d6a6d362SAlexander Graf switch (size) { 1239d6a6d362SAlexander Graf case 1: 1240d6a6d362SAlexander Graf return nam_readb(opaque, addr); 1241d6a6d362SAlexander Graf case 2: 1242d6a6d362SAlexander Graf return nam_readw(opaque, addr); 1243d6a6d362SAlexander Graf case 4: 1244d6a6d362SAlexander Graf return nam_readl(opaque, addr); 1245d6a6d362SAlexander Graf default: 1246d6a6d362SAlexander Graf return -1; 1247d6a6d362SAlexander Graf } 1248d6a6d362SAlexander Graf } 1249d6a6d362SAlexander Graf 1250d6a6d362SAlexander Graf static void nam_write(void *opaque, hwaddr addr, uint64_t val, 1251d6a6d362SAlexander Graf unsigned size) 1252d6a6d362SAlexander Graf { 1253d6a6d362SAlexander Graf if ((addr / size) > 256) { 1254d6a6d362SAlexander Graf return; 1255d6a6d362SAlexander Graf } 1256d6a6d362SAlexander Graf 1257d6a6d362SAlexander Graf switch (size) { 1258d6a6d362SAlexander Graf case 1: 1259d6a6d362SAlexander Graf nam_writeb(opaque, addr, val); 1260d6a6d362SAlexander Graf break; 1261d6a6d362SAlexander Graf case 2: 1262d6a6d362SAlexander Graf nam_writew(opaque, addr, val); 1263d6a6d362SAlexander Graf break; 1264d6a6d362SAlexander Graf case 4: 1265d6a6d362SAlexander Graf nam_writel(opaque, addr, val); 1266d6a6d362SAlexander Graf break; 1267d6a6d362SAlexander Graf } 1268d6a6d362SAlexander Graf } 1269e5c9a13eSbalrog 127083c406d9SAvi Kivity static const MemoryRegionOps ac97_io_nam_ops = { 1271d6a6d362SAlexander Graf .read = nam_read, 1272d6a6d362SAlexander Graf .write = nam_write, 1273d6a6d362SAlexander Graf .impl = { 1274d6a6d362SAlexander Graf .min_access_size = 1, 1275d6a6d362SAlexander Graf .max_access_size = 4, 1276d6a6d362SAlexander Graf }, 1277d6a6d362SAlexander Graf .endianness = DEVICE_LITTLE_ENDIAN, 127883c406d9SAvi Kivity }; 127983c406d9SAvi Kivity 1280d6a6d362SAlexander Graf static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size) 1281d6a6d362SAlexander Graf { 1282d6a6d362SAlexander Graf if ((addr / size) > 64) { 1283d6a6d362SAlexander Graf return -1; 1284d6a6d362SAlexander Graf } 1285d6a6d362SAlexander Graf 1286d6a6d362SAlexander Graf switch (size) { 1287d6a6d362SAlexander Graf case 1: 1288d6a6d362SAlexander Graf return nabm_readb(opaque, addr); 1289d6a6d362SAlexander Graf case 2: 1290d6a6d362SAlexander Graf return nabm_readw(opaque, addr); 1291d6a6d362SAlexander Graf case 4: 1292d6a6d362SAlexander Graf return nabm_readl(opaque, addr); 1293d6a6d362SAlexander Graf default: 1294d6a6d362SAlexander Graf return -1; 1295d6a6d362SAlexander Graf } 1296d6a6d362SAlexander Graf } 1297d6a6d362SAlexander Graf 1298d6a6d362SAlexander Graf static void nabm_write(void *opaque, hwaddr addr, uint64_t val, 1299d6a6d362SAlexander Graf unsigned size) 1300d6a6d362SAlexander Graf { 1301d6a6d362SAlexander Graf if ((addr / size) > 64) { 1302d6a6d362SAlexander Graf return; 1303d6a6d362SAlexander Graf } 1304d6a6d362SAlexander Graf 1305d6a6d362SAlexander Graf switch (size) { 1306d6a6d362SAlexander Graf case 1: 1307d6a6d362SAlexander Graf nabm_writeb(opaque, addr, val); 1308d6a6d362SAlexander Graf break; 1309d6a6d362SAlexander Graf case 2: 1310d6a6d362SAlexander Graf nabm_writew(opaque, addr, val); 1311d6a6d362SAlexander Graf break; 1312d6a6d362SAlexander Graf case 4: 1313d6a6d362SAlexander Graf nabm_writel(opaque, addr, val); 1314d6a6d362SAlexander Graf break; 1315d6a6d362SAlexander Graf } 1316d6a6d362SAlexander Graf } 1317d6a6d362SAlexander Graf 131883c406d9SAvi Kivity 131983c406d9SAvi Kivity static const MemoryRegionOps ac97_io_nabm_ops = { 1320d6a6d362SAlexander Graf .read = nabm_read, 1321d6a6d362SAlexander Graf .write = nabm_write, 1322d6a6d362SAlexander Graf .impl = { 1323d6a6d362SAlexander Graf .min_access_size = 1, 1324d6a6d362SAlexander Graf .max_access_size = 4, 1325d6a6d362SAlexander Graf }, 1326d6a6d362SAlexander Graf .endianness = DEVICE_LITTLE_ENDIAN, 132783c406d9SAvi Kivity }; 1328e5c9a13eSbalrog 132913377147SGerd Hoffmann static void ac97_on_reset (DeviceState *dev) 1330e5c9a13eSbalrog { 133113377147SGerd Hoffmann AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev); 1332e5c9a13eSbalrog 1333e5c9a13eSbalrog reset_bm_regs (s, &s->bm_regs[0]); 1334e5c9a13eSbalrog reset_bm_regs (s, &s->bm_regs[1]); 1335e5c9a13eSbalrog reset_bm_regs (s, &s->bm_regs[2]); 1336e5c9a13eSbalrog 1337e5c9a13eSbalrog /* 1338e5c9a13eSbalrog * Reset the mixer too. The Windows XP driver seems to rely on 1339e5c9a13eSbalrog * this. At least it wants to read the vendor id before it resets 1340e5c9a13eSbalrog * the codec manually. 1341e5c9a13eSbalrog */ 1342e5c9a13eSbalrog mixer_reset (s); 1343e5c9a13eSbalrog } 1344e5c9a13eSbalrog 13459af21dbeSMarkus Armbruster static void ac97_realize(PCIDevice *dev, Error **errp) 1346e5c9a13eSbalrog { 1347*417d430eSLi Qiang AC97LinkState *s = AC97(dev); 134810ee2aaaSJuan Quintela uint8_t *c = s->dev.config; 1349e5c9a13eSbalrog 13504468fb63SMichael S. Tsirkin /* TODO: no need to override */ 13514468fb63SMichael S. Tsirkin c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */ 13524468fb63SMichael S. Tsirkin c[PCI_COMMAND + 1] = 0x00; 1353e5c9a13eSbalrog 13544468fb63SMichael S. Tsirkin /* TODO: */ 13554468fb63SMichael S. Tsirkin c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */ 13564468fb63SMichael S. Tsirkin c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; 1357e5c9a13eSbalrog 13584468fb63SMichael S. Tsirkin c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */ 1359e5c9a13eSbalrog 13604468fb63SMichael S. Tsirkin /* TODO set when bar is registered. no need to override. */ 13614468fb63SMichael S. Tsirkin /* nabmar native audio mixer base address rw */ 13624468fb63SMichael S. Tsirkin c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO; 13634468fb63SMichael S. Tsirkin c[PCI_BASE_ADDRESS_0 + 1] = 0x00; 13644468fb63SMichael S. Tsirkin c[PCI_BASE_ADDRESS_0 + 2] = 0x00; 13654468fb63SMichael S. Tsirkin c[PCI_BASE_ADDRESS_0 + 3] = 0x00; 1366e5c9a13eSbalrog 13674468fb63SMichael S. Tsirkin /* TODO set when bar is registered. no need to override. */ 13684468fb63SMichael S. Tsirkin /* nabmbar native audio bus mastering base address rw */ 13694468fb63SMichael S. Tsirkin c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO; 13704468fb63SMichael S. Tsirkin c[PCI_BASE_ADDRESS_0 + 5] = 0x00; 13714468fb63SMichael S. Tsirkin c[PCI_BASE_ADDRESS_0 + 6] = 0x00; 13724468fb63SMichael S. Tsirkin c[PCI_BASE_ADDRESS_0 + 7] = 0x00; 1373e5c9a13eSbalrog 137425a21c94SGerd Hoffmann if (s->use_broken_id) { 137525a21c94SGerd Hoffmann c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86; 13764468fb63SMichael S. Tsirkin c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80; 137725a21c94SGerd Hoffmann c[PCI_SUBSYSTEM_ID] = 0x00; 13784468fb63SMichael S. Tsirkin c[PCI_SUBSYSTEM_ID + 1] = 0x00; 137925a21c94SGerd Hoffmann } 1380e5c9a13eSbalrog 13814468fb63SMichael S. Tsirkin c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */ 13824468fb63SMichael S. Tsirkin c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */ 1383e5c9a13eSbalrog 138464bde0f3SPaolo Bonzini memory_region_init_io (&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s, 138564bde0f3SPaolo Bonzini "ac97-nam", 1024); 138664bde0f3SPaolo Bonzini memory_region_init_io (&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s, 138764bde0f3SPaolo Bonzini "ac97-nabm", 256); 1388e824b2ccSAvi Kivity pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam); 1389e824b2ccSAvi Kivity pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm); 13901a7dafceSmalc AUD_register_card ("ac97", &s->card); 139113377147SGerd Hoffmann ac97_on_reset (&s->dev.qdev); 1392d88a76d1SGerd Hoffmann } 1393d88a76d1SGerd Hoffmann 139412351a91SLi Qiang static void ac97_exit(PCIDevice *dev) 139512351a91SLi Qiang { 1396*417d430eSLi Qiang AC97LinkState *s = AC97(dev); 139712351a91SLi Qiang 139812351a91SLi Qiang AUD_close_in(&s->card, s->voice_pi); 139912351a91SLi Qiang AUD_close_out(&s->card, s->voice_po); 140012351a91SLi Qiang AUD_close_in(&s->card, s->voice_mc); 140112351a91SLi Qiang AUD_remove_card(&s->card); 140212351a91SLi Qiang } 140312351a91SLi Qiang 140436cd6f6fSPaolo Bonzini static int ac97_init (PCIBus *bus) 1405d88a76d1SGerd Hoffmann { 1406*417d430eSLi Qiang pci_create_simple(bus, -1, TYPE_AC97); 1407e5c9a13eSbalrog return 0; 1408e5c9a13eSbalrog } 1409d88a76d1SGerd Hoffmann 141040021f08SAnthony Liguori static Property ac97_properties[] = { 141125a21c94SGerd Hoffmann DEFINE_PROP_UINT32 ("use_broken_id", AC97LinkState, use_broken_id, 0), 141225a21c94SGerd Hoffmann DEFINE_PROP_END_OF_LIST (), 141340021f08SAnthony Liguori }; 141440021f08SAnthony Liguori 141540021f08SAnthony Liguori static void ac97_class_init (ObjectClass *klass, void *data) 141640021f08SAnthony Liguori { 141739bffca2SAnthony Liguori DeviceClass *dc = DEVICE_CLASS (klass); 141840021f08SAnthony Liguori PCIDeviceClass *k = PCI_DEVICE_CLASS (klass); 141940021f08SAnthony Liguori 14209af21dbeSMarkus Armbruster k->realize = ac97_realize; 142112351a91SLi Qiang k->exit = ac97_exit; 142240021f08SAnthony Liguori k->vendor_id = PCI_VENDOR_ID_INTEL; 142340021f08SAnthony Liguori k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5; 142440021f08SAnthony Liguori k->revision = 0x01; 142540021f08SAnthony Liguori k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 1426125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 142739bffca2SAnthony Liguori dc->desc = "Intel 82801AA AC97 Audio"; 142839bffca2SAnthony Liguori dc->vmsd = &vmstate_ac97; 142939bffca2SAnthony Liguori dc->props = ac97_properties; 143013377147SGerd Hoffmann dc->reset = ac97_on_reset; 143125a21c94SGerd Hoffmann } 143240021f08SAnthony Liguori 14338c43a6f0SAndreas Färber static const TypeInfo ac97_info = { 1434*417d430eSLi Qiang .name = TYPE_AC97, 143539bffca2SAnthony Liguori .parent = TYPE_PCI_DEVICE, 143639bffca2SAnthony Liguori .instance_size = sizeof (AC97LinkState), 143740021f08SAnthony Liguori .class_init = ac97_class_init, 1438fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 1439fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1440fd3b02c8SEduardo Habkost { }, 1441fd3b02c8SEduardo Habkost }, 1442d88a76d1SGerd Hoffmann }; 1443d88a76d1SGerd Hoffmann 144483f7d43aSAndreas Färber static void ac97_register_types (void) 1445d88a76d1SGerd Hoffmann { 144639bffca2SAnthony Liguori type_register_static (&ac97_info); 144736cd6f6fSPaolo Bonzini pci_register_soundhw("ac97", "Intel 82801AA AC97 Audio", ac97_init); 1448d88a76d1SGerd Hoffmann } 1449d88a76d1SGerd Hoffmann 145083f7d43aSAndreas Färber type_init (ac97_register_types) 1451