1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "hw/sysbus.h" 32 #include "hw/arm/arm.h" 33 #include "hw/arm/primecell.h" 34 #include "hw/devices.h" 35 #include "net/net.h" 36 #include "sysemu/block-backend.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/sysemu.h" 39 #include "sysemu/kvm.h" 40 #include "hw/boards.h" 41 #include "hw/loader.h" 42 #include "exec/address-spaces.h" 43 #include "qemu/bitops.h" 44 #include "qemu/error-report.h" 45 46 #define NUM_VIRTIO_TRANSPORTS 32 47 48 /* Number of external interrupt lines to configure the GIC with */ 49 #define NUM_IRQS 128 50 51 #define GIC_FDT_IRQ_TYPE_SPI 0 52 #define GIC_FDT_IRQ_TYPE_PPI 1 53 54 #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1 55 #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2 56 #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4 57 #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8 58 59 #define GIC_FDT_IRQ_PPI_CPU_START 8 60 #define GIC_FDT_IRQ_PPI_CPU_WIDTH 8 61 62 enum { 63 VIRT_FLASH, 64 VIRT_MEM, 65 VIRT_CPUPERIPHS, 66 VIRT_GIC_DIST, 67 VIRT_GIC_CPU, 68 VIRT_UART, 69 VIRT_MMIO, 70 VIRT_RTC, 71 VIRT_FW_CFG, 72 }; 73 74 typedef struct MemMapEntry { 75 hwaddr base; 76 hwaddr size; 77 } MemMapEntry; 78 79 typedef struct VirtBoardInfo { 80 struct arm_boot_info bootinfo; 81 const char *cpu_model; 82 const MemMapEntry *memmap; 83 const int *irqmap; 84 int smp_cpus; 85 void *fdt; 86 int fdt_size; 87 uint32_t clock_phandle; 88 } VirtBoardInfo; 89 90 typedef struct { 91 MachineClass parent; 92 VirtBoardInfo *daughterboard; 93 } VirtMachineClass; 94 95 typedef struct { 96 MachineState parent; 97 bool secure; 98 } VirtMachineState; 99 100 #define TYPE_VIRT_MACHINE "virt" 101 #define VIRT_MACHINE(obj) \ 102 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) 103 #define VIRT_MACHINE_GET_CLASS(obj) \ 104 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE) 105 #define VIRT_MACHINE_CLASS(klass) \ 106 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE) 107 108 /* Addresses and sizes of our components. 109 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 110 * 128MB..256MB is used for miscellaneous device I/O. 111 * 256MB..1GB is reserved for possible future PCI support (ie where the 112 * PCI memory window will go if we add a PCI host controller). 113 * 1GB and up is RAM (which may happily spill over into the 114 * high memory region beyond 4GB). 115 * This represents a compromise between how much RAM can be given to 116 * a 32 bit VM and leaving space for expansion and in particular for PCI. 117 * Note that devices should generally be placed at multiples of 0x10000, 118 * to accommodate guests using 64K pages. 119 */ 120 static const MemMapEntry a15memmap[] = { 121 /* Space up to 0x8000000 is reserved for a boot ROM */ 122 [VIRT_FLASH] = { 0, 0x08000000 }, 123 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 124 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 125 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 126 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 127 [VIRT_UART] = { 0x09000000, 0x00001000 }, 128 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 129 [VIRT_FW_CFG] = { 0x09020000, 0x0000000a }, 130 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 131 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 132 /* 0x10000000 .. 0x40000000 reserved for PCI */ 133 [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 }, 134 }; 135 136 static const int a15irqmap[] = { 137 [VIRT_UART] = 1, 138 [VIRT_RTC] = 2, 139 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 140 }; 141 142 static VirtBoardInfo machines[] = { 143 { 144 .cpu_model = "cortex-a15", 145 .memmap = a15memmap, 146 .irqmap = a15irqmap, 147 }, 148 { 149 .cpu_model = "cortex-a57", 150 .memmap = a15memmap, 151 .irqmap = a15irqmap, 152 }, 153 { 154 .cpu_model = "host", 155 .memmap = a15memmap, 156 .irqmap = a15irqmap, 157 }, 158 }; 159 160 static VirtBoardInfo *find_machine_info(const char *cpu) 161 { 162 int i; 163 164 for (i = 0; i < ARRAY_SIZE(machines); i++) { 165 if (strcmp(cpu, machines[i].cpu_model) == 0) { 166 return &machines[i]; 167 } 168 } 169 return NULL; 170 } 171 172 static void create_fdt(VirtBoardInfo *vbi) 173 { 174 void *fdt = create_device_tree(&vbi->fdt_size); 175 176 if (!fdt) { 177 error_report("create_device_tree() failed"); 178 exit(1); 179 } 180 181 vbi->fdt = fdt; 182 183 /* Header */ 184 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 185 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 186 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 187 188 /* 189 * /chosen and /memory nodes must exist for load_dtb 190 * to fill in necessary properties later 191 */ 192 qemu_fdt_add_subnode(fdt, "/chosen"); 193 qemu_fdt_add_subnode(fdt, "/memory"); 194 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 195 196 /* Clock node, for the benefit of the UART. The kernel device tree 197 * binding documentation claims the PL011 node clock properties are 198 * optional but in practice if you omit them the kernel refuses to 199 * probe for the device. 200 */ 201 vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); 202 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 203 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 204 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 205 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 206 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 207 "clk24mhz"); 208 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); 209 210 } 211 212 static void fdt_add_psci_node(const VirtBoardInfo *vbi) 213 { 214 uint32_t cpu_suspend_fn; 215 uint32_t cpu_off_fn; 216 uint32_t cpu_on_fn; 217 uint32_t migrate_fn; 218 void *fdt = vbi->fdt; 219 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 220 221 qemu_fdt_add_subnode(fdt, "/psci"); 222 if (armcpu->psci_version == 2) { 223 const char comp[] = "arm,psci-0.2\0arm,psci"; 224 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 225 226 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 227 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 228 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 229 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 230 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 231 } else { 232 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 233 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 234 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 235 } 236 } else { 237 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 238 239 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 240 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 241 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 242 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 243 } 244 245 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 246 * to the instruction that should be used to invoke PSCI functions. 247 * However, the device tree binding uses 'method' instead, so that is 248 * what we should use here. 249 */ 250 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); 251 252 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 253 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 254 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 255 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 256 } 257 258 static void fdt_add_timer_nodes(const VirtBoardInfo *vbi) 259 { 260 /* Note that on A15 h/w these interrupts are level-triggered, 261 * but for the GIC implementation provided by both QEMU and KVM 262 * they are edge-triggered. 263 */ 264 ARMCPU *armcpu; 265 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 266 267 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 268 GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1); 269 270 qemu_fdt_add_subnode(vbi->fdt, "/timer"); 271 272 armcpu = ARM_CPU(qemu_get_cpu(0)); 273 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 274 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 275 qemu_fdt_setprop(vbi->fdt, "/timer", "compatible", 276 compat, sizeof(compat)); 277 } else { 278 qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible", 279 "arm,armv7-timer"); 280 } 281 qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", 282 GIC_FDT_IRQ_TYPE_PPI, 13, irqflags, 283 GIC_FDT_IRQ_TYPE_PPI, 14, irqflags, 284 GIC_FDT_IRQ_TYPE_PPI, 11, irqflags, 285 GIC_FDT_IRQ_TYPE_PPI, 10, irqflags); 286 } 287 288 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) 289 { 290 int cpu; 291 292 qemu_fdt_add_subnode(vbi->fdt, "/cpus"); 293 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1); 294 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); 295 296 for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { 297 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 298 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 299 300 qemu_fdt_add_subnode(vbi->fdt, nodename); 301 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); 302 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", 303 armcpu->dtb_compatible); 304 305 if (vbi->smp_cpus > 1) { 306 qemu_fdt_setprop_string(vbi->fdt, nodename, 307 "enable-method", "psci"); 308 } 309 310 qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", cpu); 311 g_free(nodename); 312 } 313 } 314 315 static void fdt_add_gic_node(const VirtBoardInfo *vbi) 316 { 317 uint32_t gic_phandle; 318 319 gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 320 qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", gic_phandle); 321 322 qemu_fdt_add_subnode(vbi->fdt, "/intc"); 323 /* 'cortex-a15-gic' means 'GIC v2' */ 324 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 325 "arm,cortex-a15-gic"); 326 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); 327 qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); 328 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 329 2, vbi->memmap[VIRT_GIC_DIST].base, 330 2, vbi->memmap[VIRT_GIC_DIST].size, 331 2, vbi->memmap[VIRT_GIC_CPU].base, 332 2, vbi->memmap[VIRT_GIC_CPU].size); 333 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", gic_phandle); 334 } 335 336 static void create_gic(const VirtBoardInfo *vbi, qemu_irq *pic) 337 { 338 /* We create a standalone GIC v2 */ 339 DeviceState *gicdev; 340 SysBusDevice *gicbusdev; 341 const char *gictype = "arm_gic"; 342 int i; 343 344 if (kvm_irqchip_in_kernel()) { 345 gictype = "kvm-arm-gic"; 346 } 347 348 gicdev = qdev_create(NULL, gictype); 349 qdev_prop_set_uint32(gicdev, "revision", 2); 350 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 351 /* Note that the num-irq property counts both internal and external 352 * interrupts; there are always 32 of the former (mandated by GIC spec). 353 */ 354 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 355 qdev_init_nofail(gicdev); 356 gicbusdev = SYS_BUS_DEVICE(gicdev); 357 sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); 358 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); 359 360 /* Wire the outputs from each CPU's generic timer to the 361 * appropriate GIC PPI inputs, and the GIC's IRQ output to 362 * the CPU's IRQ input. 363 */ 364 for (i = 0; i < smp_cpus; i++) { 365 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 366 int ppibase = NUM_IRQS + i * 32; 367 /* physical timer; we wire it up to the non-secure timer's ID, 368 * since a real A15 always has TrustZone but QEMU doesn't. 369 */ 370 qdev_connect_gpio_out(cpudev, 0, 371 qdev_get_gpio_in(gicdev, ppibase + 30)); 372 /* virtual timer */ 373 qdev_connect_gpio_out(cpudev, 1, 374 qdev_get_gpio_in(gicdev, ppibase + 27)); 375 376 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 377 } 378 379 for (i = 0; i < NUM_IRQS; i++) { 380 pic[i] = qdev_get_gpio_in(gicdev, i); 381 } 382 383 fdt_add_gic_node(vbi); 384 } 385 386 static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic) 387 { 388 char *nodename; 389 hwaddr base = vbi->memmap[VIRT_UART].base; 390 hwaddr size = vbi->memmap[VIRT_UART].size; 391 int irq = vbi->irqmap[VIRT_UART]; 392 const char compat[] = "arm,pl011\0arm,primecell"; 393 const char clocknames[] = "uartclk\0apb_pclk"; 394 395 sysbus_create_simple("pl011", base, pic[irq]); 396 397 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 398 qemu_fdt_add_subnode(vbi->fdt, nodename); 399 /* Note that we can't use setprop_string because of the embedded NUL */ 400 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", 401 compat, sizeof(compat)); 402 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 403 2, base, 2, size); 404 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 405 GIC_FDT_IRQ_TYPE_SPI, irq, 406 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 407 qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", 408 vbi->clock_phandle, vbi->clock_phandle); 409 qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", 410 clocknames, sizeof(clocknames)); 411 412 qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename); 413 g_free(nodename); 414 } 415 416 static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic) 417 { 418 char *nodename; 419 hwaddr base = vbi->memmap[VIRT_RTC].base; 420 hwaddr size = vbi->memmap[VIRT_RTC].size; 421 int irq = vbi->irqmap[VIRT_RTC]; 422 const char compat[] = "arm,pl031\0arm,primecell"; 423 424 sysbus_create_simple("pl031", base, pic[irq]); 425 426 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 427 qemu_fdt_add_subnode(vbi->fdt, nodename); 428 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 429 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 430 2, base, 2, size); 431 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 432 GIC_FDT_IRQ_TYPE_SPI, irq, 433 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 434 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 435 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 436 g_free(nodename); 437 } 438 439 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic) 440 { 441 int i; 442 hwaddr size = vbi->memmap[VIRT_MMIO].size; 443 444 /* Note that we have to create the transports in forwards order 445 * so that command line devices are inserted lowest address first, 446 * and then add dtb nodes in reverse order so that they appear in 447 * the finished device tree lowest address first. 448 */ 449 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 450 int irq = vbi->irqmap[VIRT_MMIO] + i; 451 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 452 453 sysbus_create_simple("virtio-mmio", base, pic[irq]); 454 } 455 456 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 457 char *nodename; 458 int irq = vbi->irqmap[VIRT_MMIO] + i; 459 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 460 461 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 462 qemu_fdt_add_subnode(vbi->fdt, nodename); 463 qemu_fdt_setprop_string(vbi->fdt, nodename, 464 "compatible", "virtio,mmio"); 465 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 466 2, base, 2, size); 467 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 468 GIC_FDT_IRQ_TYPE_SPI, irq, 469 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 470 g_free(nodename); 471 } 472 } 473 474 static void create_one_flash(const char *name, hwaddr flashbase, 475 hwaddr flashsize) 476 { 477 /* Create and map a single flash device. We use the same 478 * parameters as the flash devices on the Versatile Express board. 479 */ 480 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 481 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 482 const uint64_t sectorlength = 256 * 1024; 483 484 if (dinfo && qdev_prop_set_drive(dev, "drive", 485 blk_by_legacy_dinfo(dinfo))) { 486 abort(); 487 } 488 489 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 490 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 491 qdev_prop_set_uint8(dev, "width", 4); 492 qdev_prop_set_uint8(dev, "device-width", 2); 493 qdev_prop_set_uint8(dev, "big-endian", 0); 494 qdev_prop_set_uint16(dev, "id0", 0x89); 495 qdev_prop_set_uint16(dev, "id1", 0x18); 496 qdev_prop_set_uint16(dev, "id2", 0x00); 497 qdev_prop_set_uint16(dev, "id3", 0x00); 498 qdev_prop_set_string(dev, "name", name); 499 qdev_init_nofail(dev); 500 501 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, flashbase); 502 } 503 504 static void create_flash(const VirtBoardInfo *vbi) 505 { 506 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 507 * Any file passed via -bios goes in the first of these. 508 */ 509 hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2; 510 hwaddr flashbase = vbi->memmap[VIRT_FLASH].base; 511 char *nodename; 512 513 if (bios_name) { 514 const char *fn; 515 516 if (drive_get(IF_PFLASH, 0, 0)) { 517 error_report("The contents of the first flash device may be " 518 "specified with -bios or with -drive if=pflash... " 519 "but you cannot use both options at once"); 520 exit(1); 521 } 522 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 523 if (!fn || load_image_targphys(fn, flashbase, flashsize) < 0) { 524 error_report("Could not load ROM image '%s'", bios_name); 525 exit(1); 526 } 527 } 528 529 create_one_flash("virt.flash0", flashbase, flashsize); 530 create_one_flash("virt.flash1", flashbase + flashsize, flashsize); 531 532 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 533 qemu_fdt_add_subnode(vbi->fdt, nodename); 534 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 535 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 536 2, flashbase, 2, flashsize, 537 2, flashbase + flashsize, 2, flashsize); 538 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 539 g_free(nodename); 540 } 541 542 static void create_fw_cfg(const VirtBoardInfo *vbi) 543 { 544 hwaddr base = vbi->memmap[VIRT_FW_CFG].base; 545 hwaddr size = vbi->memmap[VIRT_FW_CFG].size; 546 char *nodename; 547 548 fw_cfg_init_mem_wide(base + 8, base, 8); 549 550 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 551 qemu_fdt_add_subnode(vbi->fdt, nodename); 552 qemu_fdt_setprop_string(vbi->fdt, nodename, 553 "compatible", "qemu,fw-cfg-mmio"); 554 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 555 2, base, 2, size); 556 g_free(nodename); 557 } 558 559 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 560 { 561 const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; 562 563 *fdt_size = board->fdt_size; 564 return board->fdt; 565 } 566 567 static void machvirt_init(MachineState *machine) 568 { 569 VirtMachineState *vms = VIRT_MACHINE(machine); 570 qemu_irq pic[NUM_IRQS]; 571 MemoryRegion *sysmem = get_system_memory(); 572 int n; 573 MemoryRegion *ram = g_new(MemoryRegion, 1); 574 const char *cpu_model = machine->cpu_model; 575 VirtBoardInfo *vbi; 576 577 if (!cpu_model) { 578 cpu_model = "cortex-a15"; 579 } 580 581 vbi = find_machine_info(cpu_model); 582 583 if (!vbi) { 584 error_report("mach-virt: CPU %s not supported", cpu_model); 585 exit(1); 586 } 587 588 vbi->smp_cpus = smp_cpus; 589 590 if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { 591 error_report("mach-virt: cannot model more than 30GB RAM"); 592 exit(1); 593 } 594 595 create_fdt(vbi); 596 597 for (n = 0; n < smp_cpus; n++) { 598 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 599 Object *cpuobj; 600 601 if (!oc) { 602 fprintf(stderr, "Unable to find CPU definition\n"); 603 exit(1); 604 } 605 cpuobj = object_new(object_class_get_name(oc)); 606 607 if (!vms->secure) { 608 object_property_set_bool(cpuobj, false, "has_el3", NULL); 609 } 610 611 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, "psci-conduit", 612 NULL); 613 614 /* Secondary CPUs start in PSCI powered-down state */ 615 if (n > 0) { 616 object_property_set_bool(cpuobj, true, "start-powered-off", NULL); 617 } 618 619 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 620 object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, 621 "reset-cbar", &error_abort); 622 } 623 624 object_property_set_bool(cpuobj, true, "realized", NULL); 625 } 626 fdt_add_timer_nodes(vbi); 627 fdt_add_cpu_nodes(vbi); 628 fdt_add_psci_node(vbi); 629 630 memory_region_init_ram(ram, NULL, "mach-virt.ram", machine->ram_size, 631 &error_abort); 632 vmstate_register_ram_global(ram); 633 memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); 634 635 create_flash(vbi); 636 637 create_gic(vbi, pic); 638 639 create_uart(vbi, pic); 640 641 create_rtc(vbi, pic); 642 643 /* Create mmio transports, so the user can create virtio backends 644 * (which will be automatically plugged in to the transports). If 645 * no backend is created the transport will just sit harmlessly idle. 646 */ 647 create_virtio_devices(vbi, pic); 648 649 create_fw_cfg(vbi); 650 651 vbi->bootinfo.ram_size = machine->ram_size; 652 vbi->bootinfo.kernel_filename = machine->kernel_filename; 653 vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; 654 vbi->bootinfo.initrd_filename = machine->initrd_filename; 655 vbi->bootinfo.nb_cpus = smp_cpus; 656 vbi->bootinfo.board_id = -1; 657 vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; 658 vbi->bootinfo.get_dtb = machvirt_dtb; 659 vbi->bootinfo.firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 660 arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); 661 } 662 663 static bool virt_get_secure(Object *obj, Error **errp) 664 { 665 VirtMachineState *vms = VIRT_MACHINE(obj); 666 667 return vms->secure; 668 } 669 670 static void virt_set_secure(Object *obj, bool value, Error **errp) 671 { 672 VirtMachineState *vms = VIRT_MACHINE(obj); 673 674 vms->secure = value; 675 } 676 677 static void virt_instance_init(Object *obj) 678 { 679 VirtMachineState *vms = VIRT_MACHINE(obj); 680 681 /* EL3 is enabled by default on virt */ 682 vms->secure = true; 683 object_property_add_bool(obj, "secure", virt_get_secure, 684 virt_set_secure, NULL); 685 object_property_set_description(obj, "secure", 686 "Set on/off to enable/disable the ARM " 687 "Security Extensions (TrustZone)", 688 NULL); 689 } 690 691 static void virt_class_init(ObjectClass *oc, void *data) 692 { 693 MachineClass *mc = MACHINE_CLASS(oc); 694 695 mc->name = TYPE_VIRT_MACHINE; 696 mc->desc = "ARM Virtual Machine", 697 mc->init = machvirt_init; 698 mc->max_cpus = 8; 699 } 700 701 static const TypeInfo machvirt_info = { 702 .name = TYPE_VIRT_MACHINE, 703 .parent = TYPE_MACHINE, 704 .instance_size = sizeof(VirtMachineState), 705 .instance_init = virt_instance_init, 706 .class_size = sizeof(VirtMachineClass), 707 .class_init = virt_class_init, 708 }; 709 710 static void machvirt_machine_init(void) 711 { 712 type_register_static(&machvirt_info); 713 } 714 715 machine_init(machvirt_machine_init); 716