1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu-common.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/boards.h" 39 #include "hw/arm/boot.h" 40 #include "hw/arm/primecell.h" 41 #include "hw/arm/virt.h" 42 #include "hw/block/flash.h" 43 #include "hw/vfio/vfio-calxeda-xgmac.h" 44 #include "hw/vfio/vfio-amd-xgbe.h" 45 #include "hw/display/ramfb.h" 46 #include "net/net.h" 47 #include "sysemu/device_tree.h" 48 #include "sysemu/numa.h" 49 #include "sysemu/runstate.h" 50 #include "sysemu/sysemu.h" 51 #include "sysemu/kvm.h" 52 #include "hw/loader.h" 53 #include "exec/address-spaces.h" 54 #include "qemu/bitops.h" 55 #include "qemu/error-report.h" 56 #include "qemu/module.h" 57 #include "hw/pci-host/gpex.h" 58 #include "hw/virtio/virtio-pci.h" 59 #include "hw/arm/sysbus-fdt.h" 60 #include "hw/platform-bus.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/arm/fdt.h" 63 #include "hw/intc/arm_gic.h" 64 #include "hw/intc/arm_gicv3_common.h" 65 #include "hw/irq.h" 66 #include "kvm_arm.h" 67 #include "hw/firmware/smbios.h" 68 #include "qapi/visitor.h" 69 #include "standard-headers/linux/input.h" 70 #include "hw/arm/smmuv3.h" 71 #include "hw/acpi/acpi.h" 72 #include "target/arm/internals.h" 73 #include "hw/mem/pc-dimm.h" 74 #include "hw/mem/nvdimm.h" 75 #include "hw/acpi/generic_event_device.h" 76 #include "hw/virtio/virtio-iommu.h" 77 78 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 79 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 80 void *data) \ 81 { \ 82 MachineClass *mc = MACHINE_CLASS(oc); \ 83 virt_machine_##major##_##minor##_options(mc); \ 84 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 85 if (latest) { \ 86 mc->alias = "virt"; \ 87 } \ 88 } \ 89 static const TypeInfo machvirt_##major##_##minor##_info = { \ 90 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 91 .parent = TYPE_VIRT_MACHINE, \ 92 .class_init = virt_##major##_##minor##_class_init, \ 93 }; \ 94 static void machvirt_machine_##major##_##minor##_init(void) \ 95 { \ 96 type_register_static(&machvirt_##major##_##minor##_info); \ 97 } \ 98 type_init(machvirt_machine_##major##_##minor##_init); 99 100 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 101 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 102 #define DEFINE_VIRT_MACHINE(major, minor) \ 103 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 104 105 106 /* Number of external interrupt lines to configure the GIC with */ 107 #define NUM_IRQS 256 108 109 #define PLATFORM_BUS_NUM_IRQS 64 110 111 /* Legacy RAM limit in GB (< version 4.0) */ 112 #define LEGACY_RAMLIMIT_GB 255 113 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 114 115 /* Addresses and sizes of our components. 116 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 117 * 128MB..256MB is used for miscellaneous device I/O. 118 * 256MB..1GB is reserved for possible future PCI support (ie where the 119 * PCI memory window will go if we add a PCI host controller). 120 * 1GB and up is RAM (which may happily spill over into the 121 * high memory region beyond 4GB). 122 * This represents a compromise between how much RAM can be given to 123 * a 32 bit VM and leaving space for expansion and in particular for PCI. 124 * Note that devices should generally be placed at multiples of 0x10000, 125 * to accommodate guests using 64K pages. 126 */ 127 static const MemMapEntry base_memmap[] = { 128 /* Space up to 0x8000000 is reserved for a boot ROM */ 129 [VIRT_FLASH] = { 0, 0x08000000 }, 130 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 131 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 132 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 133 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 134 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 135 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 136 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 137 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 138 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 139 /* This redistributor space allows up to 2*64kB*123 CPUs */ 140 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 141 [VIRT_UART] = { 0x09000000, 0x00001000 }, 142 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 143 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 144 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 145 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 146 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 147 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 148 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 149 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 150 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 151 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 152 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 153 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 154 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 155 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 156 /* Actual RAM size depends on initial RAM and device memory settings */ 157 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 158 }; 159 160 /* 161 * Highmem IO Regions: This memory map is floating, located after the RAM. 162 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 163 * top of the RAM, so that its base get the same alignment as the size, 164 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 165 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 166 * Note the extended_memmap is sized so that it eventually also includes the 167 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 168 * index of base_memmap). 169 */ 170 static MemMapEntry extended_memmap[] = { 171 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 172 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 173 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 174 /* Second PCIe window */ 175 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 176 }; 177 178 static const int a15irqmap[] = { 179 [VIRT_UART] = 1, 180 [VIRT_RTC] = 2, 181 [VIRT_PCIE] = 3, /* ... to 6 */ 182 [VIRT_GPIO] = 7, 183 [VIRT_SECURE_UART] = 8, 184 [VIRT_ACPI_GED] = 9, 185 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 186 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 187 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 188 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 189 }; 190 191 static const char *valid_cpus[] = { 192 ARM_CPU_TYPE_NAME("cortex-a7"), 193 ARM_CPU_TYPE_NAME("cortex-a15"), 194 ARM_CPU_TYPE_NAME("cortex-a53"), 195 ARM_CPU_TYPE_NAME("cortex-a57"), 196 ARM_CPU_TYPE_NAME("cortex-a72"), 197 ARM_CPU_TYPE_NAME("host"), 198 ARM_CPU_TYPE_NAME("max"), 199 }; 200 201 static bool cpu_type_valid(const char *cpu) 202 { 203 int i; 204 205 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 206 if (strcmp(cpu, valid_cpus[i]) == 0) { 207 return true; 208 } 209 } 210 return false; 211 } 212 213 static void create_fdt(VirtMachineState *vms) 214 { 215 MachineState *ms = MACHINE(vms); 216 int nb_numa_nodes = ms->numa_state->num_nodes; 217 void *fdt = create_device_tree(&vms->fdt_size); 218 219 if (!fdt) { 220 error_report("create_device_tree() failed"); 221 exit(1); 222 } 223 224 vms->fdt = fdt; 225 226 /* Header */ 227 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 228 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 229 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 230 231 /* /chosen must exist for load_dtb to fill in necessary properties later */ 232 qemu_fdt_add_subnode(fdt, "/chosen"); 233 234 /* Clock node, for the benefit of the UART. The kernel device tree 235 * binding documentation claims the PL011 node clock properties are 236 * optional but in practice if you omit them the kernel refuses to 237 * probe for the device. 238 */ 239 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 240 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 241 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 242 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 243 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 244 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 245 "clk24mhz"); 246 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 247 248 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 249 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 250 uint32_t *matrix = g_malloc0(size); 251 int idx, i, j; 252 253 for (i = 0; i < nb_numa_nodes; i++) { 254 for (j = 0; j < nb_numa_nodes; j++) { 255 idx = (i * nb_numa_nodes + j) * 3; 256 matrix[idx + 0] = cpu_to_be32(i); 257 matrix[idx + 1] = cpu_to_be32(j); 258 matrix[idx + 2] = 259 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 260 } 261 } 262 263 qemu_fdt_add_subnode(fdt, "/distance-map"); 264 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 265 "numa-distance-map-v1"); 266 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 267 matrix, size); 268 g_free(matrix); 269 } 270 } 271 272 static void fdt_add_timer_nodes(const VirtMachineState *vms) 273 { 274 /* On real hardware these interrupts are level-triggered. 275 * On KVM they were edge-triggered before host kernel version 4.4, 276 * and level-triggered afterwards. 277 * On emulated QEMU they are level-triggered. 278 * 279 * Getting the DTB info about them wrong is awkward for some 280 * guest kernels: 281 * pre-4.8 ignore the DT and leave the interrupt configured 282 * with whatever the GIC reset value (or the bootloader) left it at 283 * 4.8 before rc6 honour the incorrect data by programming it back 284 * into the GIC, causing problems 285 * 4.8rc6 and later ignore the DT and always write "level triggered" 286 * into the GIC 287 * 288 * For backwards-compatibility, virt-2.8 and earlier will continue 289 * to say these are edge-triggered, but later machines will report 290 * the correct information. 291 */ 292 ARMCPU *armcpu; 293 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 294 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 295 296 if (vmc->claim_edge_triggered_timers) { 297 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 298 } 299 300 if (vms->gic_version == 2) { 301 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 302 GIC_FDT_IRQ_PPI_CPU_WIDTH, 303 (1 << vms->smp_cpus) - 1); 304 } 305 306 qemu_fdt_add_subnode(vms->fdt, "/timer"); 307 308 armcpu = ARM_CPU(qemu_get_cpu(0)); 309 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 310 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 311 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 312 compat, sizeof(compat)); 313 } else { 314 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 315 "arm,armv7-timer"); 316 } 317 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 318 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 319 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 320 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 321 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 322 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 323 } 324 325 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 326 { 327 int cpu; 328 int addr_cells = 1; 329 const MachineState *ms = MACHINE(vms); 330 331 /* 332 * From Documentation/devicetree/bindings/arm/cpus.txt 333 * On ARM v8 64-bit systems value should be set to 2, 334 * that corresponds to the MPIDR_EL1 register size. 335 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 336 * in the system, #address-cells can be set to 1, since 337 * MPIDR_EL1[63:32] bits are not used for CPUs 338 * identification. 339 * 340 * Here we actually don't know whether our system is 32- or 64-bit one. 341 * The simplest way to go is to examine affinity IDs of all our CPUs. If 342 * at least one of them has Aff3 populated, we set #address-cells to 2. 343 */ 344 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 345 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 346 347 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 348 addr_cells = 2; 349 break; 350 } 351 } 352 353 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 354 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 355 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 356 357 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 358 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 359 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 360 CPUState *cs = CPU(armcpu); 361 362 qemu_fdt_add_subnode(vms->fdt, nodename); 363 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 364 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 365 armcpu->dtb_compatible); 366 367 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 368 && vms->smp_cpus > 1) { 369 qemu_fdt_setprop_string(vms->fdt, nodename, 370 "enable-method", "psci"); 371 } 372 373 if (addr_cells == 2) { 374 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 375 armcpu->mp_affinity); 376 } else { 377 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 378 armcpu->mp_affinity); 379 } 380 381 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 382 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 383 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 384 } 385 386 g_free(nodename); 387 } 388 } 389 390 static void fdt_add_its_gic_node(VirtMachineState *vms) 391 { 392 char *nodename; 393 394 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 395 nodename = g_strdup_printf("/intc/its@%" PRIx64, 396 vms->memmap[VIRT_GIC_ITS].base); 397 qemu_fdt_add_subnode(vms->fdt, nodename); 398 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 399 "arm,gic-v3-its"); 400 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 401 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 402 2, vms->memmap[VIRT_GIC_ITS].base, 403 2, vms->memmap[VIRT_GIC_ITS].size); 404 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 405 g_free(nodename); 406 } 407 408 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 409 { 410 char *nodename; 411 412 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 413 vms->memmap[VIRT_GIC_V2M].base); 414 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 415 qemu_fdt_add_subnode(vms->fdt, nodename); 416 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 417 "arm,gic-v2m-frame"); 418 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 419 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 420 2, vms->memmap[VIRT_GIC_V2M].base, 421 2, vms->memmap[VIRT_GIC_V2M].size); 422 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 423 g_free(nodename); 424 } 425 426 static void fdt_add_gic_node(VirtMachineState *vms) 427 { 428 char *nodename; 429 430 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 431 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 432 433 nodename = g_strdup_printf("/intc@%" PRIx64, 434 vms->memmap[VIRT_GIC_DIST].base); 435 qemu_fdt_add_subnode(vms->fdt, nodename); 436 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); 437 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); 438 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); 439 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); 440 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); 441 if (vms->gic_version == 3) { 442 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 443 444 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 445 "arm,gic-v3"); 446 447 qemu_fdt_setprop_cell(vms->fdt, nodename, 448 "#redistributor-regions", nb_redist_regions); 449 450 if (nb_redist_regions == 1) { 451 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 452 2, vms->memmap[VIRT_GIC_DIST].base, 453 2, vms->memmap[VIRT_GIC_DIST].size, 454 2, vms->memmap[VIRT_GIC_REDIST].base, 455 2, vms->memmap[VIRT_GIC_REDIST].size); 456 } else { 457 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 458 2, vms->memmap[VIRT_GIC_DIST].base, 459 2, vms->memmap[VIRT_GIC_DIST].size, 460 2, vms->memmap[VIRT_GIC_REDIST].base, 461 2, vms->memmap[VIRT_GIC_REDIST].size, 462 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 463 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 464 } 465 466 if (vms->virt) { 467 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 468 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 469 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 470 } 471 } else { 472 /* 'cortex-a15-gic' means 'GIC v2' */ 473 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 474 "arm,cortex-a15-gic"); 475 if (!vms->virt) { 476 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 477 2, vms->memmap[VIRT_GIC_DIST].base, 478 2, vms->memmap[VIRT_GIC_DIST].size, 479 2, vms->memmap[VIRT_GIC_CPU].base, 480 2, vms->memmap[VIRT_GIC_CPU].size); 481 } else { 482 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 483 2, vms->memmap[VIRT_GIC_DIST].base, 484 2, vms->memmap[VIRT_GIC_DIST].size, 485 2, vms->memmap[VIRT_GIC_CPU].base, 486 2, vms->memmap[VIRT_GIC_CPU].size, 487 2, vms->memmap[VIRT_GIC_HYP].base, 488 2, vms->memmap[VIRT_GIC_HYP].size, 489 2, vms->memmap[VIRT_GIC_VCPU].base, 490 2, vms->memmap[VIRT_GIC_VCPU].size); 491 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 492 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 493 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 494 } 495 } 496 497 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); 498 g_free(nodename); 499 } 500 501 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 502 { 503 CPUState *cpu; 504 ARMCPU *armcpu; 505 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 506 507 CPU_FOREACH(cpu) { 508 armcpu = ARM_CPU(cpu); 509 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 510 return; 511 } 512 if (kvm_enabled()) { 513 if (kvm_irqchip_in_kernel()) { 514 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 515 } 516 kvm_arm_pmu_init(cpu); 517 } 518 } 519 520 if (vms->gic_version == 2) { 521 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 522 GIC_FDT_IRQ_PPI_CPU_WIDTH, 523 (1 << vms->smp_cpus) - 1); 524 } 525 526 armcpu = ARM_CPU(qemu_get_cpu(0)); 527 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 528 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 529 const char compat[] = "arm,armv8-pmuv3"; 530 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 531 compat, sizeof(compat)); 532 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 533 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 534 } 535 } 536 537 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 538 { 539 DeviceState *dev; 540 MachineState *ms = MACHINE(vms); 541 int irq = vms->irqmap[VIRT_ACPI_GED]; 542 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 543 544 if (ms->ram_slots) { 545 event |= ACPI_GED_MEM_HOTPLUG_EVT; 546 } 547 548 dev = qdev_create(NULL, TYPE_ACPI_GED); 549 qdev_prop_set_uint32(dev, "ged-event", event); 550 551 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 552 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 553 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 554 555 qdev_init_nofail(dev); 556 557 return dev; 558 } 559 560 static void create_its(VirtMachineState *vms) 561 { 562 const char *itsclass = its_class_name(); 563 DeviceState *dev; 564 565 if (!itsclass) { 566 /* Do nothing if not supported */ 567 return; 568 } 569 570 dev = qdev_create(NULL, itsclass); 571 572 object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", 573 &error_abort); 574 qdev_init_nofail(dev); 575 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 576 577 fdt_add_its_gic_node(vms); 578 } 579 580 static void create_v2m(VirtMachineState *vms) 581 { 582 int i; 583 int irq = vms->irqmap[VIRT_GIC_V2M]; 584 DeviceState *dev; 585 586 dev = qdev_create(NULL, "arm-gicv2m"); 587 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 588 qdev_prop_set_uint32(dev, "base-spi", irq); 589 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 590 qdev_init_nofail(dev); 591 592 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 593 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 594 qdev_get_gpio_in(vms->gic, irq + i)); 595 } 596 597 fdt_add_v2m_gic_node(vms); 598 } 599 600 static void create_gic(VirtMachineState *vms) 601 { 602 MachineState *ms = MACHINE(vms); 603 /* We create a standalone GIC */ 604 SysBusDevice *gicbusdev; 605 const char *gictype; 606 int type = vms->gic_version, i; 607 unsigned int smp_cpus = ms->smp.cpus; 608 uint32_t nb_redist_regions = 0; 609 610 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 611 612 vms->gic = qdev_create(NULL, gictype); 613 qdev_prop_set_uint32(vms->gic, "revision", type); 614 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 615 /* Note that the num-irq property counts both internal and external 616 * interrupts; there are always 32 of the former (mandated by GIC spec). 617 */ 618 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 619 if (!kvm_irqchip_in_kernel()) { 620 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 621 } 622 623 if (type == 3) { 624 uint32_t redist0_capacity = 625 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 626 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 627 628 nb_redist_regions = virt_gicv3_redist_region_count(vms); 629 630 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 631 nb_redist_regions); 632 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 633 634 if (nb_redist_regions == 2) { 635 uint32_t redist1_capacity = 636 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 637 638 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 639 MIN(smp_cpus - redist0_count, redist1_capacity)); 640 } 641 } else { 642 if (!kvm_irqchip_in_kernel()) { 643 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 644 vms->virt); 645 } 646 } 647 qdev_init_nofail(vms->gic); 648 gicbusdev = SYS_BUS_DEVICE(vms->gic); 649 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 650 if (type == 3) { 651 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 652 if (nb_redist_regions == 2) { 653 sysbus_mmio_map(gicbusdev, 2, 654 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 655 } 656 } else { 657 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 658 if (vms->virt) { 659 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 660 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 661 } 662 } 663 664 /* Wire the outputs from each CPU's generic timer and the GICv3 665 * maintenance interrupt signal to the appropriate GIC PPI inputs, 666 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 667 */ 668 for (i = 0; i < smp_cpus; i++) { 669 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 670 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 671 int irq; 672 /* Mapping from the output timer irq lines from the CPU to the 673 * GIC PPI inputs we use for the virt board. 674 */ 675 const int timer_irq[] = { 676 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 677 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 678 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 679 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 680 }; 681 682 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 683 qdev_connect_gpio_out(cpudev, irq, 684 qdev_get_gpio_in(vms->gic, 685 ppibase + timer_irq[irq])); 686 } 687 688 if (type == 3) { 689 qemu_irq irq = qdev_get_gpio_in(vms->gic, 690 ppibase + ARCH_GIC_MAINT_IRQ); 691 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 692 0, irq); 693 } else if (vms->virt) { 694 qemu_irq irq = qdev_get_gpio_in(vms->gic, 695 ppibase + ARCH_GIC_MAINT_IRQ); 696 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 697 } 698 699 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 700 qdev_get_gpio_in(vms->gic, ppibase 701 + VIRTUAL_PMU_IRQ)); 702 703 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 704 sysbus_connect_irq(gicbusdev, i + smp_cpus, 705 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 706 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 707 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 708 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 709 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 710 } 711 712 fdt_add_gic_node(vms); 713 714 if (type == 3 && vms->its) { 715 create_its(vms); 716 } else if (type == 2) { 717 create_v2m(vms); 718 } 719 } 720 721 static void create_uart(const VirtMachineState *vms, int uart, 722 MemoryRegion *mem, Chardev *chr) 723 { 724 char *nodename; 725 hwaddr base = vms->memmap[uart].base; 726 hwaddr size = vms->memmap[uart].size; 727 int irq = vms->irqmap[uart]; 728 const char compat[] = "arm,pl011\0arm,primecell"; 729 const char clocknames[] = "uartclk\0apb_pclk"; 730 DeviceState *dev = qdev_create(NULL, "pl011"); 731 SysBusDevice *s = SYS_BUS_DEVICE(dev); 732 733 qdev_prop_set_chr(dev, "chardev", chr); 734 qdev_init_nofail(dev); 735 memory_region_add_subregion(mem, base, 736 sysbus_mmio_get_region(s, 0)); 737 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 738 739 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 740 qemu_fdt_add_subnode(vms->fdt, nodename); 741 /* Note that we can't use setprop_string because of the embedded NUL */ 742 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 743 compat, sizeof(compat)); 744 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 745 2, base, 2, size); 746 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 747 GIC_FDT_IRQ_TYPE_SPI, irq, 748 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 749 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 750 vms->clock_phandle, vms->clock_phandle); 751 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 752 clocknames, sizeof(clocknames)); 753 754 if (uart == VIRT_UART) { 755 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 756 } else { 757 /* Mark as not usable by the normal world */ 758 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 759 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 760 761 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); 762 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", 763 nodename); 764 } 765 766 g_free(nodename); 767 } 768 769 static void create_rtc(const VirtMachineState *vms) 770 { 771 char *nodename; 772 hwaddr base = vms->memmap[VIRT_RTC].base; 773 hwaddr size = vms->memmap[VIRT_RTC].size; 774 int irq = vms->irqmap[VIRT_RTC]; 775 const char compat[] = "arm,pl031\0arm,primecell"; 776 777 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 778 779 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 780 qemu_fdt_add_subnode(vms->fdt, nodename); 781 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 782 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 783 2, base, 2, size); 784 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 785 GIC_FDT_IRQ_TYPE_SPI, irq, 786 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 787 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 788 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 789 g_free(nodename); 790 } 791 792 static DeviceState *gpio_key_dev; 793 static void virt_powerdown_req(Notifier *n, void *opaque) 794 { 795 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 796 797 if (s->acpi_dev) { 798 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 799 } else { 800 /* use gpio Pin 3 for power button event */ 801 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 802 } 803 } 804 805 static void create_gpio(const VirtMachineState *vms) 806 { 807 char *nodename; 808 DeviceState *pl061_dev; 809 hwaddr base = vms->memmap[VIRT_GPIO].base; 810 hwaddr size = vms->memmap[VIRT_GPIO].size; 811 int irq = vms->irqmap[VIRT_GPIO]; 812 const char compat[] = "arm,pl061\0arm,primecell"; 813 814 pl061_dev = sysbus_create_simple("pl061", base, 815 qdev_get_gpio_in(vms->gic, irq)); 816 817 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 818 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 819 qemu_fdt_add_subnode(vms->fdt, nodename); 820 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 821 2, base, 2, size); 822 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 823 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 824 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 825 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 826 GIC_FDT_IRQ_TYPE_SPI, irq, 827 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 828 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 829 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 830 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 831 832 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 833 qdev_get_gpio_in(pl061_dev, 3)); 834 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 835 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 836 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 837 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 838 839 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 840 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 841 "label", "GPIO Key Poweroff"); 842 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 843 KEY_POWER); 844 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 845 "gpios", phandle, 3, 0); 846 g_free(nodename); 847 } 848 849 static void create_virtio_devices(const VirtMachineState *vms) 850 { 851 int i; 852 hwaddr size = vms->memmap[VIRT_MMIO].size; 853 854 /* We create the transports in forwards order. Since qbus_realize() 855 * prepends (not appends) new child buses, the incrementing loop below will 856 * create a list of virtio-mmio buses with decreasing base addresses. 857 * 858 * When a -device option is processed from the command line, 859 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 860 * order. The upshot is that -device options in increasing command line 861 * order are mapped to virtio-mmio buses with decreasing base addresses. 862 * 863 * When this code was originally written, that arrangement ensured that the 864 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 865 * the first -device on the command line. (The end-to-end order is a 866 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 867 * guest kernel's name-to-address assignment strategy.) 868 * 869 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 870 * the message, if not necessarily the code, of commit 70161ff336. 871 * Therefore the loop now establishes the inverse of the original intent. 872 * 873 * Unfortunately, we can't counteract the kernel change by reversing the 874 * loop; it would break existing command lines. 875 * 876 * In any case, the kernel makes no guarantee about the stability of 877 * enumeration order of virtio devices (as demonstrated by it changing 878 * between kernel versions). For reliable and stable identification 879 * of disks users must use UUIDs or similar mechanisms. 880 */ 881 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 882 int irq = vms->irqmap[VIRT_MMIO] + i; 883 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 884 885 sysbus_create_simple("virtio-mmio", base, 886 qdev_get_gpio_in(vms->gic, irq)); 887 } 888 889 /* We add dtb nodes in reverse order so that they appear in the finished 890 * device tree lowest address first. 891 * 892 * Note that this mapping is independent of the loop above. The previous 893 * loop influences virtio device to virtio transport assignment, whereas 894 * this loop controls how virtio transports are laid out in the dtb. 895 */ 896 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 897 char *nodename; 898 int irq = vms->irqmap[VIRT_MMIO] + i; 899 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 900 901 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 902 qemu_fdt_add_subnode(vms->fdt, nodename); 903 qemu_fdt_setprop_string(vms->fdt, nodename, 904 "compatible", "virtio,mmio"); 905 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 906 2, base, 2, size); 907 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 908 GIC_FDT_IRQ_TYPE_SPI, irq, 909 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 910 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 911 g_free(nodename); 912 } 913 } 914 915 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 916 917 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 918 const char *name, 919 const char *alias_prop_name) 920 { 921 /* 922 * Create a single flash device. We use the same parameters as 923 * the flash devices on the Versatile Express board. 924 */ 925 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 926 927 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 928 qdev_prop_set_uint8(dev, "width", 4); 929 qdev_prop_set_uint8(dev, "device-width", 2); 930 qdev_prop_set_bit(dev, "big-endian", false); 931 qdev_prop_set_uint16(dev, "id0", 0x89); 932 qdev_prop_set_uint16(dev, "id1", 0x18); 933 qdev_prop_set_uint16(dev, "id2", 0x00); 934 qdev_prop_set_uint16(dev, "id3", 0x00); 935 qdev_prop_set_string(dev, "name", name); 936 object_property_add_child(OBJECT(vms), name, OBJECT(dev), 937 &error_abort); 938 object_property_add_alias(OBJECT(vms), alias_prop_name, 939 OBJECT(dev), "drive", &error_abort); 940 return PFLASH_CFI01(dev); 941 } 942 943 static void virt_flash_create(VirtMachineState *vms) 944 { 945 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 946 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 947 } 948 949 static void virt_flash_map1(PFlashCFI01 *flash, 950 hwaddr base, hwaddr size, 951 MemoryRegion *sysmem) 952 { 953 DeviceState *dev = DEVICE(flash); 954 955 assert(size % VIRT_FLASH_SECTOR_SIZE == 0); 956 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 957 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 958 qdev_init_nofail(dev); 959 960 memory_region_add_subregion(sysmem, base, 961 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 962 0)); 963 } 964 965 static void virt_flash_map(VirtMachineState *vms, 966 MemoryRegion *sysmem, 967 MemoryRegion *secure_sysmem) 968 { 969 /* 970 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 971 * sysmem is the system memory space. secure_sysmem is the secure view 972 * of the system, and the first flash device should be made visible only 973 * there. The second flash device is visible to both secure and nonsecure. 974 * If sysmem == secure_sysmem this means there is no separate Secure 975 * address space and both flash devices are generally visible. 976 */ 977 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 978 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 979 980 virt_flash_map1(vms->flash[0], flashbase, flashsize, 981 secure_sysmem); 982 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 983 sysmem); 984 } 985 986 static void virt_flash_fdt(VirtMachineState *vms, 987 MemoryRegion *sysmem, 988 MemoryRegion *secure_sysmem) 989 { 990 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 991 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 992 char *nodename; 993 994 if (sysmem == secure_sysmem) { 995 /* Report both flash devices as a single node in the DT */ 996 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 997 qemu_fdt_add_subnode(vms->fdt, nodename); 998 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 999 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1000 2, flashbase, 2, flashsize, 1001 2, flashbase + flashsize, 2, flashsize); 1002 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1003 g_free(nodename); 1004 } else { 1005 /* 1006 * Report the devices as separate nodes so we can mark one as 1007 * only visible to the secure world. 1008 */ 1009 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1010 qemu_fdt_add_subnode(vms->fdt, nodename); 1011 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1012 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1013 2, flashbase, 2, flashsize); 1014 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1015 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1016 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1017 g_free(nodename); 1018 1019 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1020 qemu_fdt_add_subnode(vms->fdt, nodename); 1021 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1022 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1023 2, flashbase + flashsize, 2, flashsize); 1024 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1025 g_free(nodename); 1026 } 1027 } 1028 1029 static bool virt_firmware_init(VirtMachineState *vms, 1030 MemoryRegion *sysmem, 1031 MemoryRegion *secure_sysmem) 1032 { 1033 int i; 1034 BlockBackend *pflash_blk0; 1035 1036 /* Map legacy -drive if=pflash to machine properties */ 1037 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1038 pflash_cfi01_legacy_drive(vms->flash[i], 1039 drive_get(IF_PFLASH, 0, i)); 1040 } 1041 1042 virt_flash_map(vms, sysmem, secure_sysmem); 1043 1044 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1045 1046 if (bios_name) { 1047 char *fname; 1048 MemoryRegion *mr; 1049 int image_size; 1050 1051 if (pflash_blk0) { 1052 error_report("The contents of the first flash device may be " 1053 "specified with -bios or with -drive if=pflash... " 1054 "but you cannot use both options at once"); 1055 exit(1); 1056 } 1057 1058 /* Fall back to -bios */ 1059 1060 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1061 if (!fname) { 1062 error_report("Could not find ROM image '%s'", bios_name); 1063 exit(1); 1064 } 1065 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1066 image_size = load_image_mr(fname, mr); 1067 g_free(fname); 1068 if (image_size < 0) { 1069 error_report("Could not load ROM image '%s'", bios_name); 1070 exit(1); 1071 } 1072 } 1073 1074 return pflash_blk0 || bios_name; 1075 } 1076 1077 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1078 { 1079 MachineState *ms = MACHINE(vms); 1080 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1081 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1082 FWCfgState *fw_cfg; 1083 char *nodename; 1084 1085 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1086 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1087 1088 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1089 qemu_fdt_add_subnode(vms->fdt, nodename); 1090 qemu_fdt_setprop_string(vms->fdt, nodename, 1091 "compatible", "qemu,fw-cfg-mmio"); 1092 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1093 2, base, 2, size); 1094 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1095 g_free(nodename); 1096 return fw_cfg; 1097 } 1098 1099 static void create_pcie_irq_map(const VirtMachineState *vms, 1100 uint32_t gic_phandle, 1101 int first_irq, const char *nodename) 1102 { 1103 int devfn, pin; 1104 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1105 uint32_t *irq_map = full_irq_map; 1106 1107 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1108 for (pin = 0; pin < 4; pin++) { 1109 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1110 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1111 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1112 int i; 1113 1114 uint32_t map[] = { 1115 devfn << 8, 0, 0, /* devfn */ 1116 pin + 1, /* PCI pin */ 1117 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1118 1119 /* Convert map to big endian */ 1120 for (i = 0; i < 10; i++) { 1121 irq_map[i] = cpu_to_be32(map[i]); 1122 } 1123 irq_map += 10; 1124 } 1125 } 1126 1127 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 1128 full_irq_map, sizeof(full_irq_map)); 1129 1130 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1131 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1132 0x7 /* PCI irq */); 1133 } 1134 1135 static void create_smmu(const VirtMachineState *vms, 1136 PCIBus *bus) 1137 { 1138 char *node; 1139 const char compat[] = "arm,smmu-v3"; 1140 int irq = vms->irqmap[VIRT_SMMU]; 1141 int i; 1142 hwaddr base = vms->memmap[VIRT_SMMU].base; 1143 hwaddr size = vms->memmap[VIRT_SMMU].size; 1144 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1145 DeviceState *dev; 1146 1147 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1148 return; 1149 } 1150 1151 dev = qdev_create(NULL, "arm-smmuv3"); 1152 1153 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1154 &error_abort); 1155 qdev_init_nofail(dev); 1156 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1157 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1158 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1159 qdev_get_gpio_in(vms->gic, irq + i)); 1160 } 1161 1162 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1163 qemu_fdt_add_subnode(vms->fdt, node); 1164 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1165 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 1166 1167 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 1168 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1169 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1170 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1171 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1172 1173 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 1174 sizeof(irq_names)); 1175 1176 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 1177 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 1178 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 1179 1180 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1181 1182 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1183 g_free(node); 1184 } 1185 1186 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms, Error **errp) 1187 { 1188 const char compat[] = "virtio,pci-iommu"; 1189 uint16_t bdf = vms->virtio_iommu_bdf; 1190 char *node; 1191 1192 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1193 1194 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1195 qemu_fdt_add_subnode(vms->fdt, node); 1196 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1197 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 1198 1, bdf << 8, 1, 0, 1, 0, 1199 1, 0, 1, 0); 1200 1201 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1202 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1203 g_free(node); 1204 1205 qemu_fdt_setprop_cells(vms->fdt, vms->pciehb_nodename, "iommu-map", 1206 0x0, vms->iommu_phandle, 0x0, bdf, 1207 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1208 } 1209 1210 static void create_pcie(VirtMachineState *vms) 1211 { 1212 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1213 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1214 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1215 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1216 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1217 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1218 hwaddr base_ecam, size_ecam; 1219 hwaddr base = base_mmio; 1220 int nr_pcie_buses; 1221 int irq = vms->irqmap[VIRT_PCIE]; 1222 MemoryRegion *mmio_alias; 1223 MemoryRegion *mmio_reg; 1224 MemoryRegion *ecam_alias; 1225 MemoryRegion *ecam_reg; 1226 DeviceState *dev; 1227 char *nodename; 1228 int i, ecam_id; 1229 PCIHostState *pci; 1230 1231 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1232 qdev_init_nofail(dev); 1233 1234 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1235 base_ecam = vms->memmap[ecam_id].base; 1236 size_ecam = vms->memmap[ecam_id].size; 1237 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1238 /* Map only the first size_ecam bytes of ECAM space */ 1239 ecam_alias = g_new0(MemoryRegion, 1); 1240 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1241 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1242 ecam_reg, 0, size_ecam); 1243 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1244 1245 /* Map the MMIO window into system address space so as to expose 1246 * the section of PCI MMIO space which starts at the same base address 1247 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1248 * the window). 1249 */ 1250 mmio_alias = g_new0(MemoryRegion, 1); 1251 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1252 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1253 mmio_reg, base_mmio, size_mmio); 1254 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1255 1256 if (vms->highmem) { 1257 /* Map high MMIO space */ 1258 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1259 1260 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1261 mmio_reg, base_mmio_high, size_mmio_high); 1262 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1263 high_mmio_alias); 1264 } 1265 1266 /* Map IO port space */ 1267 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1268 1269 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1270 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1271 qdev_get_gpio_in(vms->gic, irq + i)); 1272 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1273 } 1274 1275 pci = PCI_HOST_BRIDGE(dev); 1276 if (pci->bus) { 1277 for (i = 0; i < nb_nics; i++) { 1278 NICInfo *nd = &nd_table[i]; 1279 1280 if (!nd->model) { 1281 nd->model = g_strdup("virtio"); 1282 } 1283 1284 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1285 } 1286 } 1287 1288 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1289 qemu_fdt_add_subnode(vms->fdt, nodename); 1290 qemu_fdt_setprop_string(vms->fdt, nodename, 1291 "compatible", "pci-host-ecam-generic"); 1292 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1293 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1294 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1295 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1296 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1297 nr_pcie_buses - 1); 1298 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1299 1300 if (vms->msi_phandle) { 1301 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1302 vms->msi_phandle); 1303 } 1304 1305 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1306 2, base_ecam, 2, size_ecam); 1307 1308 if (vms->highmem) { 1309 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1310 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1311 2, base_pio, 2, size_pio, 1312 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1313 2, base_mmio, 2, size_mmio, 1314 1, FDT_PCI_RANGE_MMIO_64BIT, 1315 2, base_mmio_high, 1316 2, base_mmio_high, 2, size_mmio_high); 1317 } else { 1318 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1319 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1320 2, base_pio, 2, size_pio, 1321 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1322 2, base_mmio, 2, size_mmio); 1323 } 1324 1325 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1326 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1327 1328 if (vms->iommu) { 1329 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1330 1331 switch (vms->iommu) { 1332 case VIRT_IOMMU_SMMUV3: 1333 create_smmu(vms, pci->bus); 1334 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1335 0x0, vms->iommu_phandle, 0x0, 0x10000); 1336 break; 1337 default: 1338 g_assert_not_reached(); 1339 } 1340 } 1341 } 1342 1343 static void create_platform_bus(VirtMachineState *vms) 1344 { 1345 DeviceState *dev; 1346 SysBusDevice *s; 1347 int i; 1348 MemoryRegion *sysmem = get_system_memory(); 1349 1350 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1351 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1352 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1353 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1354 qdev_init_nofail(dev); 1355 vms->platform_bus_dev = dev; 1356 1357 s = SYS_BUS_DEVICE(dev); 1358 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1359 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1360 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1361 } 1362 1363 memory_region_add_subregion(sysmem, 1364 vms->memmap[VIRT_PLATFORM_BUS].base, 1365 sysbus_mmio_get_region(s, 0)); 1366 } 1367 1368 static void create_secure_ram(VirtMachineState *vms, 1369 MemoryRegion *secure_sysmem) 1370 { 1371 MemoryRegion *secram = g_new(MemoryRegion, 1); 1372 char *nodename; 1373 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1374 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1375 1376 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1377 &error_fatal); 1378 memory_region_add_subregion(secure_sysmem, base, secram); 1379 1380 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1381 qemu_fdt_add_subnode(vms->fdt, nodename); 1382 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1383 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1384 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1385 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1386 1387 g_free(nodename); 1388 } 1389 1390 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1391 { 1392 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1393 bootinfo); 1394 1395 *fdt_size = board->fdt_size; 1396 return board->fdt; 1397 } 1398 1399 static void virt_build_smbios(VirtMachineState *vms) 1400 { 1401 MachineClass *mc = MACHINE_GET_CLASS(vms); 1402 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1403 uint8_t *smbios_tables, *smbios_anchor; 1404 size_t smbios_tables_len, smbios_anchor_len; 1405 const char *product = "QEMU Virtual Machine"; 1406 1407 if (kvm_enabled()) { 1408 product = "KVM Virtual Machine"; 1409 } 1410 1411 smbios_set_defaults("QEMU", product, 1412 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1413 true, SMBIOS_ENTRY_POINT_30); 1414 1415 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len, 1416 &smbios_anchor, &smbios_anchor_len); 1417 1418 if (smbios_anchor) { 1419 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1420 smbios_tables, smbios_tables_len); 1421 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1422 smbios_anchor, smbios_anchor_len); 1423 } 1424 } 1425 1426 static 1427 void virt_machine_done(Notifier *notifier, void *data) 1428 { 1429 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1430 machine_done); 1431 MachineState *ms = MACHINE(vms); 1432 ARMCPU *cpu = ARM_CPU(first_cpu); 1433 struct arm_boot_info *info = &vms->bootinfo; 1434 AddressSpace *as = arm_boot_address_space(cpu, info); 1435 1436 /* 1437 * If the user provided a dtb, we assume the dynamic sysbus nodes 1438 * already are integrated there. This corresponds to a use case where 1439 * the dynamic sysbus nodes are complex and their generation is not yet 1440 * supported. In that case the user can take charge of the guest dt 1441 * while qemu takes charge of the qom stuff. 1442 */ 1443 if (info->dtb_filename == NULL) { 1444 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1445 vms->memmap[VIRT_PLATFORM_BUS].base, 1446 vms->memmap[VIRT_PLATFORM_BUS].size, 1447 vms->irqmap[VIRT_PLATFORM_BUS]); 1448 } 1449 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1450 exit(1); 1451 } 1452 1453 virt_acpi_setup(vms); 1454 virt_build_smbios(vms); 1455 } 1456 1457 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1458 { 1459 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1460 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1461 1462 if (!vmc->disallow_affinity_adjustment) { 1463 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1464 * GIC's target-list limitations. 32-bit KVM hosts currently 1465 * always create clusters of 4 CPUs, but that is expected to 1466 * change when they gain support for gicv3. When KVM is enabled 1467 * it will override the changes we make here, therefore our 1468 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1469 * and to improve SGI efficiency. 1470 */ 1471 if (vms->gic_version == 3) { 1472 clustersz = GICV3_TARGETLIST_BITS; 1473 } else { 1474 clustersz = GIC_TARGETLIST_BITS; 1475 } 1476 } 1477 return arm_cpu_mp_affinity(idx, clustersz); 1478 } 1479 1480 static void virt_set_memmap(VirtMachineState *vms) 1481 { 1482 MachineState *ms = MACHINE(vms); 1483 hwaddr base, device_memory_base, device_memory_size; 1484 int i; 1485 1486 vms->memmap = extended_memmap; 1487 1488 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1489 vms->memmap[i] = base_memmap[i]; 1490 } 1491 1492 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1493 error_report("unsupported number of memory slots: %"PRIu64, 1494 ms->ram_slots); 1495 exit(EXIT_FAILURE); 1496 } 1497 1498 /* 1499 * We compute the base of the high IO region depending on the 1500 * amount of initial and device memory. The device memory start/size 1501 * is aligned on 1GiB. We never put the high IO region below 256GiB 1502 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1503 * The device region size assumes 1GiB page max alignment per slot. 1504 */ 1505 device_memory_base = 1506 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1507 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1508 1509 /* Base address of the high IO region */ 1510 base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1511 if (base < device_memory_base) { 1512 error_report("maxmem/slots too huge"); 1513 exit(EXIT_FAILURE); 1514 } 1515 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1516 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1517 } 1518 1519 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1520 hwaddr size = extended_memmap[i].size; 1521 1522 base = ROUND_UP(base, size); 1523 vms->memmap[i].base = base; 1524 vms->memmap[i].size = size; 1525 base += size; 1526 } 1527 vms->highest_gpa = base - 1; 1528 if (device_memory_size > 0) { 1529 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1530 ms->device_memory->base = device_memory_base; 1531 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1532 "device-memory", device_memory_size); 1533 } 1534 } 1535 1536 static void machvirt_init(MachineState *machine) 1537 { 1538 VirtMachineState *vms = VIRT_MACHINE(machine); 1539 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1540 MachineClass *mc = MACHINE_GET_CLASS(machine); 1541 const CPUArchIdList *possible_cpus; 1542 MemoryRegion *sysmem = get_system_memory(); 1543 MemoryRegion *secure_sysmem = NULL; 1544 int n, virt_max_cpus; 1545 MemoryRegion *ram = g_new(MemoryRegion, 1); 1546 bool firmware_loaded; 1547 bool aarch64 = true; 1548 bool has_ged = !vmc->no_ged; 1549 unsigned int smp_cpus = machine->smp.cpus; 1550 unsigned int max_cpus = machine->smp.max_cpus; 1551 1552 /* 1553 * In accelerated mode, the memory map is computed earlier in kvm_type() 1554 * to create a VM with the right number of IPA bits. 1555 */ 1556 if (!vms->memmap) { 1557 virt_set_memmap(vms); 1558 } 1559 1560 /* We can probe only here because during property set 1561 * KVM is not available yet 1562 */ 1563 if (vms->gic_version <= 0) { 1564 /* "host" or "max" */ 1565 if (!kvm_enabled()) { 1566 if (vms->gic_version == 0) { 1567 error_report("gic-version=host requires KVM"); 1568 exit(1); 1569 } else { 1570 /* "max": currently means 3 for TCG */ 1571 vms->gic_version = 3; 1572 } 1573 } else { 1574 vms->gic_version = kvm_arm_vgic_probe(); 1575 if (!vms->gic_version) { 1576 error_report( 1577 "Unable to determine GIC version supported by host"); 1578 exit(1); 1579 } 1580 } 1581 } 1582 1583 if (!cpu_type_valid(machine->cpu_type)) { 1584 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1585 exit(1); 1586 } 1587 1588 if (vms->secure) { 1589 if (kvm_enabled()) { 1590 error_report("mach-virt: KVM does not support Security extensions"); 1591 exit(1); 1592 } 1593 1594 /* 1595 * The Secure view of the world is the same as the NonSecure, 1596 * but with a few extra devices. Create it as a container region 1597 * containing the system memory at low priority; any secure-only 1598 * devices go in at higher priority and take precedence. 1599 */ 1600 secure_sysmem = g_new(MemoryRegion, 1); 1601 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1602 UINT64_MAX); 1603 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1604 } 1605 1606 firmware_loaded = virt_firmware_init(vms, sysmem, 1607 secure_sysmem ?: sysmem); 1608 1609 /* If we have an EL3 boot ROM then the assumption is that it will 1610 * implement PSCI itself, so disable QEMU's internal implementation 1611 * so it doesn't get in the way. Instead of starting secondary 1612 * CPUs in PSCI powerdown state we will start them all running and 1613 * let the boot ROM sort them out. 1614 * The usual case is that we do use QEMU's PSCI implementation; 1615 * if the guest has EL2 then we will use SMC as the conduit, 1616 * and otherwise we will use HVC (for backwards compatibility and 1617 * because if we're using KVM then we must use HVC). 1618 */ 1619 if (vms->secure && firmware_loaded) { 1620 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1621 } else if (vms->virt) { 1622 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1623 } else { 1624 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1625 } 1626 1627 /* The maximum number of CPUs depends on the GIC version, or on how 1628 * many redistributors we can fit into the memory map. 1629 */ 1630 if (vms->gic_version == 3) { 1631 virt_max_cpus = 1632 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1633 virt_max_cpus += 1634 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1635 } else { 1636 virt_max_cpus = GIC_NCPU; 1637 } 1638 1639 if (max_cpus > virt_max_cpus) { 1640 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1641 "supported by machine 'mach-virt' (%d)", 1642 max_cpus, virt_max_cpus); 1643 exit(1); 1644 } 1645 1646 vms->smp_cpus = smp_cpus; 1647 1648 if (vms->virt && kvm_enabled()) { 1649 error_report("mach-virt: KVM does not support providing " 1650 "Virtualization extensions to the guest CPU"); 1651 exit(1); 1652 } 1653 1654 create_fdt(vms); 1655 1656 possible_cpus = mc->possible_cpu_arch_ids(machine); 1657 for (n = 0; n < possible_cpus->len; n++) { 1658 Object *cpuobj; 1659 CPUState *cs; 1660 1661 if (n >= smp_cpus) { 1662 break; 1663 } 1664 1665 cpuobj = object_new(possible_cpus->cpus[n].type); 1666 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1667 "mp-affinity", NULL); 1668 1669 cs = CPU(cpuobj); 1670 cs->cpu_index = n; 1671 1672 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1673 &error_fatal); 1674 1675 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1676 1677 if (!vms->secure) { 1678 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1679 } 1680 1681 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1682 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1683 } 1684 1685 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1686 object_property_set_int(cpuobj, vms->psci_conduit, 1687 "psci-conduit", NULL); 1688 1689 /* Secondary CPUs start in PSCI powered-down state */ 1690 if (n > 0) { 1691 object_property_set_bool(cpuobj, true, 1692 "start-powered-off", NULL); 1693 } 1694 } 1695 1696 if (vmc->kvm_no_adjvtime && 1697 object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { 1698 object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL); 1699 } 1700 1701 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1702 object_property_set_bool(cpuobj, false, "pmu", NULL); 1703 } 1704 1705 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1706 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1707 "reset-cbar", &error_abort); 1708 } 1709 1710 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1711 &error_abort); 1712 if (vms->secure) { 1713 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1714 "secure-memory", &error_abort); 1715 } 1716 1717 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1718 object_unref(cpuobj); 1719 } 1720 fdt_add_timer_nodes(vms); 1721 fdt_add_cpu_nodes(vms); 1722 1723 if (!kvm_enabled()) { 1724 ARMCPU *cpu = ARM_CPU(first_cpu); 1725 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); 1726 1727 if (aarch64 && vms->highmem) { 1728 int requested_pa_size, pamax = arm_pamax(cpu); 1729 1730 requested_pa_size = 64 - clz64(vms->highest_gpa); 1731 if (pamax < requested_pa_size) { 1732 error_report("VCPU supports less PA bits (%d) than requested " 1733 "by the memory map (%d)", pamax, requested_pa_size); 1734 exit(1); 1735 } 1736 } 1737 } 1738 1739 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1740 machine->ram_size); 1741 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1742 if (machine->device_memory) { 1743 memory_region_add_subregion(sysmem, machine->device_memory->base, 1744 &machine->device_memory->mr); 1745 } 1746 1747 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 1748 1749 create_gic(vms); 1750 1751 fdt_add_pmu_nodes(vms); 1752 1753 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 1754 1755 if (vms->secure) { 1756 create_secure_ram(vms, secure_sysmem); 1757 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1758 } 1759 1760 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 1761 1762 create_rtc(vms); 1763 1764 create_pcie(vms); 1765 1766 if (has_ged && aarch64 && firmware_loaded && acpi_enabled) { 1767 vms->acpi_dev = create_acpi_ged(vms); 1768 } else { 1769 create_gpio(vms); 1770 } 1771 1772 /* connect powerdown request */ 1773 vms->powerdown_notifier.notify = virt_powerdown_req; 1774 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 1775 1776 /* Create mmio transports, so the user can create virtio backends 1777 * (which will be automatically plugged in to the transports). If 1778 * no backend is created the transport will just sit harmlessly idle. 1779 */ 1780 create_virtio_devices(vms); 1781 1782 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1783 rom_set_fw(vms->fw_cfg); 1784 1785 create_platform_bus(vms); 1786 1787 vms->bootinfo.ram_size = machine->ram_size; 1788 vms->bootinfo.nb_cpus = smp_cpus; 1789 vms->bootinfo.board_id = -1; 1790 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1791 vms->bootinfo.get_dtb = machvirt_dtb; 1792 vms->bootinfo.skip_dtb_autoload = true; 1793 vms->bootinfo.firmware_loaded = firmware_loaded; 1794 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 1795 1796 vms->machine_done.notify = virt_machine_done; 1797 qemu_add_machine_init_done_notifier(&vms->machine_done); 1798 } 1799 1800 static bool virt_get_secure(Object *obj, Error **errp) 1801 { 1802 VirtMachineState *vms = VIRT_MACHINE(obj); 1803 1804 return vms->secure; 1805 } 1806 1807 static void virt_set_secure(Object *obj, bool value, Error **errp) 1808 { 1809 VirtMachineState *vms = VIRT_MACHINE(obj); 1810 1811 vms->secure = value; 1812 } 1813 1814 static bool virt_get_virt(Object *obj, Error **errp) 1815 { 1816 VirtMachineState *vms = VIRT_MACHINE(obj); 1817 1818 return vms->virt; 1819 } 1820 1821 static void virt_set_virt(Object *obj, bool value, Error **errp) 1822 { 1823 VirtMachineState *vms = VIRT_MACHINE(obj); 1824 1825 vms->virt = value; 1826 } 1827 1828 static bool virt_get_highmem(Object *obj, Error **errp) 1829 { 1830 VirtMachineState *vms = VIRT_MACHINE(obj); 1831 1832 return vms->highmem; 1833 } 1834 1835 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1836 { 1837 VirtMachineState *vms = VIRT_MACHINE(obj); 1838 1839 vms->highmem = value; 1840 } 1841 1842 static bool virt_get_its(Object *obj, Error **errp) 1843 { 1844 VirtMachineState *vms = VIRT_MACHINE(obj); 1845 1846 return vms->its; 1847 } 1848 1849 static void virt_set_its(Object *obj, bool value, Error **errp) 1850 { 1851 VirtMachineState *vms = VIRT_MACHINE(obj); 1852 1853 vms->its = value; 1854 } 1855 1856 static char *virt_get_gic_version(Object *obj, Error **errp) 1857 { 1858 VirtMachineState *vms = VIRT_MACHINE(obj); 1859 const char *val = vms->gic_version == 3 ? "3" : "2"; 1860 1861 return g_strdup(val); 1862 } 1863 1864 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1865 { 1866 VirtMachineState *vms = VIRT_MACHINE(obj); 1867 1868 if (!strcmp(value, "3")) { 1869 vms->gic_version = 3; 1870 } else if (!strcmp(value, "2")) { 1871 vms->gic_version = 2; 1872 } else if (!strcmp(value, "host")) { 1873 vms->gic_version = 0; /* Will probe later */ 1874 } else if (!strcmp(value, "max")) { 1875 vms->gic_version = -1; /* Will probe later */ 1876 } else { 1877 error_setg(errp, "Invalid gic-version value"); 1878 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 1879 } 1880 } 1881 1882 static char *virt_get_iommu(Object *obj, Error **errp) 1883 { 1884 VirtMachineState *vms = VIRT_MACHINE(obj); 1885 1886 switch (vms->iommu) { 1887 case VIRT_IOMMU_NONE: 1888 return g_strdup("none"); 1889 case VIRT_IOMMU_SMMUV3: 1890 return g_strdup("smmuv3"); 1891 default: 1892 g_assert_not_reached(); 1893 } 1894 } 1895 1896 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 1897 { 1898 VirtMachineState *vms = VIRT_MACHINE(obj); 1899 1900 if (!strcmp(value, "smmuv3")) { 1901 vms->iommu = VIRT_IOMMU_SMMUV3; 1902 } else if (!strcmp(value, "none")) { 1903 vms->iommu = VIRT_IOMMU_NONE; 1904 } else { 1905 error_setg(errp, "Invalid iommu value"); 1906 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 1907 } 1908 } 1909 1910 static CpuInstanceProperties 1911 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1912 { 1913 MachineClass *mc = MACHINE_GET_CLASS(ms); 1914 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1915 1916 assert(cpu_index < possible_cpus->len); 1917 return possible_cpus->cpus[cpu_index].props; 1918 } 1919 1920 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1921 { 1922 return idx % ms->numa_state->num_nodes; 1923 } 1924 1925 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1926 { 1927 int n; 1928 unsigned int max_cpus = ms->smp.max_cpus; 1929 VirtMachineState *vms = VIRT_MACHINE(ms); 1930 1931 if (ms->possible_cpus) { 1932 assert(ms->possible_cpus->len == max_cpus); 1933 return ms->possible_cpus; 1934 } 1935 1936 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1937 sizeof(CPUArchId) * max_cpus); 1938 ms->possible_cpus->len = max_cpus; 1939 for (n = 0; n < ms->possible_cpus->len; n++) { 1940 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1941 ms->possible_cpus->cpus[n].arch_id = 1942 virt_cpu_mp_affinity(vms, n); 1943 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1944 ms->possible_cpus->cpus[n].props.thread_id = n; 1945 } 1946 return ms->possible_cpus; 1947 } 1948 1949 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1950 Error **errp) 1951 { 1952 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 1953 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1954 1955 if (is_nvdimm) { 1956 error_setg(errp, "nvdimm is not yet supported"); 1957 return; 1958 } 1959 1960 if (!vms->acpi_dev) { 1961 error_setg(errp, 1962 "memory hotplug is not enabled: missing acpi-ged device"); 1963 return; 1964 } 1965 1966 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 1967 } 1968 1969 static void virt_memory_plug(HotplugHandler *hotplug_dev, 1970 DeviceState *dev, Error **errp) 1971 { 1972 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 1973 Error *local_err = NULL; 1974 1975 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms), &local_err); 1976 if (local_err) { 1977 goto out; 1978 } 1979 1980 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 1981 dev, &error_abort); 1982 1983 out: 1984 error_propagate(errp, local_err); 1985 } 1986 1987 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1988 DeviceState *dev, Error **errp) 1989 { 1990 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1991 virt_memory_pre_plug(hotplug_dev, dev, errp); 1992 } 1993 } 1994 1995 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1996 DeviceState *dev, Error **errp) 1997 { 1998 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 1999 2000 if (vms->platform_bus_dev) { 2001 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 2002 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2003 SYS_BUS_DEVICE(dev)); 2004 } 2005 } 2006 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2007 virt_memory_plug(hotplug_dev, dev, errp); 2008 } 2009 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2010 PCIDevice *pdev = PCI_DEVICE(dev); 2011 2012 vms->iommu = VIRT_IOMMU_VIRTIO; 2013 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2014 create_virtio_iommu_dt_bindings(vms, errp); 2015 } 2016 } 2017 2018 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2019 DeviceState *dev, Error **errp) 2020 { 2021 error_setg(errp, "device unplug request for unsupported device" 2022 " type: %s", object_get_typename(OBJECT(dev))); 2023 } 2024 2025 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2026 DeviceState *dev) 2027 { 2028 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) || 2029 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { 2030 return HOTPLUG_HANDLER(machine); 2031 } 2032 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2033 VirtMachineState *vms = VIRT_MACHINE(machine); 2034 2035 if (!vms->bootinfo.firmware_loaded || !acpi_enabled) { 2036 return HOTPLUG_HANDLER(machine); 2037 } 2038 } 2039 return NULL; 2040 } 2041 2042 /* 2043 * for arm64 kvm_type [7-0] encodes the requested number of bits 2044 * in the IPA address space 2045 */ 2046 static int virt_kvm_type(MachineState *ms, const char *type_str) 2047 { 2048 VirtMachineState *vms = VIRT_MACHINE(ms); 2049 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms); 2050 int requested_pa_size; 2051 2052 /* we freeze the memory map to compute the highest gpa */ 2053 virt_set_memmap(vms); 2054 2055 requested_pa_size = 64 - clz64(vms->highest_gpa); 2056 2057 if (requested_pa_size > max_vm_pa_size) { 2058 error_report("-m and ,maxmem option values " 2059 "require an IPA range (%d bits) larger than " 2060 "the one supported by the host (%d bits)", 2061 requested_pa_size, max_vm_pa_size); 2062 exit(1); 2063 } 2064 /* 2065 * By default we return 0 which corresponds to an implicit legacy 2066 * 40b IPA setting. Otherwise we return the actual requested PA 2067 * logsize 2068 */ 2069 return requested_pa_size > 40 ? requested_pa_size : 0; 2070 } 2071 2072 static void virt_machine_class_init(ObjectClass *oc, void *data) 2073 { 2074 MachineClass *mc = MACHINE_CLASS(oc); 2075 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2076 2077 mc->init = machvirt_init; 2078 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2079 * The value may be reduced later when we have more information about the 2080 * configuration of the particular instance. 2081 */ 2082 mc->max_cpus = 512; 2083 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2084 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2085 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2086 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2087 mc->block_default_type = IF_VIRTIO; 2088 mc->no_cdrom = 1; 2089 mc->pci_allow_0_address = true; 2090 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2091 mc->minimum_page_bits = 12; 2092 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2093 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2094 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2095 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2096 mc->kvm_type = virt_kvm_type; 2097 assert(!mc->get_hotplug_handler); 2098 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2099 hc->pre_plug = virt_machine_device_pre_plug_cb; 2100 hc->plug = virt_machine_device_plug_cb; 2101 hc->unplug_request = virt_machine_device_unplug_request_cb; 2102 mc->numa_mem_supported = true; 2103 mc->auto_enable_numa_with_memhp = true; 2104 } 2105 2106 static void virt_instance_init(Object *obj) 2107 { 2108 VirtMachineState *vms = VIRT_MACHINE(obj); 2109 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 2110 2111 /* EL3 is disabled by default on virt: this makes us consistent 2112 * between KVM and TCG for this board, and it also allows us to 2113 * boot UEFI blobs which assume no TrustZone support. 2114 */ 2115 vms->secure = false; 2116 object_property_add_bool(obj, "secure", virt_get_secure, 2117 virt_set_secure, NULL); 2118 object_property_set_description(obj, "secure", 2119 "Set on/off to enable/disable the ARM " 2120 "Security Extensions (TrustZone)", 2121 NULL); 2122 2123 /* EL2 is also disabled by default, for similar reasons */ 2124 vms->virt = false; 2125 object_property_add_bool(obj, "virtualization", virt_get_virt, 2126 virt_set_virt, NULL); 2127 object_property_set_description(obj, "virtualization", 2128 "Set on/off to enable/disable emulating a " 2129 "guest CPU which implements the ARM " 2130 "Virtualization Extensions", 2131 NULL); 2132 2133 /* High memory is enabled by default */ 2134 vms->highmem = true; 2135 object_property_add_bool(obj, "highmem", virt_get_highmem, 2136 virt_set_highmem, NULL); 2137 object_property_set_description(obj, "highmem", 2138 "Set on/off to enable/disable using " 2139 "physical address space above 32 bits", 2140 NULL); 2141 /* Default GIC type is v2 */ 2142 vms->gic_version = 2; 2143 object_property_add_str(obj, "gic-version", virt_get_gic_version, 2144 virt_set_gic_version, NULL); 2145 object_property_set_description(obj, "gic-version", 2146 "Set GIC version. " 2147 "Valid values are 2, 3 and host", NULL); 2148 2149 vms->highmem_ecam = !vmc->no_highmem_ecam; 2150 2151 if (vmc->no_its) { 2152 vms->its = false; 2153 } else { 2154 /* Default allows ITS instantiation */ 2155 vms->its = true; 2156 object_property_add_bool(obj, "its", virt_get_its, 2157 virt_set_its, NULL); 2158 object_property_set_description(obj, "its", 2159 "Set on/off to enable/disable " 2160 "ITS instantiation", 2161 NULL); 2162 } 2163 2164 /* Default disallows iommu instantiation */ 2165 vms->iommu = VIRT_IOMMU_NONE; 2166 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); 2167 object_property_set_description(obj, "iommu", 2168 "Set the IOMMU type. " 2169 "Valid values are none and smmuv3", 2170 NULL); 2171 2172 vms->irqmap = a15irqmap; 2173 2174 virt_flash_create(vms); 2175 } 2176 2177 static const TypeInfo virt_machine_info = { 2178 .name = TYPE_VIRT_MACHINE, 2179 .parent = TYPE_MACHINE, 2180 .abstract = true, 2181 .instance_size = sizeof(VirtMachineState), 2182 .class_size = sizeof(VirtMachineClass), 2183 .class_init = virt_machine_class_init, 2184 .instance_init = virt_instance_init, 2185 .interfaces = (InterfaceInfo[]) { 2186 { TYPE_HOTPLUG_HANDLER }, 2187 { } 2188 }, 2189 }; 2190 2191 static void machvirt_machine_init(void) 2192 { 2193 type_register_static(&virt_machine_info); 2194 } 2195 type_init(machvirt_machine_init); 2196 2197 static void virt_machine_5_0_options(MachineClass *mc) 2198 { 2199 } 2200 DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) 2201 2202 static void virt_machine_4_2_options(MachineClass *mc) 2203 { 2204 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2205 2206 virt_machine_5_0_options(mc); 2207 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 2208 vmc->kvm_no_adjvtime = true; 2209 } 2210 DEFINE_VIRT_MACHINE(4, 2) 2211 2212 static void virt_machine_4_1_options(MachineClass *mc) 2213 { 2214 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2215 2216 virt_machine_4_2_options(mc); 2217 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 2218 vmc->no_ged = true; 2219 mc->auto_enable_numa_with_memhp = false; 2220 } 2221 DEFINE_VIRT_MACHINE(4, 1) 2222 2223 static void virt_machine_4_0_options(MachineClass *mc) 2224 { 2225 virt_machine_4_1_options(mc); 2226 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 2227 } 2228 DEFINE_VIRT_MACHINE(4, 0) 2229 2230 static void virt_machine_3_1_options(MachineClass *mc) 2231 { 2232 virt_machine_4_0_options(mc); 2233 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 2234 } 2235 DEFINE_VIRT_MACHINE(3, 1) 2236 2237 static void virt_machine_3_0_options(MachineClass *mc) 2238 { 2239 virt_machine_3_1_options(mc); 2240 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 2241 } 2242 DEFINE_VIRT_MACHINE(3, 0) 2243 2244 static void virt_machine_2_12_options(MachineClass *mc) 2245 { 2246 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2247 2248 virt_machine_3_0_options(mc); 2249 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 2250 vmc->no_highmem_ecam = true; 2251 mc->max_cpus = 255; 2252 } 2253 DEFINE_VIRT_MACHINE(2, 12) 2254 2255 static void virt_machine_2_11_options(MachineClass *mc) 2256 { 2257 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2258 2259 virt_machine_2_12_options(mc); 2260 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 2261 vmc->smbios_old_sys_ver = true; 2262 } 2263 DEFINE_VIRT_MACHINE(2, 11) 2264 2265 static void virt_machine_2_10_options(MachineClass *mc) 2266 { 2267 virt_machine_2_11_options(mc); 2268 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 2269 /* before 2.11 we never faulted accesses to bad addresses */ 2270 mc->ignore_memory_transaction_failures = true; 2271 } 2272 DEFINE_VIRT_MACHINE(2, 10) 2273 2274 static void virt_machine_2_9_options(MachineClass *mc) 2275 { 2276 virt_machine_2_10_options(mc); 2277 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 2278 } 2279 DEFINE_VIRT_MACHINE(2, 9) 2280 2281 static void virt_machine_2_8_options(MachineClass *mc) 2282 { 2283 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2284 2285 virt_machine_2_9_options(mc); 2286 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 2287 /* For 2.8 and earlier we falsely claimed in the DT that 2288 * our timers were edge-triggered, not level-triggered. 2289 */ 2290 vmc->claim_edge_triggered_timers = true; 2291 } 2292 DEFINE_VIRT_MACHINE(2, 8) 2293 2294 static void virt_machine_2_7_options(MachineClass *mc) 2295 { 2296 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2297 2298 virt_machine_2_8_options(mc); 2299 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 2300 /* ITS was introduced with 2.8 */ 2301 vmc->no_its = true; 2302 /* Stick with 1K pages for migration compatibility */ 2303 mc->minimum_page_bits = 0; 2304 } 2305 DEFINE_VIRT_MACHINE(2, 7) 2306 2307 static void virt_machine_2_6_options(MachineClass *mc) 2308 { 2309 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2310 2311 virt_machine_2_7_options(mc); 2312 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 2313 vmc->disallow_affinity_adjustment = true; 2314 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2315 vmc->no_pmu = true; 2316 } 2317 DEFINE_VIRT_MACHINE(2, 6) 2318