1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/devices.h" 38 #include "net/net.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/numa.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/boards.h" 45 #include "hw/compat.h" 46 #include "hw/loader.h" 47 #include "exec/address-spaces.h" 48 #include "qemu/bitops.h" 49 #include "qemu/error-report.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/arm/virt-acpi-build.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic.h" 56 #include "hw/intc/arm_gicv3_common.h" 57 #include "kvm_arm.h" 58 #include "hw/smbios/smbios.h" 59 #include "qapi/visitor.h" 60 #include "standard-headers/linux/input.h" 61 62 /* Number of external interrupt lines to configure the GIC with */ 63 #define NUM_IRQS 256 64 65 #define PLATFORM_BUS_NUM_IRQS 64 66 67 static ARMPlatformBusSystemParams platform_bus_params; 68 69 typedef struct VirtBoardInfo { 70 struct arm_boot_info bootinfo; 71 const char *cpu_model; 72 const MemMapEntry *memmap; 73 const int *irqmap; 74 int smp_cpus; 75 void *fdt; 76 int fdt_size; 77 uint32_t clock_phandle; 78 uint32_t gic_phandle; 79 uint32_t msi_phandle; 80 bool using_psci; 81 } VirtBoardInfo; 82 83 typedef struct { 84 MachineClass parent; 85 VirtBoardInfo *daughterboard; 86 bool disallow_affinity_adjustment; 87 } VirtMachineClass; 88 89 typedef struct { 90 MachineState parent; 91 bool secure; 92 bool highmem; 93 int32_t gic_version; 94 } VirtMachineState; 95 96 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 97 #define VIRT_MACHINE(obj) \ 98 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) 99 #define VIRT_MACHINE_GET_CLASS(obj) \ 100 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE) 101 #define VIRT_MACHINE_CLASS(klass) \ 102 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE) 103 104 105 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 106 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 107 void *data) \ 108 { \ 109 MachineClass *mc = MACHINE_CLASS(oc); \ 110 virt_machine_##major##_##minor##_options(mc); \ 111 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 112 if (latest) { \ 113 mc->alias = "virt"; \ 114 } \ 115 } \ 116 static const TypeInfo machvirt_##major##_##minor##_info = { \ 117 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 118 .parent = TYPE_VIRT_MACHINE, \ 119 .instance_init = virt_##major##_##minor##_instance_init, \ 120 .class_init = virt_##major##_##minor##_class_init, \ 121 }; \ 122 static void machvirt_machine_##major##_##minor##_init(void) \ 123 { \ 124 type_register_static(&machvirt_##major##_##minor##_info); \ 125 } \ 126 type_init(machvirt_machine_##major##_##minor##_init); 127 128 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 129 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 130 #define DEFINE_VIRT_MACHINE(major, minor) \ 131 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 132 133 134 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 135 * RAM can go up to the 256GB mark, leaving 256GB of the physical 136 * address space unallocated and free for future use between 256G and 512G. 137 * If we need to provide more RAM to VMs in the future then we need to: 138 * * allocate a second bank of RAM starting at 2TB and working up 139 * * fix the DT and ACPI table generation code in QEMU to correctly 140 * report two split lumps of RAM to the guest 141 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 142 * (We don't want to fill all the way up to 512GB with RAM because 143 * we might want it for non-RAM purposes later. Conversely it seems 144 * reasonable to assume that anybody configuring a VM with a quarter 145 * of a terabyte of RAM will be doing it on a host with more than a 146 * terabyte of physical address space.) 147 */ 148 #define RAMLIMIT_GB 255 149 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 150 151 /* Addresses and sizes of our components. 152 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 153 * 128MB..256MB is used for miscellaneous device I/O. 154 * 256MB..1GB is reserved for possible future PCI support (ie where the 155 * PCI memory window will go if we add a PCI host controller). 156 * 1GB and up is RAM (which may happily spill over into the 157 * high memory region beyond 4GB). 158 * This represents a compromise between how much RAM can be given to 159 * a 32 bit VM and leaving space for expansion and in particular for PCI. 160 * Note that devices should generally be placed at multiples of 0x10000, 161 * to accommodate guests using 64K pages. 162 */ 163 static const MemMapEntry a15memmap[] = { 164 /* Space up to 0x8000000 is reserved for a boot ROM */ 165 [VIRT_FLASH] = { 0, 0x08000000 }, 166 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 167 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 168 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 169 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 170 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 171 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 172 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 173 /* This redistributor space allows up to 2*64kB*123 CPUs */ 174 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 175 [VIRT_UART] = { 0x09000000, 0x00001000 }, 176 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 177 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 178 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 179 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 180 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 181 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 182 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 183 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 184 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 185 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 186 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 187 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 188 /* Second PCIe window, 512GB wide at the 512GB boundary */ 189 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 190 }; 191 192 static const int a15irqmap[] = { 193 [VIRT_UART] = 1, 194 [VIRT_RTC] = 2, 195 [VIRT_PCIE] = 3, /* ... to 6 */ 196 [VIRT_GPIO] = 7, 197 [VIRT_SECURE_UART] = 8, 198 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 199 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 200 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 201 }; 202 203 static VirtBoardInfo machines[] = { 204 { 205 .cpu_model = "cortex-a15", 206 .memmap = a15memmap, 207 .irqmap = a15irqmap, 208 }, 209 { 210 .cpu_model = "cortex-a53", 211 .memmap = a15memmap, 212 .irqmap = a15irqmap, 213 }, 214 { 215 .cpu_model = "cortex-a57", 216 .memmap = a15memmap, 217 .irqmap = a15irqmap, 218 }, 219 { 220 .cpu_model = "host", 221 .memmap = a15memmap, 222 .irqmap = a15irqmap, 223 }, 224 }; 225 226 static VirtBoardInfo *find_machine_info(const char *cpu) 227 { 228 int i; 229 230 for (i = 0; i < ARRAY_SIZE(machines); i++) { 231 if (strcmp(cpu, machines[i].cpu_model) == 0) { 232 return &machines[i]; 233 } 234 } 235 return NULL; 236 } 237 238 static void create_fdt(VirtBoardInfo *vbi) 239 { 240 void *fdt = create_device_tree(&vbi->fdt_size); 241 242 if (!fdt) { 243 error_report("create_device_tree() failed"); 244 exit(1); 245 } 246 247 vbi->fdt = fdt; 248 249 /* Header */ 250 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 251 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 252 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 253 254 /* 255 * /chosen and /memory nodes must exist for load_dtb 256 * to fill in necessary properties later 257 */ 258 qemu_fdt_add_subnode(fdt, "/chosen"); 259 qemu_fdt_add_subnode(fdt, "/memory"); 260 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 261 262 /* Clock node, for the benefit of the UART. The kernel device tree 263 * binding documentation claims the PL011 node clock properties are 264 * optional but in practice if you omit them the kernel refuses to 265 * probe for the device. 266 */ 267 vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); 268 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 269 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 270 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 271 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 272 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 273 "clk24mhz"); 274 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); 275 276 } 277 278 static void fdt_add_psci_node(const VirtBoardInfo *vbi) 279 { 280 uint32_t cpu_suspend_fn; 281 uint32_t cpu_off_fn; 282 uint32_t cpu_on_fn; 283 uint32_t migrate_fn; 284 void *fdt = vbi->fdt; 285 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 286 287 if (!vbi->using_psci) { 288 return; 289 } 290 291 qemu_fdt_add_subnode(fdt, "/psci"); 292 if (armcpu->psci_version == 2) { 293 const char comp[] = "arm,psci-0.2\0arm,psci"; 294 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 295 296 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 297 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 298 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 299 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 300 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 301 } else { 302 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 303 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 304 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 305 } 306 } else { 307 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 308 309 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 310 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 311 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 312 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 313 } 314 315 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 316 * to the instruction that should be used to invoke PSCI functions. 317 * However, the device tree binding uses 'method' instead, so that is 318 * what we should use here. 319 */ 320 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); 321 322 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 323 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 324 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 325 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 326 } 327 328 static void fdt_add_timer_nodes(const VirtBoardInfo *vbi, int gictype) 329 { 330 /* Note that on A15 h/w these interrupts are level-triggered, 331 * but for the GIC implementation provided by both QEMU and KVM 332 * they are edge-triggered. 333 */ 334 ARMCPU *armcpu; 335 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 336 337 if (gictype == 2) { 338 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 339 GIC_FDT_IRQ_PPI_CPU_WIDTH, 340 (1 << vbi->smp_cpus) - 1); 341 } 342 343 qemu_fdt_add_subnode(vbi->fdt, "/timer"); 344 345 armcpu = ARM_CPU(qemu_get_cpu(0)); 346 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 347 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 348 qemu_fdt_setprop(vbi->fdt, "/timer", "compatible", 349 compat, sizeof(compat)); 350 } else { 351 qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible", 352 "arm,armv7-timer"); 353 } 354 qemu_fdt_setprop(vbi->fdt, "/timer", "always-on", NULL, 0); 355 qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", 356 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 357 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 358 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 359 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 360 } 361 362 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) 363 { 364 int cpu; 365 int addr_cells = 1; 366 unsigned int i; 367 368 /* 369 * From Documentation/devicetree/bindings/arm/cpus.txt 370 * On ARM v8 64-bit systems value should be set to 2, 371 * that corresponds to the MPIDR_EL1 register size. 372 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 373 * in the system, #address-cells can be set to 1, since 374 * MPIDR_EL1[63:32] bits are not used for CPUs 375 * identification. 376 * 377 * Here we actually don't know whether our system is 32- or 64-bit one. 378 * The simplest way to go is to examine affinity IDs of all our CPUs. If 379 * at least one of them has Aff3 populated, we set #address-cells to 2. 380 */ 381 for (cpu = 0; cpu < vbi->smp_cpus; cpu++) { 382 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 383 384 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 385 addr_cells = 2; 386 break; 387 } 388 } 389 390 qemu_fdt_add_subnode(vbi->fdt, "/cpus"); 391 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells); 392 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); 393 394 for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { 395 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 396 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 397 398 qemu_fdt_add_subnode(vbi->fdt, nodename); 399 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); 400 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", 401 armcpu->dtb_compatible); 402 403 if (vbi->using_psci && vbi->smp_cpus > 1) { 404 qemu_fdt_setprop_string(vbi->fdt, nodename, 405 "enable-method", "psci"); 406 } 407 408 if (addr_cells == 2) { 409 qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg", 410 armcpu->mp_affinity); 411 } else { 412 qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", 413 armcpu->mp_affinity); 414 } 415 416 i = numa_get_node_for_cpu(cpu); 417 if (i < nb_numa_nodes) { 418 qemu_fdt_setprop_cell(vbi->fdt, nodename, "numa-node-id", i); 419 } 420 421 g_free(nodename); 422 } 423 } 424 425 static void fdt_add_its_gic_node(VirtBoardInfo *vbi) 426 { 427 vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 428 qemu_fdt_add_subnode(vbi->fdt, "/intc/its"); 429 qemu_fdt_setprop_string(vbi->fdt, "/intc/its", "compatible", 430 "arm,gic-v3-its"); 431 qemu_fdt_setprop(vbi->fdt, "/intc/its", "msi-controller", NULL, 0); 432 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/its", "reg", 433 2, vbi->memmap[VIRT_GIC_ITS].base, 434 2, vbi->memmap[VIRT_GIC_ITS].size); 435 qemu_fdt_setprop_cell(vbi->fdt, "/intc/its", "phandle", vbi->msi_phandle); 436 } 437 438 static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi) 439 { 440 vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 441 qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m"); 442 qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible", 443 "arm,gic-v2m-frame"); 444 qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0); 445 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg", 446 2, vbi->memmap[VIRT_GIC_V2M].base, 447 2, vbi->memmap[VIRT_GIC_V2M].size); 448 qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->msi_phandle); 449 } 450 451 static void fdt_add_gic_node(VirtBoardInfo *vbi, int type) 452 { 453 vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 454 qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle); 455 456 qemu_fdt_add_subnode(vbi->fdt, "/intc"); 457 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); 458 qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); 459 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); 460 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); 461 qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); 462 if (type == 3) { 463 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 464 "arm,gic-v3"); 465 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 466 2, vbi->memmap[VIRT_GIC_DIST].base, 467 2, vbi->memmap[VIRT_GIC_DIST].size, 468 2, vbi->memmap[VIRT_GIC_REDIST].base, 469 2, vbi->memmap[VIRT_GIC_REDIST].size); 470 } else { 471 /* 'cortex-a15-gic' means 'GIC v2' */ 472 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 473 "arm,cortex-a15-gic"); 474 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 475 2, vbi->memmap[VIRT_GIC_DIST].base, 476 2, vbi->memmap[VIRT_GIC_DIST].size, 477 2, vbi->memmap[VIRT_GIC_CPU].base, 478 2, vbi->memmap[VIRT_GIC_CPU].size); 479 } 480 481 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); 482 } 483 484 static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype) 485 { 486 CPUState *cpu; 487 ARMCPU *armcpu; 488 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 489 490 CPU_FOREACH(cpu) { 491 armcpu = ARM_CPU(cpu); 492 if (!armcpu->has_pmu || 493 !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { 494 return; 495 } 496 } 497 498 if (gictype == 2) { 499 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 500 GIC_FDT_IRQ_PPI_CPU_WIDTH, 501 (1 << vbi->smp_cpus) - 1); 502 } 503 504 armcpu = ARM_CPU(qemu_get_cpu(0)); 505 qemu_fdt_add_subnode(vbi->fdt, "/pmu"); 506 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 507 const char compat[] = "arm,armv8-pmuv3"; 508 qemu_fdt_setprop(vbi->fdt, "/pmu", "compatible", 509 compat, sizeof(compat)); 510 qemu_fdt_setprop_cells(vbi->fdt, "/pmu", "interrupts", 511 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 512 } 513 } 514 515 static void create_its(VirtBoardInfo *vbi, DeviceState *gicdev) 516 { 517 const char *itsclass = its_class_name(); 518 DeviceState *dev; 519 520 if (!itsclass) { 521 /* Do nothing if not supported */ 522 return; 523 } 524 525 dev = qdev_create(NULL, itsclass); 526 527 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 528 &error_abort); 529 qdev_init_nofail(dev); 530 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_ITS].base); 531 532 fdt_add_its_gic_node(vbi); 533 } 534 535 static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic) 536 { 537 int i; 538 int irq = vbi->irqmap[VIRT_GIC_V2M]; 539 DeviceState *dev; 540 541 dev = qdev_create(NULL, "arm-gicv2m"); 542 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base); 543 qdev_prop_set_uint32(dev, "base-spi", irq); 544 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 545 qdev_init_nofail(dev); 546 547 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 548 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 549 } 550 551 fdt_add_v2m_gic_node(vbi); 552 } 553 554 static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, bool secure) 555 { 556 /* We create a standalone GIC */ 557 DeviceState *gicdev; 558 SysBusDevice *gicbusdev; 559 const char *gictype; 560 int i; 561 562 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 563 564 gicdev = qdev_create(NULL, gictype); 565 qdev_prop_set_uint32(gicdev, "revision", type); 566 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 567 /* Note that the num-irq property counts both internal and external 568 * interrupts; there are always 32 of the former (mandated by GIC spec). 569 */ 570 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 571 if (!kvm_irqchip_in_kernel()) { 572 qdev_prop_set_bit(gicdev, "has-security-extensions", secure); 573 } 574 qdev_init_nofail(gicdev); 575 gicbusdev = SYS_BUS_DEVICE(gicdev); 576 sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); 577 if (type == 3) { 578 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base); 579 } else { 580 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); 581 } 582 583 /* Wire the outputs from each CPU's generic timer to the 584 * appropriate GIC PPI inputs, and the GIC's IRQ output to 585 * the CPU's IRQ input. 586 */ 587 for (i = 0; i < smp_cpus; i++) { 588 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 589 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 590 int irq; 591 /* Mapping from the output timer irq lines from the CPU to the 592 * GIC PPI inputs we use for the virt board. 593 */ 594 const int timer_irq[] = { 595 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 596 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 597 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 598 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 599 }; 600 601 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 602 qdev_connect_gpio_out(cpudev, irq, 603 qdev_get_gpio_in(gicdev, 604 ppibase + timer_irq[irq])); 605 } 606 607 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 608 sysbus_connect_irq(gicbusdev, i + smp_cpus, 609 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 610 } 611 612 for (i = 0; i < NUM_IRQS; i++) { 613 pic[i] = qdev_get_gpio_in(gicdev, i); 614 } 615 616 fdt_add_gic_node(vbi, type); 617 618 if (type == 3) { 619 create_its(vbi, gicdev); 620 } else { 621 create_v2m(vbi, pic); 622 } 623 } 624 625 static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic, int uart, 626 MemoryRegion *mem, CharDriverState *chr) 627 { 628 char *nodename; 629 hwaddr base = vbi->memmap[uart].base; 630 hwaddr size = vbi->memmap[uart].size; 631 int irq = vbi->irqmap[uart]; 632 const char compat[] = "arm,pl011\0arm,primecell"; 633 const char clocknames[] = "uartclk\0apb_pclk"; 634 DeviceState *dev = qdev_create(NULL, "pl011"); 635 SysBusDevice *s = SYS_BUS_DEVICE(dev); 636 637 qdev_prop_set_chr(dev, "chardev", chr); 638 qdev_init_nofail(dev); 639 memory_region_add_subregion(mem, base, 640 sysbus_mmio_get_region(s, 0)); 641 sysbus_connect_irq(s, 0, pic[irq]); 642 643 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 644 qemu_fdt_add_subnode(vbi->fdt, nodename); 645 /* Note that we can't use setprop_string because of the embedded NUL */ 646 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", 647 compat, sizeof(compat)); 648 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 649 2, base, 2, size); 650 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 651 GIC_FDT_IRQ_TYPE_SPI, irq, 652 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 653 qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", 654 vbi->clock_phandle, vbi->clock_phandle); 655 qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", 656 clocknames, sizeof(clocknames)); 657 658 if (uart == VIRT_UART) { 659 qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename); 660 } else { 661 /* Mark as not usable by the normal world */ 662 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 663 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 664 } 665 666 g_free(nodename); 667 } 668 669 static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic) 670 { 671 char *nodename; 672 hwaddr base = vbi->memmap[VIRT_RTC].base; 673 hwaddr size = vbi->memmap[VIRT_RTC].size; 674 int irq = vbi->irqmap[VIRT_RTC]; 675 const char compat[] = "arm,pl031\0arm,primecell"; 676 677 sysbus_create_simple("pl031", base, pic[irq]); 678 679 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 680 qemu_fdt_add_subnode(vbi->fdt, nodename); 681 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 682 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 683 2, base, 2, size); 684 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 685 GIC_FDT_IRQ_TYPE_SPI, irq, 686 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 687 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 688 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 689 g_free(nodename); 690 } 691 692 static DeviceState *gpio_key_dev; 693 static void virt_powerdown_req(Notifier *n, void *opaque) 694 { 695 /* use gpio Pin 3 for power button event */ 696 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 697 } 698 699 static Notifier virt_system_powerdown_notifier = { 700 .notify = virt_powerdown_req 701 }; 702 703 static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic) 704 { 705 char *nodename; 706 DeviceState *pl061_dev; 707 hwaddr base = vbi->memmap[VIRT_GPIO].base; 708 hwaddr size = vbi->memmap[VIRT_GPIO].size; 709 int irq = vbi->irqmap[VIRT_GPIO]; 710 const char compat[] = "arm,pl061\0arm,primecell"; 711 712 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 713 714 uint32_t phandle = qemu_fdt_alloc_phandle(vbi->fdt); 715 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 716 qemu_fdt_add_subnode(vbi->fdt, nodename); 717 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 718 2, base, 2, size); 719 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 720 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#gpio-cells", 2); 721 qemu_fdt_setprop(vbi->fdt, nodename, "gpio-controller", NULL, 0); 722 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 723 GIC_FDT_IRQ_TYPE_SPI, irq, 724 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 725 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 726 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 727 qemu_fdt_setprop_cell(vbi->fdt, nodename, "phandle", phandle); 728 729 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 730 qdev_get_gpio_in(pl061_dev, 3)); 731 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys"); 732 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys", "compatible", "gpio-keys"); 733 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#size-cells", 0); 734 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#address-cells", 1); 735 736 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys/poweroff"); 737 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys/poweroff", 738 "label", "GPIO Key Poweroff"); 739 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys/poweroff", "linux,code", 740 KEY_POWER); 741 qemu_fdt_setprop_cells(vbi->fdt, "/gpio-keys/poweroff", 742 "gpios", phandle, 3, 0); 743 744 /* connect powerdown request */ 745 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 746 747 g_free(nodename); 748 } 749 750 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic) 751 { 752 int i; 753 hwaddr size = vbi->memmap[VIRT_MMIO].size; 754 755 /* We create the transports in forwards order. Since qbus_realize() 756 * prepends (not appends) new child buses, the incrementing loop below will 757 * create a list of virtio-mmio buses with decreasing base addresses. 758 * 759 * When a -device option is processed from the command line, 760 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 761 * order. The upshot is that -device options in increasing command line 762 * order are mapped to virtio-mmio buses with decreasing base addresses. 763 * 764 * When this code was originally written, that arrangement ensured that the 765 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 766 * the first -device on the command line. (The end-to-end order is a 767 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 768 * guest kernel's name-to-address assignment strategy.) 769 * 770 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 771 * the message, if not necessarily the code, of commit 70161ff336. 772 * Therefore the loop now establishes the inverse of the original intent. 773 * 774 * Unfortunately, we can't counteract the kernel change by reversing the 775 * loop; it would break existing command lines. 776 * 777 * In any case, the kernel makes no guarantee about the stability of 778 * enumeration order of virtio devices (as demonstrated by it changing 779 * between kernel versions). For reliable and stable identification 780 * of disks users must use UUIDs or similar mechanisms. 781 */ 782 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 783 int irq = vbi->irqmap[VIRT_MMIO] + i; 784 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 785 786 sysbus_create_simple("virtio-mmio", base, pic[irq]); 787 } 788 789 /* We add dtb nodes in reverse order so that they appear in the finished 790 * device tree lowest address first. 791 * 792 * Note that this mapping is independent of the loop above. The previous 793 * loop influences virtio device to virtio transport assignment, whereas 794 * this loop controls how virtio transports are laid out in the dtb. 795 */ 796 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 797 char *nodename; 798 int irq = vbi->irqmap[VIRT_MMIO] + i; 799 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 800 801 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 802 qemu_fdt_add_subnode(vbi->fdt, nodename); 803 qemu_fdt_setprop_string(vbi->fdt, nodename, 804 "compatible", "virtio,mmio"); 805 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 806 2, base, 2, size); 807 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 808 GIC_FDT_IRQ_TYPE_SPI, irq, 809 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 810 g_free(nodename); 811 } 812 } 813 814 static void create_one_flash(const char *name, hwaddr flashbase, 815 hwaddr flashsize, const char *file, 816 MemoryRegion *sysmem) 817 { 818 /* Create and map a single flash device. We use the same 819 * parameters as the flash devices on the Versatile Express board. 820 */ 821 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 822 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 823 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 824 const uint64_t sectorlength = 256 * 1024; 825 826 if (dinfo) { 827 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 828 &error_abort); 829 } 830 831 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 832 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 833 qdev_prop_set_uint8(dev, "width", 4); 834 qdev_prop_set_uint8(dev, "device-width", 2); 835 qdev_prop_set_bit(dev, "big-endian", false); 836 qdev_prop_set_uint16(dev, "id0", 0x89); 837 qdev_prop_set_uint16(dev, "id1", 0x18); 838 qdev_prop_set_uint16(dev, "id2", 0x00); 839 qdev_prop_set_uint16(dev, "id3", 0x00); 840 qdev_prop_set_string(dev, "name", name); 841 qdev_init_nofail(dev); 842 843 memory_region_add_subregion(sysmem, flashbase, 844 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 845 846 if (file) { 847 char *fn; 848 int image_size; 849 850 if (drive_get(IF_PFLASH, 0, 0)) { 851 error_report("The contents of the first flash device may be " 852 "specified with -bios or with -drive if=pflash... " 853 "but you cannot use both options at once"); 854 exit(1); 855 } 856 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 857 if (!fn) { 858 error_report("Could not find ROM image '%s'", file); 859 exit(1); 860 } 861 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 862 g_free(fn); 863 if (image_size < 0) { 864 error_report("Could not load ROM image '%s'", file); 865 exit(1); 866 } 867 } 868 } 869 870 static void create_flash(const VirtBoardInfo *vbi, 871 MemoryRegion *sysmem, 872 MemoryRegion *secure_sysmem) 873 { 874 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 875 * Any file passed via -bios goes in the first of these. 876 * sysmem is the system memory space. secure_sysmem is the secure view 877 * of the system, and the first flash device should be made visible only 878 * there. The second flash device is visible to both secure and nonsecure. 879 * If sysmem == secure_sysmem this means there is no separate Secure 880 * address space and both flash devices are generally visible. 881 */ 882 hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2; 883 hwaddr flashbase = vbi->memmap[VIRT_FLASH].base; 884 char *nodename; 885 886 create_one_flash("virt.flash0", flashbase, flashsize, 887 bios_name, secure_sysmem); 888 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 889 NULL, sysmem); 890 891 if (sysmem == secure_sysmem) { 892 /* Report both flash devices as a single node in the DT */ 893 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 894 qemu_fdt_add_subnode(vbi->fdt, nodename); 895 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 896 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 897 2, flashbase, 2, flashsize, 898 2, flashbase + flashsize, 2, flashsize); 899 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 900 g_free(nodename); 901 } else { 902 /* Report the devices as separate nodes so we can mark one as 903 * only visible to the secure world. 904 */ 905 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 906 qemu_fdt_add_subnode(vbi->fdt, nodename); 907 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 908 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 909 2, flashbase, 2, flashsize); 910 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 911 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 912 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 913 g_free(nodename); 914 915 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 916 qemu_fdt_add_subnode(vbi->fdt, nodename); 917 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 918 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 919 2, flashbase + flashsize, 2, flashsize); 920 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 921 g_free(nodename); 922 } 923 } 924 925 static void create_fw_cfg(const VirtBoardInfo *vbi, AddressSpace *as) 926 { 927 hwaddr base = vbi->memmap[VIRT_FW_CFG].base; 928 hwaddr size = vbi->memmap[VIRT_FW_CFG].size; 929 char *nodename; 930 931 fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 932 933 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 934 qemu_fdt_add_subnode(vbi->fdt, nodename); 935 qemu_fdt_setprop_string(vbi->fdt, nodename, 936 "compatible", "qemu,fw-cfg-mmio"); 937 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 938 2, base, 2, size); 939 g_free(nodename); 940 } 941 942 static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, 943 int first_irq, const char *nodename) 944 { 945 int devfn, pin; 946 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 947 uint32_t *irq_map = full_irq_map; 948 949 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 950 for (pin = 0; pin < 4; pin++) { 951 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 952 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 953 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 954 int i; 955 956 uint32_t map[] = { 957 devfn << 8, 0, 0, /* devfn */ 958 pin + 1, /* PCI pin */ 959 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 960 961 /* Convert map to big endian */ 962 for (i = 0; i < 10; i++) { 963 irq_map[i] = cpu_to_be32(map[i]); 964 } 965 irq_map += 10; 966 } 967 } 968 969 qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map", 970 full_irq_map, sizeof(full_irq_map)); 971 972 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask", 973 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 974 0x7 /* PCI irq */); 975 } 976 977 static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic, 978 bool use_highmem) 979 { 980 hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base; 981 hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size; 982 hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base; 983 hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size; 984 hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base; 985 hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size; 986 hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base; 987 hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size; 988 hwaddr base = base_mmio; 989 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 990 int irq = vbi->irqmap[VIRT_PCIE]; 991 MemoryRegion *mmio_alias; 992 MemoryRegion *mmio_reg; 993 MemoryRegion *ecam_alias; 994 MemoryRegion *ecam_reg; 995 DeviceState *dev; 996 char *nodename; 997 int i; 998 PCIHostState *pci; 999 1000 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1001 qdev_init_nofail(dev); 1002 1003 /* Map only the first size_ecam bytes of ECAM space */ 1004 ecam_alias = g_new0(MemoryRegion, 1); 1005 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1006 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1007 ecam_reg, 0, size_ecam); 1008 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1009 1010 /* Map the MMIO window into system address space so as to expose 1011 * the section of PCI MMIO space which starts at the same base address 1012 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1013 * the window). 1014 */ 1015 mmio_alias = g_new0(MemoryRegion, 1); 1016 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1017 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1018 mmio_reg, base_mmio, size_mmio); 1019 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1020 1021 if (use_highmem) { 1022 /* Map high MMIO space */ 1023 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1024 1025 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1026 mmio_reg, base_mmio_high, size_mmio_high); 1027 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1028 high_mmio_alias); 1029 } 1030 1031 /* Map IO port space */ 1032 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1033 1034 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1035 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1036 } 1037 1038 pci = PCI_HOST_BRIDGE(dev); 1039 if (pci->bus) { 1040 for (i = 0; i < nb_nics; i++) { 1041 NICInfo *nd = &nd_table[i]; 1042 1043 if (!nd->model) { 1044 nd->model = g_strdup("virtio"); 1045 } 1046 1047 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1048 } 1049 } 1050 1051 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1052 qemu_fdt_add_subnode(vbi->fdt, nodename); 1053 qemu_fdt_setprop_string(vbi->fdt, nodename, 1054 "compatible", "pci-host-ecam-generic"); 1055 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci"); 1056 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3); 1057 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2); 1058 qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, 1059 nr_pcie_buses - 1); 1060 qemu_fdt_setprop(vbi->fdt, nodename, "dma-coherent", NULL, 0); 1061 1062 if (vbi->msi_phandle) { 1063 qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", 1064 vbi->msi_phandle); 1065 } 1066 1067 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 1068 2, base_ecam, 2, size_ecam); 1069 1070 if (use_highmem) { 1071 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", 1072 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1073 2, base_pio, 2, size_pio, 1074 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1075 2, base_mmio, 2, size_mmio, 1076 1, FDT_PCI_RANGE_MMIO_64BIT, 1077 2, base_mmio_high, 1078 2, base_mmio_high, 2, size_mmio_high); 1079 } else { 1080 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", 1081 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1082 2, base_pio, 2, size_pio, 1083 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1084 2, base_mmio, 2, size_mmio); 1085 } 1086 1087 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1); 1088 create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename); 1089 1090 g_free(nodename); 1091 } 1092 1093 static void create_platform_bus(VirtBoardInfo *vbi, qemu_irq *pic) 1094 { 1095 DeviceState *dev; 1096 SysBusDevice *s; 1097 int i; 1098 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1099 MemoryRegion *sysmem = get_system_memory(); 1100 1101 platform_bus_params.platform_bus_base = vbi->memmap[VIRT_PLATFORM_BUS].base; 1102 platform_bus_params.platform_bus_size = vbi->memmap[VIRT_PLATFORM_BUS].size; 1103 platform_bus_params.platform_bus_first_irq = vbi->irqmap[VIRT_PLATFORM_BUS]; 1104 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1105 1106 fdt_params->system_params = &platform_bus_params; 1107 fdt_params->binfo = &vbi->bootinfo; 1108 fdt_params->intc = "/intc"; 1109 /* 1110 * register a machine init done notifier that creates the device tree 1111 * nodes of the platform bus and its children dynamic sysbus devices 1112 */ 1113 arm_register_platform_bus_fdt_creator(fdt_params); 1114 1115 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1116 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1117 qdev_prop_set_uint32(dev, "num_irqs", 1118 platform_bus_params.platform_bus_num_irqs); 1119 qdev_prop_set_uint32(dev, "mmio_size", 1120 platform_bus_params.platform_bus_size); 1121 qdev_init_nofail(dev); 1122 s = SYS_BUS_DEVICE(dev); 1123 1124 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1125 int irqn = platform_bus_params.platform_bus_first_irq + i; 1126 sysbus_connect_irq(s, i, pic[irqn]); 1127 } 1128 1129 memory_region_add_subregion(sysmem, 1130 platform_bus_params.platform_bus_base, 1131 sysbus_mmio_get_region(s, 0)); 1132 } 1133 1134 static void create_secure_ram(VirtBoardInfo *vbi, MemoryRegion *secure_sysmem) 1135 { 1136 MemoryRegion *secram = g_new(MemoryRegion, 1); 1137 char *nodename; 1138 hwaddr base = vbi->memmap[VIRT_SECURE_MEM].base; 1139 hwaddr size = vbi->memmap[VIRT_SECURE_MEM].size; 1140 1141 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); 1142 vmstate_register_ram_global(secram); 1143 memory_region_add_subregion(secure_sysmem, base, secram); 1144 1145 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1146 qemu_fdt_add_subnode(vbi->fdt, nodename); 1147 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "memory"); 1148 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base, 2, size); 1149 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 1150 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 1151 1152 g_free(nodename); 1153 } 1154 1155 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1156 { 1157 const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; 1158 1159 *fdt_size = board->fdt_size; 1160 return board->fdt; 1161 } 1162 1163 static void virt_build_smbios(VirtGuestInfo *guest_info) 1164 { 1165 FWCfgState *fw_cfg = guest_info->fw_cfg; 1166 uint8_t *smbios_tables, *smbios_anchor; 1167 size_t smbios_tables_len, smbios_anchor_len; 1168 const char *product = "QEMU Virtual Machine"; 1169 1170 if (!fw_cfg) { 1171 return; 1172 } 1173 1174 if (kvm_enabled()) { 1175 product = "KVM Virtual Machine"; 1176 } 1177 1178 smbios_set_defaults("QEMU", product, 1179 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1180 1181 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1182 &smbios_anchor, &smbios_anchor_len); 1183 1184 if (smbios_anchor) { 1185 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 1186 smbios_tables, smbios_tables_len); 1187 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 1188 smbios_anchor, smbios_anchor_len); 1189 } 1190 } 1191 1192 static 1193 void virt_guest_info_machine_done(Notifier *notifier, void *data) 1194 { 1195 VirtGuestInfoState *guest_info_state = container_of(notifier, 1196 VirtGuestInfoState, machine_done); 1197 virt_acpi_setup(&guest_info_state->info); 1198 virt_build_smbios(&guest_info_state->info); 1199 } 1200 1201 static void machvirt_init(MachineState *machine) 1202 { 1203 VirtMachineState *vms = VIRT_MACHINE(machine); 1204 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1205 qemu_irq pic[NUM_IRQS]; 1206 MemoryRegion *sysmem = get_system_memory(); 1207 MemoryRegion *secure_sysmem = NULL; 1208 int gic_version = vms->gic_version; 1209 int n, virt_max_cpus; 1210 MemoryRegion *ram = g_new(MemoryRegion, 1); 1211 const char *cpu_model = machine->cpu_model; 1212 VirtBoardInfo *vbi; 1213 VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1214 VirtGuestInfo *guest_info = &guest_info_state->info; 1215 char **cpustr; 1216 ObjectClass *oc; 1217 const char *typename; 1218 CPUClass *cc; 1219 Error *err = NULL; 1220 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1221 uint8_t clustersz; 1222 1223 if (!cpu_model) { 1224 cpu_model = "cortex-a15"; 1225 } 1226 1227 /* We can probe only here because during property set 1228 * KVM is not available yet 1229 */ 1230 if (!gic_version) { 1231 if (!kvm_enabled()) { 1232 error_report("gic-version=host requires KVM"); 1233 exit(1); 1234 } 1235 1236 gic_version = kvm_arm_vgic_probe(); 1237 if (!gic_version) { 1238 error_report("Unable to determine GIC version supported by host"); 1239 exit(1); 1240 } 1241 } 1242 1243 /* Separate the actual CPU model name from any appended features */ 1244 cpustr = g_strsplit(cpu_model, ",", 2); 1245 1246 vbi = find_machine_info(cpustr[0]); 1247 1248 if (!vbi) { 1249 error_report("mach-virt: CPU %s not supported", cpustr[0]); 1250 exit(1); 1251 } 1252 1253 /* If we have an EL3 boot ROM then the assumption is that it will 1254 * implement PSCI itself, so disable QEMU's internal implementation 1255 * so it doesn't get in the way. Instead of starting secondary 1256 * CPUs in PSCI powerdown state we will start them all running and 1257 * let the boot ROM sort them out. 1258 * The usual case is that we do use QEMU's PSCI implementation. 1259 */ 1260 vbi->using_psci = !(vms->secure && firmware_loaded); 1261 1262 /* The maximum number of CPUs depends on the GIC version, or on how 1263 * many redistributors we can fit into the memory map. 1264 */ 1265 if (gic_version == 3) { 1266 virt_max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000; 1267 clustersz = GICV3_TARGETLIST_BITS; 1268 } else { 1269 virt_max_cpus = GIC_NCPU; 1270 clustersz = GIC_TARGETLIST_BITS; 1271 } 1272 1273 if (max_cpus > virt_max_cpus) { 1274 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1275 "supported by machine 'mach-virt' (%d)", 1276 max_cpus, virt_max_cpus); 1277 exit(1); 1278 } 1279 1280 vbi->smp_cpus = smp_cpus; 1281 1282 if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { 1283 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1284 exit(1); 1285 } 1286 1287 if (vms->secure) { 1288 if (kvm_enabled()) { 1289 error_report("mach-virt: KVM does not support Security extensions"); 1290 exit(1); 1291 } 1292 1293 /* The Secure view of the world is the same as the NonSecure, 1294 * but with a few extra devices. Create it as a container region 1295 * containing the system memory at low priority; any secure-only 1296 * devices go in at higher priority and take precedence. 1297 */ 1298 secure_sysmem = g_new(MemoryRegion, 1); 1299 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1300 UINT64_MAX); 1301 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1302 } 1303 1304 create_fdt(vbi); 1305 1306 oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 1307 if (!oc) { 1308 error_report("Unable to find CPU definition"); 1309 exit(1); 1310 } 1311 typename = object_class_get_name(oc); 1312 1313 /* convert -smp CPU options specified by the user into global props */ 1314 cc = CPU_CLASS(oc); 1315 cc->parse_features(typename, cpustr[1], &err); 1316 g_strfreev(cpustr); 1317 if (err) { 1318 error_report_err(err); 1319 exit(1); 1320 } 1321 1322 for (n = 0; n < smp_cpus; n++) { 1323 Object *cpuobj = object_new(typename); 1324 if (!vmc->disallow_affinity_adjustment) { 1325 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1326 * GIC's target-list limitations. 32-bit KVM hosts currently 1327 * always create clusters of 4 CPUs, but that is expected to 1328 * change when they gain support for gicv3. When KVM is enabled 1329 * it will override the changes we make here, therefore our 1330 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1331 * and to improve SGI efficiency. 1332 */ 1333 uint8_t aff1 = n / clustersz; 1334 uint8_t aff0 = n % clustersz; 1335 object_property_set_int(cpuobj, (aff1 << ARM_AFF1_SHIFT) | aff0, 1336 "mp-affinity", NULL); 1337 } 1338 1339 if (!vms->secure) { 1340 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1341 } 1342 1343 if (vbi->using_psci) { 1344 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, 1345 "psci-conduit", NULL); 1346 1347 /* Secondary CPUs start in PSCI powered-down state */ 1348 if (n > 0) { 1349 object_property_set_bool(cpuobj, true, 1350 "start-powered-off", NULL); 1351 } 1352 } 1353 1354 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1355 object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, 1356 "reset-cbar", &error_abort); 1357 } 1358 1359 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1360 &error_abort); 1361 if (vms->secure) { 1362 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1363 "secure-memory", &error_abort); 1364 } 1365 1366 object_property_set_bool(cpuobj, true, "realized", NULL); 1367 } 1368 fdt_add_timer_nodes(vbi, gic_version); 1369 fdt_add_cpu_nodes(vbi); 1370 fdt_add_psci_node(vbi); 1371 1372 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1373 machine->ram_size); 1374 memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); 1375 1376 create_flash(vbi, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1377 1378 create_gic(vbi, pic, gic_version, vms->secure); 1379 1380 fdt_add_pmu_nodes(vbi, gic_version); 1381 1382 create_uart(vbi, pic, VIRT_UART, sysmem, serial_hds[0]); 1383 1384 if (vms->secure) { 1385 create_secure_ram(vbi, secure_sysmem); 1386 create_uart(vbi, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1387 } 1388 1389 create_rtc(vbi, pic); 1390 1391 create_pcie(vbi, pic, vms->highmem); 1392 1393 create_gpio(vbi, pic); 1394 1395 /* Create mmio transports, so the user can create virtio backends 1396 * (which will be automatically plugged in to the transports). If 1397 * no backend is created the transport will just sit harmlessly idle. 1398 */ 1399 create_virtio_devices(vbi, pic); 1400 1401 create_fw_cfg(vbi, &address_space_memory); 1402 rom_set_fw(fw_cfg_find()); 1403 1404 guest_info->smp_cpus = smp_cpus; 1405 guest_info->fw_cfg = fw_cfg_find(); 1406 guest_info->memmap = vbi->memmap; 1407 guest_info->irqmap = vbi->irqmap; 1408 guest_info->use_highmem = vms->highmem; 1409 guest_info->gic_version = gic_version; 1410 guest_info_state->machine_done.notify = virt_guest_info_machine_done; 1411 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1412 1413 vbi->bootinfo.ram_size = machine->ram_size; 1414 vbi->bootinfo.kernel_filename = machine->kernel_filename; 1415 vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1416 vbi->bootinfo.initrd_filename = machine->initrd_filename; 1417 vbi->bootinfo.nb_cpus = smp_cpus; 1418 vbi->bootinfo.board_id = -1; 1419 vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; 1420 vbi->bootinfo.get_dtb = machvirt_dtb; 1421 vbi->bootinfo.firmware_loaded = firmware_loaded; 1422 arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); 1423 1424 /* 1425 * arm_load_kernel machine init done notifier registration must 1426 * happen before the platform_bus_create call. In this latter, 1427 * another notifier is registered which adds platform bus nodes. 1428 * Notifiers are executed in registration reverse order. 1429 */ 1430 create_platform_bus(vbi, pic); 1431 } 1432 1433 static bool virt_get_secure(Object *obj, Error **errp) 1434 { 1435 VirtMachineState *vms = VIRT_MACHINE(obj); 1436 1437 return vms->secure; 1438 } 1439 1440 static void virt_set_secure(Object *obj, bool value, Error **errp) 1441 { 1442 VirtMachineState *vms = VIRT_MACHINE(obj); 1443 1444 vms->secure = value; 1445 } 1446 1447 static bool virt_get_highmem(Object *obj, Error **errp) 1448 { 1449 VirtMachineState *vms = VIRT_MACHINE(obj); 1450 1451 return vms->highmem; 1452 } 1453 1454 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1455 { 1456 VirtMachineState *vms = VIRT_MACHINE(obj); 1457 1458 vms->highmem = value; 1459 } 1460 1461 static char *virt_get_gic_version(Object *obj, Error **errp) 1462 { 1463 VirtMachineState *vms = VIRT_MACHINE(obj); 1464 const char *val = vms->gic_version == 3 ? "3" : "2"; 1465 1466 return g_strdup(val); 1467 } 1468 1469 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1470 { 1471 VirtMachineState *vms = VIRT_MACHINE(obj); 1472 1473 if (!strcmp(value, "3")) { 1474 vms->gic_version = 3; 1475 } else if (!strcmp(value, "2")) { 1476 vms->gic_version = 2; 1477 } else if (!strcmp(value, "host")) { 1478 vms->gic_version = 0; /* Will probe later */ 1479 } else { 1480 error_setg(errp, "Invalid gic-version value"); 1481 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1482 } 1483 } 1484 1485 static void virt_machine_class_init(ObjectClass *oc, void *data) 1486 { 1487 MachineClass *mc = MACHINE_CLASS(oc); 1488 1489 mc->init = machvirt_init; 1490 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1491 * it later in machvirt_init, where we have more information about the 1492 * configuration of the particular instance. 1493 */ 1494 mc->max_cpus = MAX_CPUMASK_BITS; 1495 mc->has_dynamic_sysbus = true; 1496 mc->block_default_type = IF_VIRTIO; 1497 mc->no_cdrom = 1; 1498 mc->pci_allow_0_address = true; 1499 } 1500 1501 static const TypeInfo virt_machine_info = { 1502 .name = TYPE_VIRT_MACHINE, 1503 .parent = TYPE_MACHINE, 1504 .abstract = true, 1505 .instance_size = sizeof(VirtMachineState), 1506 .class_size = sizeof(VirtMachineClass), 1507 .class_init = virt_machine_class_init, 1508 }; 1509 1510 static void machvirt_machine_init(void) 1511 { 1512 type_register_static(&virt_machine_info); 1513 } 1514 type_init(machvirt_machine_init); 1515 1516 static void virt_2_8_instance_init(Object *obj) 1517 { 1518 VirtMachineState *vms = VIRT_MACHINE(obj); 1519 1520 /* EL3 is disabled by default on virt: this makes us consistent 1521 * between KVM and TCG for this board, and it also allows us to 1522 * boot UEFI blobs which assume no TrustZone support. 1523 */ 1524 vms->secure = false; 1525 object_property_add_bool(obj, "secure", virt_get_secure, 1526 virt_set_secure, NULL); 1527 object_property_set_description(obj, "secure", 1528 "Set on/off to enable/disable the ARM " 1529 "Security Extensions (TrustZone)", 1530 NULL); 1531 1532 /* High memory is enabled by default */ 1533 vms->highmem = true; 1534 object_property_add_bool(obj, "highmem", virt_get_highmem, 1535 virt_set_highmem, NULL); 1536 object_property_set_description(obj, "highmem", 1537 "Set on/off to enable/disable using " 1538 "physical address space above 32 bits", 1539 NULL); 1540 /* Default GIC type is v2 */ 1541 vms->gic_version = 2; 1542 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1543 virt_set_gic_version, NULL); 1544 object_property_set_description(obj, "gic-version", 1545 "Set GIC version. " 1546 "Valid values are 2, 3 and host", NULL); 1547 } 1548 1549 static void virt_machine_2_8_options(MachineClass *mc) 1550 { 1551 } 1552 DEFINE_VIRT_MACHINE_AS_LATEST(2, 8) 1553 1554 #define VIRT_COMPAT_2_7 \ 1555 HW_COMPAT_2_7 1556 1557 static void virt_2_7_instance_init(Object *obj) 1558 { 1559 virt_2_8_instance_init(obj); 1560 } 1561 1562 static void virt_machine_2_7_options(MachineClass *mc) 1563 { 1564 virt_machine_2_8_options(mc); 1565 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1566 } 1567 DEFINE_VIRT_MACHINE(2, 7) 1568 1569 #define VIRT_COMPAT_2_6 \ 1570 HW_COMPAT_2_6 1571 1572 static void virt_2_6_instance_init(Object *obj) 1573 { 1574 virt_2_7_instance_init(obj); 1575 } 1576 1577 static void virt_machine_2_6_options(MachineClass *mc) 1578 { 1579 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1580 1581 virt_machine_2_7_options(mc); 1582 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1583 vmc->disallow_affinity_adjustment = true; 1584 } 1585 DEFINE_VIRT_MACHINE(2, 6) 1586