1 /*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
44 #include "net/net.h"
45 #include "system/device_tree.h"
46 #include "system/numa.h"
47 #include "system/runstate.h"
48 #include "system/tpm.h"
49 #include "system/tcg.h"
50 #include "system/kvm.h"
51 #include "system/hvf.h"
52 #include "system/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/cutils.h"
57 #include "qemu/error-report.h"
58 #include "qemu/module.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/virtio/virtio-pci.h"
61 #include "hw/core/sysbus-fdt.h"
62 #include "hw/platform-bus.h"
63 #include "hw/qdev-properties.h"
64 #include "hw/arm/fdt.h"
65 #include "hw/intc/arm_gic.h"
66 #include "hw/intc/arm_gicv3_common.h"
67 #include "hw/intc/arm_gicv3_its_common.h"
68 #include "hw/irq.h"
69 #include "kvm_arm.h"
70 #include "hvf_arm.h"
71 #include "hw/firmware/smbios.h"
72 #include "qapi/visitor.h"
73 #include "qapi/qapi-visit-common.h"
74 #include "qobject/qlist.h"
75 #include "standard-headers/linux/input.h"
76 #include "hw/arm/smmuv3.h"
77 #include "hw/acpi/acpi.h"
78 #include "target/arm/cpu-qom.h"
79 #include "target/arm/internals.h"
80 #include "target/arm/multiprocessing.h"
81 #include "target/arm/gtimer.h"
82 #include "hw/mem/pc-dimm.h"
83 #include "hw/mem/nvdimm.h"
84 #include "hw/acpi/generic_event_device.h"
85 #include "hw/uefi/var-service-api.h"
86 #include "hw/virtio/virtio-md-pci.h"
87 #include "hw/virtio/virtio-iommu.h"
88 #include "hw/char/pl011.h"
89 #include "qemu/guest-random.h"
90
91 static GlobalProperty arm_virt_compat[] = {
92 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" },
93 };
94 static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat);
95
96 /*
97 * This cannot be called from the virt_machine_class_init() because
98 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
99 * only is called on virt non abstract class init.
100 */
arm_virt_compat_set(MachineClass * mc)101 static void arm_virt_compat_set(MachineClass *mc)
102 {
103 compat_props_add(mc->compat_props, arm_virt_compat,
104 arm_virt_compat_len);
105 }
106
107 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \
108 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \
109 ObjectClass *oc, \
110 const void *data) \
111 { \
112 MachineClass *mc = MACHINE_CLASS(oc); \
113 arm_virt_compat_set(mc); \
114 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \
115 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \
116 MACHINE_VER_DEPRECATION(__VA_ARGS__); \
117 if (latest) { \
118 mc->alias = "virt"; \
119 } \
120 } \
121 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \
122 { \
123 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
124 .parent = TYPE_VIRT_MACHINE, \
125 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
126 }; \
127 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
128 { \
129 MACHINE_VER_DELETION(__VA_ARGS__); \
130 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \
131 } \
132 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__));
133
134 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
135 DEFINE_VIRT_MACHINE_IMPL(true, major, minor)
136 #define DEFINE_VIRT_MACHINE(major, minor) \
137 DEFINE_VIRT_MACHINE_IMPL(false, major, minor)
138
139
140 /* Number of external interrupt lines to configure the GIC with */
141 #define NUM_IRQS 256
142
143 #define PLATFORM_BUS_NUM_IRQS 64
144
145 /* Legacy RAM limit in GB (< version 4.0) */
146 #define LEGACY_RAMLIMIT_GB 255
147 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
148
149 /* Addresses and sizes of our components.
150 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
151 * 128MB..256MB is used for miscellaneous device I/O.
152 * 256MB..1GB is reserved for possible future PCI support (ie where the
153 * PCI memory window will go if we add a PCI host controller).
154 * 1GB and up is RAM (which may happily spill over into the
155 * high memory region beyond 4GB).
156 * This represents a compromise between how much RAM can be given to
157 * a 32 bit VM and leaving space for expansion and in particular for PCI.
158 * Note that devices should generally be placed at multiples of 0x10000,
159 * to accommodate guests using 64K pages.
160 */
161 static const MemMapEntry base_memmap[] = {
162 /* Space up to 0x8000000 is reserved for a boot ROM */
163 [VIRT_FLASH] = { 0, 0x08000000 },
164 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
165 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
166 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
167 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
168 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
169 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
170 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
171 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
172 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
173 /* This redistributor space allows up to 2*64kB*123 CPUs */
174 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
175 [VIRT_UART0] = { 0x09000000, 0x00001000 },
176 [VIRT_RTC] = { 0x09010000, 0x00001000 },
177 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
178 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
179 [VIRT_UART1] = { 0x09040000, 0x00001000 },
180 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
181 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
182 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
183 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
184 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
185 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
186 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
187 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
188 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
189 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
190 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
191 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
192 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
193 /* Actual RAM size depends on initial RAM and device memory settings */
194 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
195 };
196
197 /* Update the docs for highmem-mmio-size when changing this default */
198 #define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512
199 #define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB)
200
201 /*
202 * Highmem IO Regions: This memory map is floating, located after the RAM.
203 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
204 * top of the RAM, so that its base get the same alignment as the size,
205 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
206 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
207 * Note the extended_memmap is sized so that it eventually also includes the
208 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
209 * index of base_memmap).
210 *
211 * The memory map for these Highmem IO Regions can be in legacy or compact
212 * layout, depending on 'compact-highmem' property. With legacy layout, the
213 * PA space for one specific region is always reserved, even if the region
214 * has been disabled or doesn't fit into the PA space. However, the PA space
215 * for the region won't be reserved in these circumstances with compact layout.
216 *
217 * Note that the highmem-mmio-size property will update the high PCIE MMIO size
218 * field in this array.
219 */
220 static MemMapEntry extended_memmap[] = {
221 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
222 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
223 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
224 /* Second PCIe window */
225 [VIRT_HIGH_PCIE_MMIO] = { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE },
226 };
227
228 static const int a15irqmap[] = {
229 [VIRT_UART0] = 1,
230 [VIRT_RTC] = 2,
231 [VIRT_PCIE] = 3, /* ... to 6 */
232 [VIRT_GPIO] = 7,
233 [VIRT_UART1] = 8,
234 [VIRT_ACPI_GED] = 9,
235 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
236 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
237 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
238 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
239 };
240
create_randomness(MachineState * ms,const char * node)241 static void create_randomness(MachineState *ms, const char *node)
242 {
243 struct {
244 uint64_t kaslr;
245 uint8_t rng[32];
246 } seed;
247
248 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
249 return;
250 }
251 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
252 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
253 }
254
255 /*
256 * The CPU object always exposes the NS EL2 virt timer IRQ line,
257 * but we don't want to advertise it to the guest in the dtb or ACPI
258 * table unless it's really going to do something.
259 */
ns_el2_virt_timer_present(void)260 static bool ns_el2_virt_timer_present(void)
261 {
262 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
263 CPUARMState *env = &cpu->env;
264
265 return arm_feature(env, ARM_FEATURE_AARCH64) &&
266 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
267 }
268
create_fdt(VirtMachineState * vms)269 static void create_fdt(VirtMachineState *vms)
270 {
271 MachineState *ms = MACHINE(vms);
272 int nb_numa_nodes = ms->numa_state->num_nodes;
273 void *fdt = create_device_tree(&vms->fdt_size);
274
275 if (!fdt) {
276 error_report("create_device_tree() failed");
277 exit(1);
278 }
279
280 ms->fdt = fdt;
281
282 /* Header */
283 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
284 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
285 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
286 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
287
288 /*
289 * For QEMU, all DMA is coherent. Advertising this in the root node
290 * has two benefits:
291 *
292 * - It avoids potential bugs where we forget to mark a DMA
293 * capable device as being dma-coherent
294 * - It avoids spurious warnings from the Linux kernel about
295 * devices which can't do DMA at all
296 */
297 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0);
298
299 /* /chosen must exist for load_dtb to fill in necessary properties later */
300 qemu_fdt_add_subnode(fdt, "/chosen");
301 if (vms->dtb_randomness) {
302 create_randomness(ms, "/chosen");
303 }
304
305 if (vms->secure) {
306 qemu_fdt_add_subnode(fdt, "/secure-chosen");
307 if (vms->dtb_randomness) {
308 create_randomness(ms, "/secure-chosen");
309 }
310 }
311
312 qemu_fdt_add_subnode(fdt, "/aliases");
313
314 /* Clock node, for the benefit of the UART. The kernel device tree
315 * binding documentation claims the PL011 node clock properties are
316 * optional but in practice if you omit them the kernel refuses to
317 * probe for the device.
318 */
319 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
320 qemu_fdt_add_subnode(fdt, "/apb-pclk");
321 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
322 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
323 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
324 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
325 "clk24mhz");
326 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
327
328 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
329 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
330 uint32_t *matrix = g_malloc0(size);
331 int idx, i, j;
332
333 for (i = 0; i < nb_numa_nodes; i++) {
334 for (j = 0; j < nb_numa_nodes; j++) {
335 idx = (i * nb_numa_nodes + j) * 3;
336 matrix[idx + 0] = cpu_to_be32(i);
337 matrix[idx + 1] = cpu_to_be32(j);
338 matrix[idx + 2] =
339 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
340 }
341 }
342
343 qemu_fdt_add_subnode(fdt, "/distance-map");
344 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
345 "numa-distance-map-v1");
346 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
347 matrix, size);
348 g_free(matrix);
349 }
350 }
351
fdt_add_timer_nodes(const VirtMachineState * vms)352 static void fdt_add_timer_nodes(const VirtMachineState *vms)
353 {
354 /* On real hardware these interrupts are level-triggered.
355 * On KVM they were edge-triggered before host kernel version 4.4,
356 * and level-triggered afterwards.
357 * On emulated QEMU they are level-triggered.
358 *
359 * Getting the DTB info about them wrong is awkward for some
360 * guest kernels:
361 * pre-4.8 ignore the DT and leave the interrupt configured
362 * with whatever the GIC reset value (or the bootloader) left it at
363 * 4.8 before rc6 honour the incorrect data by programming it back
364 * into the GIC, causing problems
365 * 4.8rc6 and later ignore the DT and always write "level triggered"
366 * into the GIC
367 *
368 * For backwards-compatibility, virt-2.8 and earlier will continue
369 * to say these are edge-triggered, but later machines will report
370 * the correct information.
371 */
372 ARMCPU *armcpu;
373 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
374 MachineState *ms = MACHINE(vms);
375
376 if (vms->gic_version == VIRT_GIC_VERSION_2) {
377 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
378 GIC_FDT_IRQ_PPI_CPU_WIDTH,
379 (1 << MACHINE(vms)->smp.cpus) - 1);
380 }
381
382 qemu_fdt_add_subnode(ms->fdt, "/timer");
383
384 armcpu = ARM_CPU(qemu_get_cpu(0));
385 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
386 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
387 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
388 compat, sizeof(compat));
389 } else {
390 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
391 "arm,armv7-timer");
392 }
393 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
394 if (vms->ns_el2_virt_timer_irq) {
395 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
396 GIC_FDT_IRQ_TYPE_PPI,
397 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
398 GIC_FDT_IRQ_TYPE_PPI,
399 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
400 GIC_FDT_IRQ_TYPE_PPI,
401 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
402 GIC_FDT_IRQ_TYPE_PPI,
403 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
404 GIC_FDT_IRQ_TYPE_PPI,
405 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
406 } else {
407 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
408 GIC_FDT_IRQ_TYPE_PPI,
409 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
410 GIC_FDT_IRQ_TYPE_PPI,
411 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
412 GIC_FDT_IRQ_TYPE_PPI,
413 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
414 GIC_FDT_IRQ_TYPE_PPI,
415 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
416 }
417 }
418
fdt_add_cpu_nodes(const VirtMachineState * vms)419 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
420 {
421 int cpu;
422 int addr_cells = 1;
423 const MachineState *ms = MACHINE(vms);
424 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
425 int smp_cpus = ms->smp.cpus;
426
427 /*
428 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
429 * On ARM v8 64-bit systems value should be set to 2,
430 * that corresponds to the MPIDR_EL1 register size.
431 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
432 * in the system, #address-cells can be set to 1, since
433 * MPIDR_EL1[63:32] bits are not used for CPUs
434 * identification.
435 *
436 * Here we actually don't know whether our system is 32- or 64-bit one.
437 * The simplest way to go is to examine affinity IDs of all our CPUs. If
438 * at least one of them has Aff3 populated, we set #address-cells to 2.
439 */
440 for (cpu = 0; cpu < smp_cpus; cpu++) {
441 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
442
443 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) {
444 addr_cells = 2;
445 break;
446 }
447 }
448
449 qemu_fdt_add_subnode(ms->fdt, "/cpus");
450 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
451 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
452
453 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
454 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
455 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
456 CPUState *cs = CPU(armcpu);
457
458 qemu_fdt_add_subnode(ms->fdt, nodename);
459 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
460 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
461 armcpu->dtb_compatible);
462
463 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
464 qemu_fdt_setprop_string(ms->fdt, nodename,
465 "enable-method", "psci");
466 }
467
468 if (addr_cells == 2) {
469 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
470 arm_cpu_mp_affinity(armcpu));
471 } else {
472 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
473 arm_cpu_mp_affinity(armcpu));
474 }
475
476 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
477 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
478 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
479 }
480
481 if (!vmc->no_cpu_topology) {
482 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
483 qemu_fdt_alloc_phandle(ms->fdt));
484 }
485
486 g_free(nodename);
487 }
488
489 if (!vmc->no_cpu_topology) {
490 /*
491 * Add vCPU topology description through fdt node cpu-map.
492 *
493 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
494 * In a SMP system, the hierarchy of CPUs can be defined through
495 * four entities that are used to describe the layout of CPUs in
496 * the system: socket/cluster/core/thread.
497 *
498 * A socket node represents the boundary of system physical package
499 * and its child nodes must be one or more cluster nodes. A system
500 * can contain several layers of clustering within a single physical
501 * package and cluster nodes can be contained in parent cluster nodes.
502 *
503 * Note: currently we only support one layer of clustering within
504 * each physical package.
505 */
506 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
507
508 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
509 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
510 char *map_path;
511
512 if (ms->smp.threads > 1) {
513 map_path = g_strdup_printf(
514 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
515 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
516 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
517 (cpu / ms->smp.threads) % ms->smp.cores,
518 cpu % ms->smp.threads);
519 } else {
520 map_path = g_strdup_printf(
521 "/cpus/cpu-map/socket%d/cluster%d/core%d",
522 cpu / (ms->smp.clusters * ms->smp.cores),
523 (cpu / ms->smp.cores) % ms->smp.clusters,
524 cpu % ms->smp.cores);
525 }
526 qemu_fdt_add_path(ms->fdt, map_path);
527 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
528
529 g_free(map_path);
530 g_free(cpu_path);
531 }
532 }
533 }
534
fdt_add_its_gic_node(VirtMachineState * vms)535 static void fdt_add_its_gic_node(VirtMachineState *vms)
536 {
537 char *nodename;
538 MachineState *ms = MACHINE(vms);
539
540 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
541 nodename = g_strdup_printf("/intc/its@%" PRIx64,
542 vms->memmap[VIRT_GIC_ITS].base);
543 qemu_fdt_add_subnode(ms->fdt, nodename);
544 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
545 "arm,gic-v3-its");
546 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
547 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
548 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
549 2, vms->memmap[VIRT_GIC_ITS].base,
550 2, vms->memmap[VIRT_GIC_ITS].size);
551 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
552 g_free(nodename);
553 }
554
fdt_add_v2m_gic_node(VirtMachineState * vms)555 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
556 {
557 MachineState *ms = MACHINE(vms);
558 char *nodename;
559
560 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
561 vms->memmap[VIRT_GIC_V2M].base);
562 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
563 qemu_fdt_add_subnode(ms->fdt, nodename);
564 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
565 "arm,gic-v2m-frame");
566 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
567 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
568 2, vms->memmap[VIRT_GIC_V2M].base,
569 2, vms->memmap[VIRT_GIC_V2M].size);
570 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
571 g_free(nodename);
572 }
573
fdt_add_gic_node(VirtMachineState * vms)574 static void fdt_add_gic_node(VirtMachineState *vms)
575 {
576 MachineState *ms = MACHINE(vms);
577 char *nodename;
578
579 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
580 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
581
582 nodename = g_strdup_printf("/intc@%" PRIx64,
583 vms->memmap[VIRT_GIC_DIST].base);
584 qemu_fdt_add_subnode(ms->fdt, nodename);
585 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
586 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
587 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
588 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
589 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
590 if (vms->gic_version != VIRT_GIC_VERSION_2) {
591 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
592
593 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
594 "arm,gic-v3");
595
596 qemu_fdt_setprop_cell(ms->fdt, nodename,
597 "#redistributor-regions", nb_redist_regions);
598
599 if (nb_redist_regions == 1) {
600 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
601 2, vms->memmap[VIRT_GIC_DIST].base,
602 2, vms->memmap[VIRT_GIC_DIST].size,
603 2, vms->memmap[VIRT_GIC_REDIST].base,
604 2, vms->memmap[VIRT_GIC_REDIST].size);
605 } else {
606 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
607 2, vms->memmap[VIRT_GIC_DIST].base,
608 2, vms->memmap[VIRT_GIC_DIST].size,
609 2, vms->memmap[VIRT_GIC_REDIST].base,
610 2, vms->memmap[VIRT_GIC_REDIST].size,
611 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
612 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
613 }
614
615 if (vms->virt) {
616 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
617 GIC_FDT_IRQ_TYPE_PPI,
618 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
619 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
620 }
621 } else {
622 /* 'cortex-a15-gic' means 'GIC v2' */
623 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
624 "arm,cortex-a15-gic");
625 if (!vms->virt) {
626 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
627 2, vms->memmap[VIRT_GIC_DIST].base,
628 2, vms->memmap[VIRT_GIC_DIST].size,
629 2, vms->memmap[VIRT_GIC_CPU].base,
630 2, vms->memmap[VIRT_GIC_CPU].size);
631 } else {
632 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
633 2, vms->memmap[VIRT_GIC_DIST].base,
634 2, vms->memmap[VIRT_GIC_DIST].size,
635 2, vms->memmap[VIRT_GIC_CPU].base,
636 2, vms->memmap[VIRT_GIC_CPU].size,
637 2, vms->memmap[VIRT_GIC_HYP].base,
638 2, vms->memmap[VIRT_GIC_HYP].size,
639 2, vms->memmap[VIRT_GIC_VCPU].base,
640 2, vms->memmap[VIRT_GIC_VCPU].size);
641 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
642 GIC_FDT_IRQ_TYPE_PPI,
643 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
644 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
645 }
646 }
647
648 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
649 g_free(nodename);
650 }
651
fdt_add_pmu_nodes(const VirtMachineState * vms)652 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
653 {
654 ARMCPU *armcpu = ARM_CPU(first_cpu);
655 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
656 MachineState *ms = MACHINE(vms);
657
658 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
659 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
660 return;
661 }
662
663 if (vms->gic_version == VIRT_GIC_VERSION_2) {
664 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
665 GIC_FDT_IRQ_PPI_CPU_WIDTH,
666 (1 << MACHINE(vms)->smp.cpus) - 1);
667 }
668
669 qemu_fdt_add_subnode(ms->fdt, "/pmu");
670 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
671 const char compat[] = "arm,armv8-pmuv3";
672 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
673 compat, sizeof(compat));
674 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
675 GIC_FDT_IRQ_TYPE_PPI,
676 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags);
677 }
678 }
679
create_acpi_ged(VirtMachineState * vms)680 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
681 {
682 DeviceState *dev;
683 MachineState *ms = MACHINE(vms);
684 int irq = vms->irqmap[VIRT_ACPI_GED];
685 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
686
687 if (ms->ram_slots) {
688 event |= ACPI_GED_MEM_HOTPLUG_EVT;
689 }
690
691 if (ms->nvdimms_state->is_enabled) {
692 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
693 }
694
695 dev = qdev_new(TYPE_ACPI_GED);
696 qdev_prop_set_uint32(dev, "ged-event", event);
697 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
698
699 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
700 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
701 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
702
703 return dev;
704 }
705
create_its(VirtMachineState * vms)706 static void create_its(VirtMachineState *vms)
707 {
708 DeviceState *dev;
709
710 assert(vms->its);
711 if (!kvm_irqchip_in_kernel() && !vms->tcg_its) {
712 /*
713 * Do nothing if ITS is neither supported by the host nor emulated by
714 * the machine.
715 */
716 return;
717 }
718
719 dev = qdev_new(its_class_name());
720
721 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
722 &error_abort);
723 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
724 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
725
726 fdt_add_its_gic_node(vms);
727 vms->msi_controller = VIRT_MSI_CTRL_ITS;
728 }
729
create_v2m(VirtMachineState * vms)730 static void create_v2m(VirtMachineState *vms)
731 {
732 int i;
733 int irq = vms->irqmap[VIRT_GIC_V2M];
734 DeviceState *dev;
735
736 dev = qdev_new("arm-gicv2m");
737 qdev_prop_set_uint32(dev, "base-spi", irq);
738 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
739 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
740 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
741
742 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
743 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
744 qdev_get_gpio_in(vms->gic, irq + i));
745 }
746
747 fdt_add_v2m_gic_node(vms);
748 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
749 }
750
751 /*
752 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
753 * It's permitted to have a configuration with NMI in the CPU (and thus the
754 * GICv3 CPU interface) but not in the distributor/redistributors, but it's
755 * not very useful.
756 */
gicv3_nmi_present(VirtMachineState * vms)757 static bool gicv3_nmi_present(VirtMachineState *vms)
758 {
759 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
760
761 return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) &&
762 (vms->gic_version != VIRT_GIC_VERSION_2);
763 }
764
create_gic(VirtMachineState * vms,MemoryRegion * mem)765 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
766 {
767 MachineState *ms = MACHINE(vms);
768 /* We create a standalone GIC */
769 SysBusDevice *gicbusdev;
770 const char *gictype;
771 int i;
772 unsigned int smp_cpus = ms->smp.cpus;
773 uint32_t nb_redist_regions = 0;
774 int revision;
775
776 if (vms->gic_version == VIRT_GIC_VERSION_2) {
777 gictype = gic_class_name();
778 } else {
779 gictype = gicv3_class_name();
780 }
781
782 switch (vms->gic_version) {
783 case VIRT_GIC_VERSION_2:
784 revision = 2;
785 break;
786 case VIRT_GIC_VERSION_3:
787 revision = 3;
788 break;
789 case VIRT_GIC_VERSION_4:
790 revision = 4;
791 break;
792 default:
793 g_assert_not_reached();
794 }
795 vms->gic = qdev_new(gictype);
796 qdev_prop_set_uint32(vms->gic, "revision", revision);
797 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
798 /* Note that the num-irq property counts both internal and external
799 * interrupts; there are always 32 of the former (mandated by GIC spec).
800 */
801 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
802 if (!kvm_irqchip_in_kernel()) {
803 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
804 }
805
806 if (vms->gic_version != VIRT_GIC_VERSION_2) {
807 QList *redist_region_count;
808 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
809 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
810
811 nb_redist_regions = virt_gicv3_redist_region_count(vms);
812
813 redist_region_count = qlist_new();
814 qlist_append_int(redist_region_count, redist0_count);
815 if (nb_redist_regions == 2) {
816 uint32_t redist1_capacity =
817 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
818
819 qlist_append_int(redist_region_count,
820 MIN(smp_cpus - redist0_count, redist1_capacity));
821 }
822 qdev_prop_set_array(vms->gic, "redist-region-count",
823 redist_region_count);
824
825 if (!kvm_irqchip_in_kernel()) {
826 if (vms->tcg_its) {
827 object_property_set_link(OBJECT(vms->gic), "sysmem",
828 OBJECT(mem), &error_fatal);
829 qdev_prop_set_bit(vms->gic, "has-lpi", true);
830 }
831 }
832 } else {
833 if (!kvm_irqchip_in_kernel()) {
834 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
835 vms->virt);
836 }
837 }
838
839 if (gicv3_nmi_present(vms)) {
840 qdev_prop_set_bit(vms->gic, "has-nmi", true);
841 }
842
843 gicbusdev = SYS_BUS_DEVICE(vms->gic);
844 sysbus_realize_and_unref(gicbusdev, &error_fatal);
845 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
846 if (vms->gic_version != VIRT_GIC_VERSION_2) {
847 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
848 if (nb_redist_regions == 2) {
849 sysbus_mmio_map(gicbusdev, 2,
850 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
851 }
852 } else {
853 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
854 if (vms->virt) {
855 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
856 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
857 }
858 }
859
860 /* Wire the outputs from each CPU's generic timer and the GICv3
861 * maintenance interrupt signal to the appropriate GIC PPI inputs,
862 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
863 * CPU's inputs.
864 */
865 for (i = 0; i < smp_cpus; i++) {
866 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
867 int intidbase = NUM_IRQS + i * GIC_INTERNAL;
868 /* Mapping from the output timer irq lines from the CPU to the
869 * GIC PPI inputs we use for the virt board.
870 */
871 const int timer_irq[] = {
872 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
873 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
874 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
875 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
876 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
877 [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
878 [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
879 };
880
881 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
882 qdev_connect_gpio_out(cpudev, irq,
883 qdev_get_gpio_in(vms->gic,
884 intidbase + timer_irq[irq]));
885 }
886
887 if (vms->gic_version != VIRT_GIC_VERSION_2) {
888 qemu_irq irq = qdev_get_gpio_in(vms->gic,
889 intidbase + ARCH_GIC_MAINT_IRQ);
890 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
891 0, irq);
892 } else if (vms->virt) {
893 qemu_irq irq = qdev_get_gpio_in(vms->gic,
894 intidbase + ARCH_GIC_MAINT_IRQ);
895 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
896 }
897
898 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
899 qdev_get_gpio_in(vms->gic, intidbase
900 + VIRTUAL_PMU_IRQ));
901
902 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
903 sysbus_connect_irq(gicbusdev, i + smp_cpus,
904 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
905 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
906 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
907 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
908 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
909
910 if (vms->gic_version != VIRT_GIC_VERSION_2) {
911 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,
912 qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
913 sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,
914 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
915 }
916 }
917
918 fdt_add_gic_node(vms);
919
920 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
921 create_its(vms);
922 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
923 create_v2m(vms);
924 }
925 }
926
create_uart(const VirtMachineState * vms,int uart,MemoryRegion * mem,Chardev * chr,bool secure)927 static void create_uart(const VirtMachineState *vms, int uart,
928 MemoryRegion *mem, Chardev *chr, bool secure)
929 {
930 char *nodename;
931 hwaddr base = vms->memmap[uart].base;
932 hwaddr size = vms->memmap[uart].size;
933 int irq = vms->irqmap[uart];
934 const char compat[] = "arm,pl011\0arm,primecell";
935 const char clocknames[] = "uartclk\0apb_pclk";
936 DeviceState *dev = qdev_new(TYPE_PL011);
937 SysBusDevice *s = SYS_BUS_DEVICE(dev);
938 MachineState *ms = MACHINE(vms);
939
940 qdev_prop_set_chr(dev, "chardev", chr);
941 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
942 memory_region_add_subregion(mem, base,
943 sysbus_mmio_get_region(s, 0));
944 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
945
946 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
947 qemu_fdt_add_subnode(ms->fdt, nodename);
948 /* Note that we can't use setprop_string because of the embedded NUL */
949 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
950 compat, sizeof(compat));
951 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
952 2, base, 2, size);
953 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
954 GIC_FDT_IRQ_TYPE_SPI, irq,
955 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
956 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
957 vms->clock_phandle, vms->clock_phandle);
958 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
959 clocknames, sizeof(clocknames));
960
961 if (uart == VIRT_UART0) {
962 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
963 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
964 } else {
965 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename);
966 }
967 if (secure) {
968 /* Mark as not usable by the normal world */
969 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
970 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
971
972 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
973 nodename);
974 }
975
976 g_free(nodename);
977 }
978
create_rtc(const VirtMachineState * vms)979 static void create_rtc(const VirtMachineState *vms)
980 {
981 char *nodename;
982 hwaddr base = vms->memmap[VIRT_RTC].base;
983 hwaddr size = vms->memmap[VIRT_RTC].size;
984 int irq = vms->irqmap[VIRT_RTC];
985 const char compat[] = "arm,pl031\0arm,primecell";
986 MachineState *ms = MACHINE(vms);
987
988 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
989
990 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
991 qemu_fdt_add_subnode(ms->fdt, nodename);
992 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
993 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
994 2, base, 2, size);
995 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
996 GIC_FDT_IRQ_TYPE_SPI, irq,
997 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
998 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
999 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1000 g_free(nodename);
1001 }
1002
1003 static DeviceState *gpio_key_dev;
virt_powerdown_req(Notifier * n,void * opaque)1004 static void virt_powerdown_req(Notifier *n, void *opaque)
1005 {
1006 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
1007
1008 if (s->acpi_dev) {
1009 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
1010 } else {
1011 /* use gpio Pin for power button event */
1012 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
1013 }
1014 }
1015
create_gpio_keys(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1016 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
1017 uint32_t phandle)
1018 {
1019 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
1020 qdev_get_gpio_in(pl061_dev,
1021 GPIO_PIN_POWER_BUTTON));
1022
1023 qemu_fdt_add_subnode(fdt, "/gpio-keys");
1024 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
1025
1026 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
1027 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
1028 "label", "GPIO Key Poweroff");
1029 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
1030 KEY_POWER);
1031 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
1032 "gpios", phandle, GPIO_PIN_POWER_BUTTON, 0);
1033 }
1034
1035 #define SECURE_GPIO_POWEROFF 0
1036 #define SECURE_GPIO_RESET 1
1037
create_secure_gpio_pwr(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1038 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
1039 uint32_t phandle)
1040 {
1041 DeviceState *gpio_pwr_dev;
1042
1043 /* gpio-pwr */
1044 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
1045
1046 /* connect secure pl061 to gpio-pwr */
1047 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
1048 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
1049 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
1050 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
1051
1052 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
1053 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
1054 "gpio-poweroff");
1055 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
1056 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
1057 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
1058 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
1059 "okay");
1060
1061 qemu_fdt_add_subnode(fdt, "/gpio-restart");
1062 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
1063 "gpio-restart");
1064 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
1065 "gpios", phandle, SECURE_GPIO_RESET, 0);
1066 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
1067 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
1068 "okay");
1069 }
1070
create_gpio_devices(const VirtMachineState * vms,int gpio,MemoryRegion * mem)1071 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
1072 MemoryRegion *mem)
1073 {
1074 char *nodename;
1075 DeviceState *pl061_dev;
1076 hwaddr base = vms->memmap[gpio].base;
1077 hwaddr size = vms->memmap[gpio].size;
1078 int irq = vms->irqmap[gpio];
1079 const char compat[] = "arm,pl061\0arm,primecell";
1080 SysBusDevice *s;
1081 MachineState *ms = MACHINE(vms);
1082
1083 pl061_dev = qdev_new("pl061");
1084 /* Pull lines down to 0 if not driven by the PL061 */
1085 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
1086 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
1087 s = SYS_BUS_DEVICE(pl061_dev);
1088 sysbus_realize_and_unref(s, &error_fatal);
1089 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
1090 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1091
1092 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1093 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1094 qemu_fdt_add_subnode(ms->fdt, nodename);
1095 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1096 2, base, 2, size);
1097 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1098 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1099 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1100 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1101 GIC_FDT_IRQ_TYPE_SPI, irq,
1102 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1103 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1104 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1105 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1106
1107 if (gpio != VIRT_GPIO) {
1108 /* Mark as not usable by the normal world */
1109 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1110 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1111 }
1112 g_free(nodename);
1113
1114 /* Child gpio devices */
1115 if (gpio == VIRT_GPIO) {
1116 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1117 } else {
1118 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1119 }
1120 }
1121
create_virtio_devices(const VirtMachineState * vms)1122 static void create_virtio_devices(const VirtMachineState *vms)
1123 {
1124 int i;
1125 hwaddr size = vms->memmap[VIRT_MMIO].size;
1126 MachineState *ms = MACHINE(vms);
1127
1128 /* We create the transports in forwards order. Since qbus_realize()
1129 * prepends (not appends) new child buses, the incrementing loop below will
1130 * create a list of virtio-mmio buses with decreasing base addresses.
1131 *
1132 * When a -device option is processed from the command line,
1133 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1134 * order. The upshot is that -device options in increasing command line
1135 * order are mapped to virtio-mmio buses with decreasing base addresses.
1136 *
1137 * When this code was originally written, that arrangement ensured that the
1138 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1139 * the first -device on the command line. (The end-to-end order is a
1140 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1141 * guest kernel's name-to-address assignment strategy.)
1142 *
1143 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1144 * the message, if not necessarily the code, of commit 70161ff336.
1145 * Therefore the loop now establishes the inverse of the original intent.
1146 *
1147 * Unfortunately, we can't counteract the kernel change by reversing the
1148 * loop; it would break existing command lines.
1149 *
1150 * In any case, the kernel makes no guarantee about the stability of
1151 * enumeration order of virtio devices (as demonstrated by it changing
1152 * between kernel versions). For reliable and stable identification
1153 * of disks users must use UUIDs or similar mechanisms.
1154 */
1155 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1156 int irq = vms->irqmap[VIRT_MMIO] + i;
1157 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1158
1159 sysbus_create_simple("virtio-mmio", base,
1160 qdev_get_gpio_in(vms->gic, irq));
1161 }
1162
1163 /* We add dtb nodes in reverse order so that they appear in the finished
1164 * device tree lowest address first.
1165 *
1166 * Note that this mapping is independent of the loop above. The previous
1167 * loop influences virtio device to virtio transport assignment, whereas
1168 * this loop controls how virtio transports are laid out in the dtb.
1169 */
1170 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1171 char *nodename;
1172 int irq = vms->irqmap[VIRT_MMIO] + i;
1173 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1174
1175 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1176 qemu_fdt_add_subnode(ms->fdt, nodename);
1177 qemu_fdt_setprop_string(ms->fdt, nodename,
1178 "compatible", "virtio,mmio");
1179 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1180 2, base, 2, size);
1181 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1182 GIC_FDT_IRQ_TYPE_SPI, irq,
1183 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1184 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1185 g_free(nodename);
1186 }
1187 }
1188
1189 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1190
virt_flash_create1(VirtMachineState * vms,const char * name,const char * alias_prop_name)1191 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1192 const char *name,
1193 const char *alias_prop_name)
1194 {
1195 /*
1196 * Create a single flash device. We use the same parameters as
1197 * the flash devices on the Versatile Express board.
1198 */
1199 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1200
1201 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1202 qdev_prop_set_uint8(dev, "width", 4);
1203 qdev_prop_set_uint8(dev, "device-width", 2);
1204 qdev_prop_set_bit(dev, "big-endian", false);
1205 qdev_prop_set_uint16(dev, "id0", 0x89);
1206 qdev_prop_set_uint16(dev, "id1", 0x18);
1207 qdev_prop_set_uint16(dev, "id2", 0x00);
1208 qdev_prop_set_uint16(dev, "id3", 0x00);
1209 qdev_prop_set_string(dev, "name", name);
1210 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1211 object_property_add_alias(OBJECT(vms), alias_prop_name,
1212 OBJECT(dev), "drive");
1213 return PFLASH_CFI01(dev);
1214 }
1215
virt_flash_create(VirtMachineState * vms)1216 static void virt_flash_create(VirtMachineState *vms)
1217 {
1218 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1219 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1220 }
1221
virt_flash_map1(PFlashCFI01 * flash,hwaddr base,hwaddr size,MemoryRegion * sysmem)1222 static void virt_flash_map1(PFlashCFI01 *flash,
1223 hwaddr base, hwaddr size,
1224 MemoryRegion *sysmem)
1225 {
1226 DeviceState *dev = DEVICE(flash);
1227
1228 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1229 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1230 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1231 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1232
1233 memory_region_add_subregion(sysmem, base,
1234 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1235 0));
1236 }
1237
virt_flash_map(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1238 static void virt_flash_map(VirtMachineState *vms,
1239 MemoryRegion *sysmem,
1240 MemoryRegion *secure_sysmem)
1241 {
1242 /*
1243 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1244 * sysmem is the system memory space. secure_sysmem is the secure view
1245 * of the system, and the first flash device should be made visible only
1246 * there. The second flash device is visible to both secure and nonsecure.
1247 * If sysmem == secure_sysmem this means there is no separate Secure
1248 * address space and both flash devices are generally visible.
1249 */
1250 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1251 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1252
1253 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1254 secure_sysmem);
1255 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1256 sysmem);
1257 }
1258
virt_flash_fdt(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1259 static void virt_flash_fdt(VirtMachineState *vms,
1260 MemoryRegion *sysmem,
1261 MemoryRegion *secure_sysmem)
1262 {
1263 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1264 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1265 MachineState *ms = MACHINE(vms);
1266 char *nodename;
1267
1268 if (sysmem == secure_sysmem) {
1269 /* Report both flash devices as a single node in the DT */
1270 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1271 qemu_fdt_add_subnode(ms->fdt, nodename);
1272 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1273 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1274 2, flashbase, 2, flashsize,
1275 2, flashbase + flashsize, 2, flashsize);
1276 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1277 g_free(nodename);
1278 } else {
1279 /*
1280 * Report the devices as separate nodes so we can mark one as
1281 * only visible to the secure world.
1282 */
1283 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1284 qemu_fdt_add_subnode(ms->fdt, nodename);
1285 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1286 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1287 2, flashbase, 2, flashsize);
1288 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1289 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1290 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1291 g_free(nodename);
1292
1293 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1294 qemu_fdt_add_subnode(ms->fdt, nodename);
1295 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1296 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1297 2, flashbase + flashsize, 2, flashsize);
1298 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1299 g_free(nodename);
1300 }
1301 }
1302
virt_firmware_init(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1303 static bool virt_firmware_init(VirtMachineState *vms,
1304 MemoryRegion *sysmem,
1305 MemoryRegion *secure_sysmem)
1306 {
1307 int i;
1308 const char *bios_name;
1309 BlockBackend *pflash_blk0;
1310
1311 /* Map legacy -drive if=pflash to machine properties */
1312 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1313 pflash_cfi01_legacy_drive(vms->flash[i],
1314 drive_get(IF_PFLASH, 0, i));
1315 }
1316
1317 virt_flash_map(vms, sysmem, secure_sysmem);
1318
1319 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1320
1321 bios_name = MACHINE(vms)->firmware;
1322 if (bios_name) {
1323 char *fname;
1324 MemoryRegion *mr;
1325 int image_size;
1326
1327 if (pflash_blk0) {
1328 error_report("The contents of the first flash device may be "
1329 "specified with -bios or with -drive if=pflash... "
1330 "but you cannot use both options at once");
1331 exit(1);
1332 }
1333
1334 /* Fall back to -bios */
1335
1336 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1337 if (!fname) {
1338 error_report("Could not find ROM image '%s'", bios_name);
1339 exit(1);
1340 }
1341 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1342 image_size = load_image_mr(fname, mr);
1343 g_free(fname);
1344 if (image_size < 0) {
1345 error_report("Could not load ROM image '%s'", bios_name);
1346 exit(1);
1347 }
1348 }
1349
1350 return pflash_blk0 || bios_name;
1351 }
1352
create_fw_cfg(const VirtMachineState * vms,AddressSpace * as)1353 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1354 {
1355 MachineState *ms = MACHINE(vms);
1356 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1357 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1358 FWCfgState *fw_cfg;
1359 char *nodename;
1360
1361 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1362 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1363
1364 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1365 qemu_fdt_add_subnode(ms->fdt, nodename);
1366 qemu_fdt_setprop_string(ms->fdt, nodename,
1367 "compatible", "qemu,fw-cfg-mmio");
1368 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1369 2, base, 2, size);
1370 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1371 g_free(nodename);
1372 return fw_cfg;
1373 }
1374
create_pcie_irq_map(const MachineState * ms,uint32_t gic_phandle,int first_irq,const char * nodename)1375 static void create_pcie_irq_map(const MachineState *ms,
1376 uint32_t gic_phandle,
1377 int first_irq, const char *nodename)
1378 {
1379 int devfn, pin;
1380 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1381 uint32_t *irq_map = full_irq_map;
1382
1383 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1384 for (pin = 0; pin < 4; pin++) {
1385 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1386 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1387 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1388 int i;
1389
1390 uint32_t map[] = {
1391 devfn << 8, 0, 0, /* devfn */
1392 pin + 1, /* PCI pin */
1393 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1394
1395 /* Convert map to big endian */
1396 for (i = 0; i < 10; i++) {
1397 irq_map[i] = cpu_to_be32(map[i]);
1398 }
1399 irq_map += 10;
1400 }
1401 }
1402
1403 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1404 full_irq_map, sizeof(full_irq_map));
1405
1406 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1407 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1408 0, 0,
1409 0x7 /* PCI irq */);
1410 }
1411
create_smmu(const VirtMachineState * vms,PCIBus * bus)1412 static void create_smmu(const VirtMachineState *vms,
1413 PCIBus *bus)
1414 {
1415 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1416 char *node;
1417 const char compat[] = "arm,smmu-v3";
1418 int irq = vms->irqmap[VIRT_SMMU];
1419 int i;
1420 hwaddr base = vms->memmap[VIRT_SMMU].base;
1421 hwaddr size = vms->memmap[VIRT_SMMU].size;
1422 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1423 DeviceState *dev;
1424 MachineState *ms = MACHINE(vms);
1425
1426 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1427 return;
1428 }
1429
1430 dev = qdev_new(TYPE_ARM_SMMUV3);
1431
1432 if (!vmc->no_nested_smmu) {
1433 object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal);
1434 }
1435 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1436 &error_abort);
1437 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1438 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1439 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1440 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1441 qdev_get_gpio_in(vms->gic, irq + i));
1442 }
1443
1444 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1445 qemu_fdt_add_subnode(ms->fdt, node);
1446 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1447 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1448
1449 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1450 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1451 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1452 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1453 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1454
1455 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1456 sizeof(irq_names));
1457
1458 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1459
1460 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1461
1462 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1463 g_free(node);
1464 }
1465
create_virtio_iommu_dt_bindings(VirtMachineState * vms)1466 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1467 {
1468 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1469 uint16_t bdf = vms->virtio_iommu_bdf;
1470 MachineState *ms = MACHINE(vms);
1471 char *node;
1472
1473 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1474
1475 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1476 PCI_SLOT(bdf), PCI_FUNC(bdf));
1477 qemu_fdt_add_subnode(ms->fdt, node);
1478 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1479 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1480 1, bdf << 8, 1, 0, 1, 0,
1481 1, 0, 1, 0);
1482
1483 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1484 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1485 g_free(node);
1486
1487 if (!vms->default_bus_bypass_iommu) {
1488 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1489 0x0, vms->iommu_phandle, 0x0, bdf,
1490 bdf + 1, vms->iommu_phandle, bdf + 1,
1491 0xffff - bdf);
1492 }
1493 }
1494
create_pcie(VirtMachineState * vms)1495 static void create_pcie(VirtMachineState *vms)
1496 {
1497 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1498 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1499 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1500 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1501 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1502 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1503 hwaddr base_ecam, size_ecam;
1504 hwaddr base = base_mmio;
1505 int nr_pcie_buses;
1506 int irq = vms->irqmap[VIRT_PCIE];
1507 MemoryRegion *mmio_alias;
1508 MemoryRegion *mmio_reg;
1509 MemoryRegion *ecam_alias;
1510 MemoryRegion *ecam_reg;
1511 DeviceState *dev;
1512 char *nodename;
1513 int i, ecam_id;
1514 PCIHostState *pci;
1515 MachineState *ms = MACHINE(vms);
1516 MachineClass *mc = MACHINE_GET_CLASS(ms);
1517
1518 dev = qdev_new(TYPE_GPEX_HOST);
1519 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1520
1521 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1522 base_ecam = vms->memmap[ecam_id].base;
1523 size_ecam = vms->memmap[ecam_id].size;
1524 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1525 /* Map only the first size_ecam bytes of ECAM space */
1526 ecam_alias = g_new0(MemoryRegion, 1);
1527 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1528 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1529 ecam_reg, 0, size_ecam);
1530 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1531
1532 /* Map the MMIO window into system address space so as to expose
1533 * the section of PCI MMIO space which starts at the same base address
1534 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1535 * the window).
1536 */
1537 mmio_alias = g_new0(MemoryRegion, 1);
1538 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1539 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1540 mmio_reg, base_mmio, size_mmio);
1541 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1542
1543 if (vms->highmem_mmio) {
1544 /* Map high MMIO space */
1545 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1546
1547 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1548 mmio_reg, base_mmio_high, size_mmio_high);
1549 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1550 high_mmio_alias);
1551 }
1552
1553 /* Map IO port space */
1554 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1555
1556 for (i = 0; i < PCI_NUM_PINS; i++) {
1557 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1558 qdev_get_gpio_in(vms->gic, irq + i));
1559 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1560 }
1561
1562 pci = PCI_HOST_BRIDGE(dev);
1563 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1564 vms->bus = pci->bus;
1565 if (vms->bus) {
1566 pci_init_nic_devices(pci->bus, mc->default_nic);
1567 }
1568
1569 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1570 qemu_fdt_add_subnode(ms->fdt, nodename);
1571 qemu_fdt_setprop_string(ms->fdt, nodename,
1572 "compatible", "pci-host-ecam-generic");
1573 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1574 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1575 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1576 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1577 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1578 nr_pcie_buses - 1);
1579 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1580
1581 if (vms->msi_phandle) {
1582 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1583 0, vms->msi_phandle, 0, 0x10000);
1584 }
1585
1586 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1587 2, base_ecam, 2, size_ecam);
1588
1589 if (vms->highmem_mmio) {
1590 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1591 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1592 2, base_pio, 2, size_pio,
1593 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1594 2, base_mmio, 2, size_mmio,
1595 1, FDT_PCI_RANGE_MMIO_64BIT,
1596 2, base_mmio_high,
1597 2, base_mmio_high, 2, size_mmio_high);
1598 } else {
1599 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1600 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1601 2, base_pio, 2, size_pio,
1602 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1603 2, base_mmio, 2, size_mmio);
1604 }
1605
1606 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1607 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1608
1609 if (vms->iommu) {
1610 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1611
1612 switch (vms->iommu) {
1613 case VIRT_IOMMU_SMMUV3:
1614 create_smmu(vms, vms->bus);
1615 if (!vms->default_bus_bypass_iommu) {
1616 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1617 0x0, vms->iommu_phandle, 0x0, 0x10000);
1618 }
1619 break;
1620 default:
1621 g_assert_not_reached();
1622 }
1623 }
1624 }
1625
create_platform_bus(VirtMachineState * vms)1626 static void create_platform_bus(VirtMachineState *vms)
1627 {
1628 DeviceState *dev;
1629 SysBusDevice *s;
1630 int i;
1631 MemoryRegion *sysmem = get_system_memory();
1632
1633 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1634 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1635 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1636 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1637 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1638 vms->platform_bus_dev = dev;
1639
1640 s = SYS_BUS_DEVICE(dev);
1641 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1642 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1643 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1644 }
1645
1646 memory_region_add_subregion(sysmem,
1647 vms->memmap[VIRT_PLATFORM_BUS].base,
1648 sysbus_mmio_get_region(s, 0));
1649 }
1650
create_tag_ram(MemoryRegion * tag_sysmem,hwaddr base,hwaddr size,const char * name)1651 static void create_tag_ram(MemoryRegion *tag_sysmem,
1652 hwaddr base, hwaddr size,
1653 const char *name)
1654 {
1655 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1656
1657 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1658 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1659 }
1660
create_secure_ram(VirtMachineState * vms,MemoryRegion * secure_sysmem,MemoryRegion * secure_tag_sysmem)1661 static void create_secure_ram(VirtMachineState *vms,
1662 MemoryRegion *secure_sysmem,
1663 MemoryRegion *secure_tag_sysmem)
1664 {
1665 MemoryRegion *secram = g_new(MemoryRegion, 1);
1666 char *nodename;
1667 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1668 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1669 MachineState *ms = MACHINE(vms);
1670
1671 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1672 &error_fatal);
1673 memory_region_add_subregion(secure_sysmem, base, secram);
1674
1675 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1676 qemu_fdt_add_subnode(ms->fdt, nodename);
1677 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1678 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1679 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1680 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1681
1682 if (secure_tag_sysmem) {
1683 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1684 }
1685
1686 g_free(nodename);
1687 }
1688
machvirt_dtb(const struct arm_boot_info * binfo,int * fdt_size)1689 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1690 {
1691 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1692 bootinfo);
1693 MachineState *ms = MACHINE(board);
1694
1695
1696 *fdt_size = board->fdt_size;
1697 return ms->fdt;
1698 }
1699
virt_build_smbios(VirtMachineState * vms)1700 static void virt_build_smbios(VirtMachineState *vms)
1701 {
1702 MachineClass *mc = MACHINE_GET_CLASS(vms);
1703 MachineState *ms = MACHINE(vms);
1704 uint8_t *smbios_tables, *smbios_anchor;
1705 size_t smbios_tables_len, smbios_anchor_len;
1706 struct smbios_phys_mem_area mem_array;
1707 const char *product = "QEMU Virtual Machine";
1708
1709 if (kvm_enabled()) {
1710 product = "KVM Virtual Machine";
1711 }
1712
1713 smbios_set_defaults("QEMU", product, mc->name);
1714
1715 /* build the array of physical mem area from base_memmap */
1716 mem_array.address = vms->memmap[VIRT_MEM].base;
1717 mem_array.length = ms->ram_size;
1718
1719 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1,
1720 &smbios_tables, &smbios_tables_len,
1721 &smbios_anchor, &smbios_anchor_len,
1722 &error_fatal);
1723
1724 if (smbios_anchor) {
1725 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1726 smbios_tables, smbios_tables_len);
1727 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1728 smbios_anchor, smbios_anchor_len);
1729 }
1730 }
1731
1732 static
virt_machine_done(Notifier * notifier,void * data)1733 void virt_machine_done(Notifier *notifier, void *data)
1734 {
1735 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1736 machine_done);
1737 MachineState *ms = MACHINE(vms);
1738 ARMCPU *cpu = ARM_CPU(first_cpu);
1739 struct arm_boot_info *info = &vms->bootinfo;
1740 AddressSpace *as = arm_boot_address_space(cpu, info);
1741
1742 /*
1743 * If the user provided a dtb, we assume the dynamic sysbus nodes
1744 * already are integrated there. This corresponds to a use case where
1745 * the dynamic sysbus nodes are complex and their generation is not yet
1746 * supported. In that case the user can take charge of the guest dt
1747 * while qemu takes charge of the qom stuff.
1748 */
1749 if (info->dtb_filename == NULL) {
1750 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1751 vms->memmap[VIRT_PLATFORM_BUS].base,
1752 vms->memmap[VIRT_PLATFORM_BUS].size,
1753 vms->irqmap[VIRT_PLATFORM_BUS]);
1754 }
1755 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) {
1756 exit(1);
1757 }
1758
1759 pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus,
1760 &error_abort);
1761
1762 virt_acpi_setup(vms);
1763 virt_build_smbios(vms);
1764 }
1765
virt_cpu_mp_affinity(VirtMachineState * vms,int idx)1766 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1767 {
1768 uint8_t clustersz;
1769
1770 /*
1771 * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts)
1772 * and to improve SGI efficiency.
1773 */
1774 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1775 clustersz = GIC_TARGETLIST_BITS;
1776 } else {
1777 clustersz = GICV3_TARGETLIST_BITS;
1778 }
1779
1780 return arm_build_mp_affinity(idx, clustersz);
1781 }
1782
virt_get_high_memmap_enabled(VirtMachineState * vms,int index)1783 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
1784 int index)
1785 {
1786 bool *enabled_array[] = {
1787 &vms->highmem_redists,
1788 &vms->highmem_ecam,
1789 &vms->highmem_mmio,
1790 };
1791
1792 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1793 ARRAY_SIZE(enabled_array));
1794 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1795
1796 return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1797 }
1798
virt_set_high_memmap(VirtMachineState * vms,hwaddr base,int pa_bits)1799 static void virt_set_high_memmap(VirtMachineState *vms,
1800 hwaddr base, int pa_bits)
1801 {
1802 hwaddr region_base, region_size;
1803 bool *region_enabled, fits;
1804 int i;
1805
1806 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1807 region_enabled = virt_get_high_memmap_enabled(vms, i);
1808 region_base = ROUND_UP(base, extended_memmap[i].size);
1809 region_size = extended_memmap[i].size;
1810
1811 vms->memmap[i].base = region_base;
1812 vms->memmap[i].size = region_size;
1813
1814 /*
1815 * Check each device to see if it fits in the PA space,
1816 * moving highest_gpa as we go. For compatibility, move
1817 * highest_gpa for disabled fitting devices as well, if
1818 * the compact layout has been disabled.
1819 *
1820 * For each device that doesn't fit, disable it.
1821 */
1822 fits = (region_base + region_size) <= BIT_ULL(pa_bits);
1823 *region_enabled &= fits;
1824 if (vms->highmem_compact && !*region_enabled) {
1825 continue;
1826 }
1827
1828 base = region_base + region_size;
1829 if (fits) {
1830 vms->highest_gpa = base - 1;
1831 }
1832 }
1833 }
1834
virt_set_memmap(VirtMachineState * vms,int pa_bits)1835 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
1836 {
1837 MachineState *ms = MACHINE(vms);
1838 hwaddr base, device_memory_base, device_memory_size, memtop;
1839 int i;
1840
1841 vms->memmap = extended_memmap;
1842
1843 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1844 vms->memmap[i] = base_memmap[i];
1845 }
1846
1847 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1848 error_report("unsupported number of memory slots: %"PRIu64,
1849 ms->ram_slots);
1850 exit(EXIT_FAILURE);
1851 }
1852
1853 /*
1854 * !highmem is exactly the same as limiting the PA space to 32bit,
1855 * irrespective of the underlying capabilities of the HW.
1856 */
1857 if (!vms->highmem) {
1858 pa_bits = 32;
1859 }
1860
1861 /*
1862 * We compute the base of the high IO region depending on the
1863 * amount of initial and device memory. The device memory start/size
1864 * is aligned on 1GiB. We never put the high IO region below 256GiB
1865 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1866 * The device region size assumes 1GiB page max alignment per slot.
1867 */
1868 device_memory_base =
1869 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1870 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1871
1872 /* Base address of the high IO region */
1873 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1874 if (memtop > BIT_ULL(pa_bits)) {
1875 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
1876 pa_bits, memtop - BIT_ULL(pa_bits));
1877 exit(EXIT_FAILURE);
1878 }
1879 if (base < device_memory_base) {
1880 error_report("maxmem/slots too huge");
1881 exit(EXIT_FAILURE);
1882 }
1883 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1884 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1885 }
1886
1887 /* We know for sure that at least the memory fits in the PA space */
1888 vms->highest_gpa = memtop - 1;
1889
1890 virt_set_high_memmap(vms, base, pa_bits);
1891
1892 if (device_memory_size > 0) {
1893 machine_memory_devices_init(ms, device_memory_base, device_memory_size);
1894 }
1895 }
1896
finalize_gic_version_do(const char * accel_name,VirtGICType gic_version,int gics_supported,unsigned int max_cpus)1897 static VirtGICType finalize_gic_version_do(const char *accel_name,
1898 VirtGICType gic_version,
1899 int gics_supported,
1900 unsigned int max_cpus)
1901 {
1902 /* Convert host/max/nosel to GIC version number */
1903 switch (gic_version) {
1904 case VIRT_GIC_VERSION_HOST:
1905 if (!kvm_enabled()) {
1906 error_report("gic-version=host requires KVM");
1907 exit(1);
1908 }
1909
1910 /* For KVM, gic-version=host means gic-version=max */
1911 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
1912 gics_supported, max_cpus);
1913 case VIRT_GIC_VERSION_MAX:
1914 if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
1915 gic_version = VIRT_GIC_VERSION_4;
1916 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1917 gic_version = VIRT_GIC_VERSION_3;
1918 } else {
1919 gic_version = VIRT_GIC_VERSION_2;
1920 }
1921 break;
1922 case VIRT_GIC_VERSION_NOSEL:
1923 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
1924 max_cpus <= GIC_NCPU) {
1925 gic_version = VIRT_GIC_VERSION_2;
1926 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1927 /*
1928 * in case the host does not support v2 emulation or
1929 * the end-user requested more than 8 VCPUs we now default
1930 * to v3. In any case defaulting to v2 would be broken.
1931 */
1932 gic_version = VIRT_GIC_VERSION_3;
1933 } else if (max_cpus > GIC_NCPU) {
1934 error_report("%s only supports GICv2 emulation but more than 8 "
1935 "vcpus are requested", accel_name);
1936 exit(1);
1937 }
1938 break;
1939 case VIRT_GIC_VERSION_2:
1940 case VIRT_GIC_VERSION_3:
1941 case VIRT_GIC_VERSION_4:
1942 break;
1943 }
1944
1945 /* Check chosen version is effectively supported */
1946 switch (gic_version) {
1947 case VIRT_GIC_VERSION_2:
1948 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
1949 error_report("%s does not support GICv2 emulation", accel_name);
1950 exit(1);
1951 }
1952 break;
1953 case VIRT_GIC_VERSION_3:
1954 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
1955 error_report("%s does not support GICv3 emulation", accel_name);
1956 exit(1);
1957 }
1958 break;
1959 case VIRT_GIC_VERSION_4:
1960 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
1961 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1962 accel_name);
1963 exit(1);
1964 }
1965 break;
1966 default:
1967 error_report("logic error in finalize_gic_version");
1968 exit(1);
1969 break;
1970 }
1971
1972 return gic_version;
1973 }
1974
1975 /*
1976 * finalize_gic_version - Determines the final gic_version
1977 * according to the gic-version property
1978 *
1979 * Default GIC type is v2
1980 */
finalize_gic_version(VirtMachineState * vms)1981 static void finalize_gic_version(VirtMachineState *vms)
1982 {
1983 const char *accel_name = current_accel_name();
1984 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1985 int gics_supported = 0;
1986
1987 /* Determine which GIC versions the current environment supports */
1988 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1989 int probe_bitmap = kvm_arm_vgic_probe();
1990
1991 if (!probe_bitmap) {
1992 error_report("Unable to determine GIC version supported by host");
1993 exit(1);
1994 }
1995
1996 if (probe_bitmap & KVM_ARM_VGIC_V2) {
1997 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1998 }
1999 if (probe_bitmap & KVM_ARM_VGIC_V3) {
2000 gics_supported |= VIRT_GIC_VERSION_3_MASK;
2001 }
2002 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
2003 /* KVM w/o kernel irqchip can only deal with GICv2 */
2004 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2005 accel_name = "KVM with kernel-irqchip=off";
2006 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
2007 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2008 if (module_object_class_by_name("arm-gicv3")) {
2009 gics_supported |= VIRT_GIC_VERSION_3_MASK;
2010 if (vms->virt) {
2011 /* GICv4 only makes sense if CPU has EL2 */
2012 gics_supported |= VIRT_GIC_VERSION_4_MASK;
2013 }
2014 }
2015 } else {
2016 error_report("Unsupported accelerator, can not determine GIC support");
2017 exit(1);
2018 }
2019
2020 /*
2021 * Then convert helpers like host/max to concrete GIC versions and ensure
2022 * the desired version is supported
2023 */
2024 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
2025 gics_supported, max_cpus);
2026 }
2027
2028 /*
2029 * virt_post_cpus_gic_realized() must be called after the CPUs and
2030 * the GIC have both been realized.
2031 */
virt_post_cpus_gic_realized(VirtMachineState * vms,MemoryRegion * sysmem)2032 static void virt_post_cpus_gic_realized(VirtMachineState *vms,
2033 MemoryRegion *sysmem)
2034 {
2035 int max_cpus = MACHINE(vms)->smp.max_cpus;
2036 bool aarch64, pmu, steal_time;
2037 CPUState *cpu;
2038
2039 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
2040 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
2041 steal_time = object_property_get_bool(OBJECT(first_cpu),
2042 "kvm-steal-time", NULL);
2043
2044 if (kvm_enabled()) {
2045 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
2046 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
2047
2048 if (steal_time) {
2049 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
2050 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
2051
2052 /* The memory region size must be a multiple of host page size. */
2053 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
2054
2055 if (pvtime_size > pvtime_reg_size) {
2056 error_report("pvtime requires a %" HWADDR_PRId
2057 " byte memory region for %d CPUs,"
2058 " but only %" HWADDR_PRId " has been reserved",
2059 pvtime_size, max_cpus, pvtime_reg_size);
2060 exit(1);
2061 }
2062
2063 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
2064 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
2065 }
2066
2067 CPU_FOREACH(cpu) {
2068 if (pmu) {
2069 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
2070 if (kvm_irqchip_in_kernel()) {
2071 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ);
2072 }
2073 kvm_arm_pmu_init(ARM_CPU(cpu));
2074 }
2075 if (steal_time) {
2076 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base
2077 + cpu->cpu_index
2078 * PVTIME_SIZE_PER_CPU);
2079 }
2080 }
2081 } else {
2082 if (aarch64 && vms->highmem) {
2083 int requested_pa_size = 64 - clz64(vms->highest_gpa);
2084 int pamax = arm_pamax(ARM_CPU(first_cpu));
2085
2086 if (pamax < requested_pa_size) {
2087 error_report("VCPU supports less PA bits (%d) than "
2088 "requested by the memory map (%d)",
2089 pamax, requested_pa_size);
2090 exit(1);
2091 }
2092 }
2093 }
2094 }
2095
machvirt_init(MachineState * machine)2096 static void machvirt_init(MachineState *machine)
2097 {
2098 VirtMachineState *vms = VIRT_MACHINE(machine);
2099 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
2100 MachineClass *mc = MACHINE_GET_CLASS(machine);
2101 const CPUArchIdList *possible_cpus;
2102 MemoryRegion *sysmem = get_system_memory();
2103 MemoryRegion *secure_sysmem = NULL;
2104 MemoryRegion *tag_sysmem = NULL;
2105 MemoryRegion *secure_tag_sysmem = NULL;
2106 int n, virt_max_cpus;
2107 bool firmware_loaded;
2108 bool aarch64 = true;
2109 bool has_ged = !vmc->no_ged;
2110 unsigned int smp_cpus = machine->smp.cpus;
2111 unsigned int max_cpus = machine->smp.max_cpus;
2112
2113 possible_cpus = mc->possible_cpu_arch_ids(machine);
2114
2115 /*
2116 * In accelerated mode, the memory map is computed earlier in kvm_type()
2117 * for Linux, or hvf_get_physical_address_range() for macOS to create a
2118 * VM with the right number of IPA bits.
2119 */
2120 if (!vms->memmap) {
2121 Object *cpuobj;
2122 ARMCPU *armcpu;
2123 int pa_bits;
2124
2125 /*
2126 * Instantiate a temporary CPU object to find out about what
2127 * we are about to deal with. Once this is done, get rid of
2128 * the object.
2129 */
2130 cpuobj = object_new(possible_cpus->cpus[0].type);
2131 armcpu = ARM_CPU(cpuobj);
2132
2133 pa_bits = arm_pamax(armcpu);
2134
2135 object_unref(cpuobj);
2136
2137 virt_set_memmap(vms, pa_bits);
2138 }
2139
2140 /* We can probe only here because during property set
2141 * KVM is not available yet
2142 */
2143 finalize_gic_version(vms);
2144
2145 if (vms->secure) {
2146 /*
2147 * The Secure view of the world is the same as the NonSecure,
2148 * but with a few extra devices. Create it as a container region
2149 * containing the system memory at low priority; any secure-only
2150 * devices go in at higher priority and take precedence.
2151 */
2152 secure_sysmem = g_new(MemoryRegion, 1);
2153 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2154 UINT64_MAX);
2155 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2156 }
2157
2158 firmware_loaded = virt_firmware_init(vms, sysmem,
2159 secure_sysmem ?: sysmem);
2160
2161 /* If we have an EL3 boot ROM then the assumption is that it will
2162 * implement PSCI itself, so disable QEMU's internal implementation
2163 * so it doesn't get in the way. Instead of starting secondary
2164 * CPUs in PSCI powerdown state we will start them all running and
2165 * let the boot ROM sort them out.
2166 * The usual case is that we do use QEMU's PSCI implementation;
2167 * if the guest has EL2 then we will use SMC as the conduit,
2168 * and otherwise we will use HVC (for backwards compatibility and
2169 * because if we're using KVM then we must use HVC).
2170 */
2171 if (vms->secure && firmware_loaded) {
2172 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2173 } else if (vms->virt) {
2174 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2175 } else {
2176 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2177 }
2178
2179 /*
2180 * The maximum number of CPUs depends on the GIC version, or on how
2181 * many redistributors we can fit into the memory map (which in turn
2182 * depends on whether this is a GICv3 or v4).
2183 */
2184 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2185 virt_max_cpus = GIC_NCPU;
2186 } else {
2187 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
2188 if (vms->highmem_redists) {
2189 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2190 }
2191 }
2192
2193 if (max_cpus > virt_max_cpus) {
2194 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2195 "supported by machine 'mach-virt' (%d)",
2196 max_cpus, virt_max_cpus);
2197 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2198 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2199 }
2200
2201 exit(1);
2202 }
2203
2204 if (vms->secure && !tcg_enabled() && !qtest_enabled()) {
2205 error_report("mach-virt: %s does not support providing "
2206 "Security extensions (TrustZone) to the guest CPU",
2207 current_accel_name());
2208 exit(1);
2209 }
2210
2211 if (vms->virt && !tcg_enabled() && !qtest_enabled()) {
2212 error_report("mach-virt: %s does not support providing "
2213 "Virtualization extensions to the guest CPU",
2214 current_accel_name());
2215 exit(1);
2216 }
2217
2218 if (vms->mte && hvf_enabled()) {
2219 error_report("mach-virt: %s does not support providing "
2220 "MTE to the guest CPU",
2221 current_accel_name());
2222 exit(1);
2223 }
2224
2225 create_fdt(vms);
2226
2227 assert(possible_cpus->len == max_cpus);
2228 for (n = 0; n < possible_cpus->len; n++) {
2229 Object *cpuobj;
2230 CPUState *cs;
2231
2232 if (n >= smp_cpus) {
2233 break;
2234 }
2235
2236 cpuobj = object_new(possible_cpus->cpus[n].type);
2237 object_property_set_int(cpuobj, "mp-affinity",
2238 possible_cpus->cpus[n].arch_id, NULL);
2239
2240 cs = CPU(cpuobj);
2241 cs->cpu_index = n;
2242
2243 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2244 &error_fatal);
2245
2246 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2247
2248 if (!vms->secure) {
2249 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2250 }
2251
2252 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2253 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2254 }
2255
2256 if (vmc->kvm_no_adjvtime &&
2257 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2258 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2259 }
2260
2261 if (vmc->no_kvm_steal_time &&
2262 object_property_find(cpuobj, "kvm-steal-time")) {
2263 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2264 }
2265
2266 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2267 object_property_set_bool(cpuobj, "lpa2", false, NULL);
2268 }
2269
2270 if (object_property_find(cpuobj, "reset-cbar")) {
2271 object_property_set_int(cpuobj, "reset-cbar",
2272 vms->memmap[VIRT_CPUPERIPHS].base,
2273 &error_abort);
2274 }
2275
2276 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2277 &error_abort);
2278 if (vms->secure) {
2279 object_property_set_link(cpuobj, "secure-memory",
2280 OBJECT(secure_sysmem), &error_abort);
2281 }
2282
2283 if (vms->mte) {
2284 if (tcg_enabled()) {
2285 /* Create the memory region only once, but link to all cpus. */
2286 if (!tag_sysmem) {
2287 /*
2288 * The property exists only if MemTag is supported.
2289 * If it is, we must allocate the ram to back that up.
2290 */
2291 if (!object_property_find(cpuobj, "tag-memory")) {
2292 error_report("MTE requested, but not supported "
2293 "by the guest CPU");
2294 exit(1);
2295 }
2296
2297 tag_sysmem = g_new(MemoryRegion, 1);
2298 memory_region_init(tag_sysmem, OBJECT(machine),
2299 "tag-memory", UINT64_MAX / 32);
2300
2301 if (vms->secure) {
2302 secure_tag_sysmem = g_new(MemoryRegion, 1);
2303 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2304 "secure-tag-memory",
2305 UINT64_MAX / 32);
2306
2307 /* As with ram, secure-tag takes precedence over tag. */
2308 memory_region_add_subregion_overlap(secure_tag_sysmem,
2309 0, tag_sysmem, -1);
2310 }
2311 }
2312
2313 object_property_set_link(cpuobj, "tag-memory",
2314 OBJECT(tag_sysmem), &error_abort);
2315 if (vms->secure) {
2316 object_property_set_link(cpuobj, "secure-tag-memory",
2317 OBJECT(secure_tag_sysmem),
2318 &error_abort);
2319 }
2320 } else if (kvm_enabled()) {
2321 if (!kvm_arm_mte_supported()) {
2322 error_report("MTE requested, but not supported by KVM");
2323 exit(1);
2324 }
2325 kvm_arm_enable_mte(cpuobj, &error_abort);
2326 } else {
2327 error_report("MTE requested, but not supported ");
2328 exit(1);
2329 }
2330 }
2331
2332 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2333 object_unref(cpuobj);
2334 }
2335
2336 /* Now we've created the CPUs we can see if they have the hypvirt timer */
2337 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
2338 !vmc->no_ns_el2_virt_timer_irq;
2339
2340 fdt_add_timer_nodes(vms);
2341 fdt_add_cpu_nodes(vms);
2342
2343 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2344 machine->ram);
2345
2346 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2347
2348 create_gic(vms, sysmem);
2349
2350 virt_post_cpus_gic_realized(vms, sysmem);
2351
2352 fdt_add_pmu_nodes(vms);
2353
2354 /*
2355 * The first UART always exists. If the security extensions are
2356 * enabled, the second UART also always exists. Otherwise, it only exists
2357 * if a backend is configured explicitly via '-serial <backend>'.
2358 * This avoids potentially breaking existing user setups that expect
2359 * only one NonSecure UART to be present (for instance, older EDK2
2360 * binaries).
2361 *
2362 * The nodes end up in the DTB in reverse order of creation, so we must
2363 * create UART0 last to ensure it appears as the first node in the DTB,
2364 * for compatibility with guest software that just iterates through the
2365 * DTB to find the first UART, as older versions of EDK2 do.
2366 * DTB readers that follow the spec, as Linux does, should honour the
2367 * aliases node information and /chosen/stdout-path regardless of
2368 * the order that nodes appear in the DTB.
2369 *
2370 * For similar back-compatibility reasons, if UART1 is the secure UART
2371 * we create it second (and so it appears first in the DTB), because
2372 * that's what QEMU has always done.
2373 */
2374 if (!vms->secure) {
2375 Chardev *serial1 = serial_hd(1);
2376
2377 if (serial1) {
2378 vms->second_ns_uart_present = true;
2379 create_uart(vms, VIRT_UART1, sysmem, serial1, false);
2380 }
2381 }
2382 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false);
2383 if (vms->secure) {
2384 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true);
2385 }
2386
2387 if (vms->secure) {
2388 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2389 }
2390
2391 if (tag_sysmem) {
2392 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2393 machine->ram_size, "mach-virt.tag");
2394 }
2395
2396 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2397
2398 create_rtc(vms);
2399
2400 create_pcie(vms);
2401
2402 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2403 vms->acpi_dev = create_acpi_ged(vms);
2404 } else {
2405 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2406 }
2407
2408 if (vms->secure && !vmc->no_secure_gpio) {
2409 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2410 }
2411
2412 /* connect powerdown request */
2413 vms->powerdown_notifier.notify = virt_powerdown_req;
2414 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2415
2416 /* Create mmio transports, so the user can create virtio backends
2417 * (which will be automatically plugged in to the transports). If
2418 * no backend is created the transport will just sit harmlessly idle.
2419 */
2420 create_virtio_devices(vms);
2421
2422 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2423 rom_set_fw(vms->fw_cfg);
2424
2425 create_platform_bus(vms);
2426
2427 if (machine->nvdimms_state->is_enabled) {
2428 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2429 .space_id = AML_AS_SYSTEM_MEMORY,
2430 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2431 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2432 };
2433
2434 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2435 arm_virt_nvdimm_acpi_dsmio,
2436 vms->fw_cfg, OBJECT(vms));
2437 }
2438
2439 vms->bootinfo.ram_size = machine->ram_size;
2440 vms->bootinfo.board_id = -1;
2441 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2442 vms->bootinfo.get_dtb = machvirt_dtb;
2443 vms->bootinfo.skip_dtb_autoload = true;
2444 vms->bootinfo.firmware_loaded = firmware_loaded;
2445 vms->bootinfo.psci_conduit = vms->psci_conduit;
2446 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2447
2448 vms->machine_done.notify = virt_machine_done;
2449 qemu_add_machine_init_done_notifier(&vms->machine_done);
2450 }
2451
virt_get_secure(Object * obj,Error ** errp)2452 static bool virt_get_secure(Object *obj, Error **errp)
2453 {
2454 VirtMachineState *vms = VIRT_MACHINE(obj);
2455
2456 return vms->secure;
2457 }
2458
virt_set_secure(Object * obj,bool value,Error ** errp)2459 static void virt_set_secure(Object *obj, bool value, Error **errp)
2460 {
2461 VirtMachineState *vms = VIRT_MACHINE(obj);
2462
2463 vms->secure = value;
2464 }
2465
virt_get_virt(Object * obj,Error ** errp)2466 static bool virt_get_virt(Object *obj, Error **errp)
2467 {
2468 VirtMachineState *vms = VIRT_MACHINE(obj);
2469
2470 return vms->virt;
2471 }
2472
virt_set_virt(Object * obj,bool value,Error ** errp)2473 static void virt_set_virt(Object *obj, bool value, Error **errp)
2474 {
2475 VirtMachineState *vms = VIRT_MACHINE(obj);
2476
2477 vms->virt = value;
2478 }
2479
virt_get_highmem(Object * obj,Error ** errp)2480 static bool virt_get_highmem(Object *obj, Error **errp)
2481 {
2482 VirtMachineState *vms = VIRT_MACHINE(obj);
2483
2484 return vms->highmem;
2485 }
2486
virt_set_highmem(Object * obj,bool value,Error ** errp)2487 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2488 {
2489 VirtMachineState *vms = VIRT_MACHINE(obj);
2490
2491 vms->highmem = value;
2492 }
2493
virt_get_compact_highmem(Object * obj,Error ** errp)2494 static bool virt_get_compact_highmem(Object *obj, Error **errp)
2495 {
2496 VirtMachineState *vms = VIRT_MACHINE(obj);
2497
2498 return vms->highmem_compact;
2499 }
2500
virt_set_compact_highmem(Object * obj,bool value,Error ** errp)2501 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
2502 {
2503 VirtMachineState *vms = VIRT_MACHINE(obj);
2504
2505 vms->highmem_compact = value;
2506 }
2507
virt_get_highmem_redists(Object * obj,Error ** errp)2508 static bool virt_get_highmem_redists(Object *obj, Error **errp)
2509 {
2510 VirtMachineState *vms = VIRT_MACHINE(obj);
2511
2512 return vms->highmem_redists;
2513 }
2514
virt_set_highmem_redists(Object * obj,bool value,Error ** errp)2515 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
2516 {
2517 VirtMachineState *vms = VIRT_MACHINE(obj);
2518
2519 vms->highmem_redists = value;
2520 }
2521
virt_get_highmem_ecam(Object * obj,Error ** errp)2522 static bool virt_get_highmem_ecam(Object *obj, Error **errp)
2523 {
2524 VirtMachineState *vms = VIRT_MACHINE(obj);
2525
2526 return vms->highmem_ecam;
2527 }
2528
virt_set_highmem_ecam(Object * obj,bool value,Error ** errp)2529 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
2530 {
2531 VirtMachineState *vms = VIRT_MACHINE(obj);
2532
2533 vms->highmem_ecam = value;
2534 }
2535
virt_get_highmem_mmio(Object * obj,Error ** errp)2536 static bool virt_get_highmem_mmio(Object *obj, Error **errp)
2537 {
2538 VirtMachineState *vms = VIRT_MACHINE(obj);
2539
2540 return vms->highmem_mmio;
2541 }
2542
virt_set_highmem_mmio(Object * obj,bool value,Error ** errp)2543 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
2544 {
2545 VirtMachineState *vms = VIRT_MACHINE(obj);
2546
2547 vms->highmem_mmio = value;
2548 }
2549
virt_get_highmem_mmio_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2550 static void virt_get_highmem_mmio_size(Object *obj, Visitor *v,
2551 const char *name, void *opaque,
2552 Error **errp)
2553 {
2554 uint64_t size = extended_memmap[VIRT_HIGH_PCIE_MMIO].size;
2555
2556 visit_type_size(v, name, &size, errp);
2557 }
2558
virt_set_highmem_mmio_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2559 static void virt_set_highmem_mmio_size(Object *obj, Visitor *v,
2560 const char *name, void *opaque,
2561 Error **errp)
2562 {
2563 uint64_t size;
2564
2565 if (!visit_type_size(v, name, &size, errp)) {
2566 return;
2567 }
2568
2569 if (!is_power_of_2(size)) {
2570 error_setg(errp, "highmem-mmio-size is not a power of 2");
2571 return;
2572 }
2573
2574 if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) {
2575 char *sz = size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE);
2576 error_setg(errp, "highmem-mmio-size cannot be set to a lower value "
2577 "than the default (%s)", sz);
2578 g_free(sz);
2579 return;
2580 }
2581
2582 extended_memmap[VIRT_HIGH_PCIE_MMIO].size = size;
2583 }
2584
virt_get_its(Object * obj,Error ** errp)2585 static bool virt_get_its(Object *obj, Error **errp)
2586 {
2587 VirtMachineState *vms = VIRT_MACHINE(obj);
2588
2589 return vms->its;
2590 }
2591
virt_set_its(Object * obj,bool value,Error ** errp)2592 static void virt_set_its(Object *obj, bool value, Error **errp)
2593 {
2594 VirtMachineState *vms = VIRT_MACHINE(obj);
2595
2596 vms->its = value;
2597 }
2598
virt_get_dtb_randomness(Object * obj,Error ** errp)2599 static bool virt_get_dtb_randomness(Object *obj, Error **errp)
2600 {
2601 VirtMachineState *vms = VIRT_MACHINE(obj);
2602
2603 return vms->dtb_randomness;
2604 }
2605
virt_set_dtb_randomness(Object * obj,bool value,Error ** errp)2606 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp)
2607 {
2608 VirtMachineState *vms = VIRT_MACHINE(obj);
2609
2610 vms->dtb_randomness = value;
2611 }
2612
virt_get_oem_id(Object * obj,Error ** errp)2613 static char *virt_get_oem_id(Object *obj, Error **errp)
2614 {
2615 VirtMachineState *vms = VIRT_MACHINE(obj);
2616
2617 return g_strdup(vms->oem_id);
2618 }
2619
virt_set_oem_id(Object * obj,const char * value,Error ** errp)2620 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2621 {
2622 VirtMachineState *vms = VIRT_MACHINE(obj);
2623 size_t len = strlen(value);
2624
2625 if (len > 6) {
2626 error_setg(errp,
2627 "User specified oem-id value is bigger than 6 bytes in size");
2628 return;
2629 }
2630
2631 strncpy(vms->oem_id, value, 6);
2632 }
2633
virt_get_oem_table_id(Object * obj,Error ** errp)2634 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2635 {
2636 VirtMachineState *vms = VIRT_MACHINE(obj);
2637
2638 return g_strdup(vms->oem_table_id);
2639 }
2640
virt_set_oem_table_id(Object * obj,const char * value,Error ** errp)2641 static void virt_set_oem_table_id(Object *obj, const char *value,
2642 Error **errp)
2643 {
2644 VirtMachineState *vms = VIRT_MACHINE(obj);
2645 size_t len = strlen(value);
2646
2647 if (len > 8) {
2648 error_setg(errp,
2649 "User specified oem-table-id value is bigger than 8 bytes in size");
2650 return;
2651 }
2652 strncpy(vms->oem_table_id, value, 8);
2653 }
2654
2655
virt_is_acpi_enabled(VirtMachineState * vms)2656 bool virt_is_acpi_enabled(VirtMachineState *vms)
2657 {
2658 if (vms->acpi == ON_OFF_AUTO_OFF) {
2659 return false;
2660 }
2661 return true;
2662 }
2663
virt_get_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2664 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2665 void *opaque, Error **errp)
2666 {
2667 VirtMachineState *vms = VIRT_MACHINE(obj);
2668 OnOffAuto acpi = vms->acpi;
2669
2670 visit_type_OnOffAuto(v, name, &acpi, errp);
2671 }
2672
virt_set_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2673 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2674 void *opaque, Error **errp)
2675 {
2676 VirtMachineState *vms = VIRT_MACHINE(obj);
2677
2678 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2679 }
2680
virt_get_ras(Object * obj,Error ** errp)2681 static bool virt_get_ras(Object *obj, Error **errp)
2682 {
2683 VirtMachineState *vms = VIRT_MACHINE(obj);
2684
2685 return vms->ras;
2686 }
2687
virt_set_ras(Object * obj,bool value,Error ** errp)2688 static void virt_set_ras(Object *obj, bool value, Error **errp)
2689 {
2690 VirtMachineState *vms = VIRT_MACHINE(obj);
2691
2692 vms->ras = value;
2693 }
2694
virt_get_mte(Object * obj,Error ** errp)2695 static bool virt_get_mte(Object *obj, Error **errp)
2696 {
2697 VirtMachineState *vms = VIRT_MACHINE(obj);
2698
2699 return vms->mte;
2700 }
2701
virt_set_mte(Object * obj,bool value,Error ** errp)2702 static void virt_set_mte(Object *obj, bool value, Error **errp)
2703 {
2704 VirtMachineState *vms = VIRT_MACHINE(obj);
2705
2706 vms->mte = value;
2707 }
2708
virt_get_gic_version(Object * obj,Error ** errp)2709 static char *virt_get_gic_version(Object *obj, Error **errp)
2710 {
2711 VirtMachineState *vms = VIRT_MACHINE(obj);
2712 const char *val;
2713
2714 switch (vms->gic_version) {
2715 case VIRT_GIC_VERSION_4:
2716 val = "4";
2717 break;
2718 case VIRT_GIC_VERSION_3:
2719 val = "3";
2720 break;
2721 default:
2722 val = "2";
2723 break;
2724 }
2725 return g_strdup(val);
2726 }
2727
virt_set_gic_version(Object * obj,const char * value,Error ** errp)2728 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2729 {
2730 VirtMachineState *vms = VIRT_MACHINE(obj);
2731
2732 if (!strcmp(value, "4")) {
2733 vms->gic_version = VIRT_GIC_VERSION_4;
2734 } else if (!strcmp(value, "3")) {
2735 vms->gic_version = VIRT_GIC_VERSION_3;
2736 } else if (!strcmp(value, "2")) {
2737 vms->gic_version = VIRT_GIC_VERSION_2;
2738 } else if (!strcmp(value, "host")) {
2739 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2740 } else if (!strcmp(value, "max")) {
2741 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2742 } else {
2743 error_setg(errp, "Invalid gic-version value");
2744 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2745 }
2746 }
2747
virt_get_iommu(Object * obj,Error ** errp)2748 static char *virt_get_iommu(Object *obj, Error **errp)
2749 {
2750 VirtMachineState *vms = VIRT_MACHINE(obj);
2751
2752 switch (vms->iommu) {
2753 case VIRT_IOMMU_NONE:
2754 return g_strdup("none");
2755 case VIRT_IOMMU_SMMUV3:
2756 return g_strdup("smmuv3");
2757 default:
2758 g_assert_not_reached();
2759 }
2760 }
2761
virt_set_iommu(Object * obj,const char * value,Error ** errp)2762 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2763 {
2764 VirtMachineState *vms = VIRT_MACHINE(obj);
2765
2766 if (!strcmp(value, "smmuv3")) {
2767 vms->iommu = VIRT_IOMMU_SMMUV3;
2768 } else if (!strcmp(value, "none")) {
2769 vms->iommu = VIRT_IOMMU_NONE;
2770 } else {
2771 error_setg(errp, "Invalid iommu value");
2772 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2773 }
2774 }
2775
virt_get_default_bus_bypass_iommu(Object * obj,Error ** errp)2776 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2777 {
2778 VirtMachineState *vms = VIRT_MACHINE(obj);
2779
2780 return vms->default_bus_bypass_iommu;
2781 }
2782
virt_set_default_bus_bypass_iommu(Object * obj,bool value,Error ** errp)2783 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2784 Error **errp)
2785 {
2786 VirtMachineState *vms = VIRT_MACHINE(obj);
2787
2788 vms->default_bus_bypass_iommu = value;
2789 }
2790
2791 static CpuInstanceProperties
virt_cpu_index_to_props(MachineState * ms,unsigned cpu_index)2792 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2793 {
2794 MachineClass *mc = MACHINE_GET_CLASS(ms);
2795 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2796
2797 assert(cpu_index < possible_cpus->len);
2798 return possible_cpus->cpus[cpu_index].props;
2799 }
2800
virt_get_default_cpu_node_id(const MachineState * ms,int idx)2801 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2802 {
2803 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2804
2805 return socket_id % ms->numa_state->num_nodes;
2806 }
2807
virt_possible_cpu_arch_ids(MachineState * ms)2808 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2809 {
2810 int n;
2811 unsigned int max_cpus = ms->smp.max_cpus;
2812 VirtMachineState *vms = VIRT_MACHINE(ms);
2813 MachineClass *mc = MACHINE_GET_CLASS(vms);
2814
2815 if (ms->possible_cpus) {
2816 assert(ms->possible_cpus->len == max_cpus);
2817 return ms->possible_cpus;
2818 }
2819
2820 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2821 sizeof(CPUArchId) * max_cpus);
2822 ms->possible_cpus->len = max_cpus;
2823 for (n = 0; n < ms->possible_cpus->len; n++) {
2824 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2825 ms->possible_cpus->cpus[n].arch_id =
2826 virt_cpu_mp_affinity(vms, n);
2827
2828 assert(!mc->smp_props.dies_supported);
2829 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2830 ms->possible_cpus->cpus[n].props.socket_id =
2831 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2832 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2833 ms->possible_cpus->cpus[n].props.cluster_id =
2834 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2835 ms->possible_cpus->cpus[n].props.has_core_id = true;
2836 ms->possible_cpus->cpus[n].props.core_id =
2837 (n / ms->smp.threads) % ms->smp.cores;
2838 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2839 ms->possible_cpus->cpus[n].props.thread_id =
2840 n % ms->smp.threads;
2841 }
2842 return ms->possible_cpus;
2843 }
2844
virt_memory_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2845 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2846 Error **errp)
2847 {
2848 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2849 const MachineState *ms = MACHINE(hotplug_dev);
2850 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2851
2852 if (!vms->acpi_dev) {
2853 error_setg(errp,
2854 "memory hotplug is not enabled: missing acpi-ged device");
2855 return;
2856 }
2857
2858 if (vms->mte) {
2859 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2860 return;
2861 }
2862
2863 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2864 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2865 return;
2866 }
2867
2868 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
2869 }
2870
virt_memory_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2871 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2872 DeviceState *dev, Error **errp)
2873 {
2874 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2875 MachineState *ms = MACHINE(hotplug_dev);
2876 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2877
2878 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2879
2880 if (is_nvdimm) {
2881 nvdimm_plug(ms->nvdimms_state);
2882 }
2883
2884 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2885 dev, &error_abort);
2886 }
2887
virt_machine_device_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2888 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2889 DeviceState *dev, Error **errp)
2890 {
2891 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2892
2893 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2894 virt_memory_pre_plug(hotplug_dev, dev, errp);
2895 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2896 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2897 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2898 hwaddr db_start = 0, db_end = 0;
2899 QList *reserved_regions;
2900 char *resv_prop_str;
2901
2902 if (vms->iommu != VIRT_IOMMU_NONE) {
2903 error_setg(errp, "virt machine does not support multiple IOMMUs");
2904 return;
2905 }
2906
2907 switch (vms->msi_controller) {
2908 case VIRT_MSI_CTRL_NONE:
2909 return;
2910 case VIRT_MSI_CTRL_ITS:
2911 /* GITS_TRANSLATER page */
2912 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2913 db_end = base_memmap[VIRT_GIC_ITS].base +
2914 base_memmap[VIRT_GIC_ITS].size - 1;
2915 break;
2916 case VIRT_MSI_CTRL_GICV2M:
2917 /* MSI_SETSPI_NS page */
2918 db_start = base_memmap[VIRT_GIC_V2M].base;
2919 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2920 break;
2921 }
2922 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2923 db_start, db_end,
2924 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2925
2926 reserved_regions = qlist_new();
2927 qlist_append_str(reserved_regions, resv_prop_str);
2928 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
2929 g_free(resv_prop_str);
2930 }
2931 }
2932
virt_machine_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2933 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2934 DeviceState *dev, Error **errp)
2935 {
2936 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2937
2938 if (vms->platform_bus_dev) {
2939 MachineClass *mc = MACHINE_GET_CLASS(vms);
2940
2941 if (device_is_dynamic_sysbus(mc, dev)) {
2942 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2943 SYS_BUS_DEVICE(dev));
2944 }
2945 }
2946
2947 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2948 virt_memory_plug(hotplug_dev, dev, errp);
2949 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2950 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2951 }
2952
2953 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2954 PCIDevice *pdev = PCI_DEVICE(dev);
2955
2956 vms->iommu = VIRT_IOMMU_VIRTIO;
2957 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2958 create_virtio_iommu_dt_bindings(vms);
2959 }
2960 }
2961
virt_dimm_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2962 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2963 DeviceState *dev, Error **errp)
2964 {
2965 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2966
2967 if (!vms->acpi_dev) {
2968 error_setg(errp,
2969 "memory hotplug is not enabled: missing acpi-ged device");
2970 return;
2971 }
2972
2973 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2974 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
2975 return;
2976 }
2977
2978 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2979 errp);
2980 }
2981
virt_dimm_unplug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2982 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2983 DeviceState *dev, Error **errp)
2984 {
2985 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2986 Error *local_err = NULL;
2987
2988 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2989 if (local_err) {
2990 goto out;
2991 }
2992
2993 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2994 qdev_unrealize(dev);
2995
2996 out:
2997 error_propagate(errp, local_err);
2998 }
2999
virt_machine_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3000 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
3001 DeviceState *dev, Error **errp)
3002 {
3003 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3004 virt_dimm_unplug_request(hotplug_dev, dev, errp);
3005 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
3006 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
3007 errp);
3008 } else {
3009 error_setg(errp, "device unplug request for unsupported device"
3010 " type: %s", object_get_typename(OBJECT(dev)));
3011 }
3012 }
3013
virt_machine_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3014 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
3015 DeviceState *dev, Error **errp)
3016 {
3017 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3018 virt_dimm_unplug(hotplug_dev, dev, errp);
3019 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
3020 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
3021 } else {
3022 error_setg(errp, "virt: device unplug for unsupported device"
3023 " type: %s", object_get_typename(OBJECT(dev)));
3024 }
3025 }
3026
virt_machine_get_hotplug_handler(MachineState * machine,DeviceState * dev)3027 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
3028 DeviceState *dev)
3029 {
3030 MachineClass *mc = MACHINE_GET_CLASS(machine);
3031
3032 if (device_is_dynamic_sysbus(mc, dev) ||
3033 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3034 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
3035 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
3036 return HOTPLUG_HANDLER(machine);
3037 }
3038 return NULL;
3039 }
3040
3041 /*
3042 * for arm64 kvm_type [7-0] encodes the requested number of bits
3043 * in the IPA address space
3044 */
virt_kvm_type(MachineState * ms,const char * type_str)3045 static int virt_kvm_type(MachineState *ms, const char *type_str)
3046 {
3047 VirtMachineState *vms = VIRT_MACHINE(ms);
3048 int max_vm_pa_size, requested_pa_size;
3049 bool fixed_ipa;
3050
3051 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
3052
3053 /* we freeze the memory map to compute the highest gpa */
3054 virt_set_memmap(vms, max_vm_pa_size);
3055
3056 requested_pa_size = 64 - clz64(vms->highest_gpa);
3057
3058 /*
3059 * KVM requires the IPA size to be at least 32 bits.
3060 */
3061 if (requested_pa_size < 32) {
3062 requested_pa_size = 32;
3063 }
3064
3065 if (requested_pa_size > max_vm_pa_size) {
3066 error_report("-m and ,maxmem option values "
3067 "require an IPA range (%d bits) larger than "
3068 "the one supported by the host (%d bits)",
3069 requested_pa_size, max_vm_pa_size);
3070 return -1;
3071 }
3072 /*
3073 * We return the requested PA log size, unless KVM only supports
3074 * the implicit legacy 40b IPA setting, in which case the kvm_type
3075 * must be 0.
3076 */
3077 return fixed_ipa ? 0 : requested_pa_size;
3078 }
3079
virt_hvf_get_physical_address_range(MachineState * ms)3080 static int virt_hvf_get_physical_address_range(MachineState *ms)
3081 {
3082 VirtMachineState *vms = VIRT_MACHINE(ms);
3083
3084 int default_ipa_size = hvf_arm_get_default_ipa_bit_size();
3085 int max_ipa_size = hvf_arm_get_max_ipa_bit_size();
3086
3087 /* We freeze the memory map to compute the highest gpa */
3088 virt_set_memmap(vms, max_ipa_size);
3089
3090 int requested_ipa_size = 64 - clz64(vms->highest_gpa);
3091
3092 /*
3093 * If we're <= the default IPA size just use the default.
3094 * If we're above the default but below the maximum, round up to
3095 * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only
3096 * returns values that are valid ARM PARange values.
3097 */
3098 if (requested_ipa_size <= default_ipa_size) {
3099 requested_ipa_size = default_ipa_size;
3100 } else if (requested_ipa_size <= max_ipa_size) {
3101 requested_ipa_size = max_ipa_size;
3102 } else {
3103 error_report("-m and ,maxmem option values "
3104 "require an IPA range (%d bits) larger than "
3105 "the one supported by the host (%d bits)",
3106 requested_ipa_size, max_ipa_size);
3107 return -1;
3108 }
3109
3110 return requested_ipa_size;
3111 }
3112
virt_machine_class_init(ObjectClass * oc,const void * data)3113 static void virt_machine_class_init(ObjectClass *oc, const void *data)
3114 {
3115 MachineClass *mc = MACHINE_CLASS(oc);
3116 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3117 static const char * const valid_cpu_types[] = {
3118 #ifdef CONFIG_TCG
3119 ARM_CPU_TYPE_NAME("cortex-a7"),
3120 ARM_CPU_TYPE_NAME("cortex-a15"),
3121 #ifdef TARGET_AARCH64
3122 ARM_CPU_TYPE_NAME("cortex-a35"),
3123 ARM_CPU_TYPE_NAME("cortex-a55"),
3124 ARM_CPU_TYPE_NAME("cortex-a72"),
3125 ARM_CPU_TYPE_NAME("cortex-a76"),
3126 ARM_CPU_TYPE_NAME("cortex-a710"),
3127 ARM_CPU_TYPE_NAME("a64fx"),
3128 ARM_CPU_TYPE_NAME("neoverse-n1"),
3129 ARM_CPU_TYPE_NAME("neoverse-v1"),
3130 ARM_CPU_TYPE_NAME("neoverse-n2"),
3131 #endif /* TARGET_AARCH64 */
3132 #endif /* CONFIG_TCG */
3133 #ifdef TARGET_AARCH64
3134 ARM_CPU_TYPE_NAME("cortex-a53"),
3135 ARM_CPU_TYPE_NAME("cortex-a57"),
3136 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3137 ARM_CPU_TYPE_NAME("host"),
3138 #endif /* CONFIG_KVM || CONFIG_HVF */
3139 #endif /* TARGET_AARCH64 */
3140 ARM_CPU_TYPE_NAME("max"),
3141 NULL
3142 };
3143
3144 mc->init = machvirt_init;
3145 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
3146 * The value may be reduced later when we have more information about the
3147 * configuration of the particular instance.
3148 */
3149 mc->max_cpus = 512;
3150 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
3151 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
3152 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
3153 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
3154 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS);
3155 #ifdef CONFIG_TPM
3156 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
3157 #endif
3158 mc->block_default_type = IF_VIRTIO;
3159 mc->no_cdrom = 1;
3160 mc->pci_allow_0_address = true;
3161 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3162 mc->minimum_page_bits = 12;
3163 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
3164 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
3165 #ifdef CONFIG_TCG
3166 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
3167 #else
3168 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
3169 #endif
3170 mc->valid_cpu_types = valid_cpu_types;
3171 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
3172 mc->kvm_type = virt_kvm_type;
3173 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
3174 assert(!mc->get_hotplug_handler);
3175 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
3176 hc->pre_plug = virt_machine_device_pre_plug_cb;
3177 hc->plug = virt_machine_device_plug_cb;
3178 hc->unplug_request = virt_machine_device_unplug_request_cb;
3179 hc->unplug = virt_machine_device_unplug_cb;
3180 mc->nvdimm_supported = true;
3181 mc->smp_props.clusters_supported = true;
3182 mc->auto_enable_numa_with_memhp = true;
3183 mc->auto_enable_numa_with_memdev = true;
3184 /* platform instead of architectural choice */
3185 mc->cpu_cluster_has_numa_boundary = true;
3186 mc->default_ram_id = "mach-virt.ram";
3187 mc->default_nic = "virtio-net-pci";
3188
3189 object_class_property_add(oc, "acpi", "OnOffAuto",
3190 virt_get_acpi, virt_set_acpi,
3191 NULL, NULL);
3192 object_class_property_set_description(oc, "acpi",
3193 "Enable ACPI");
3194 object_class_property_add_bool(oc, "secure", virt_get_secure,
3195 virt_set_secure);
3196 object_class_property_set_description(oc, "secure",
3197 "Set on/off to enable/disable the ARM "
3198 "Security Extensions (TrustZone)");
3199
3200 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
3201 virt_set_virt);
3202 object_class_property_set_description(oc, "virtualization",
3203 "Set on/off to enable/disable emulating a "
3204 "guest CPU which implements the ARM "
3205 "Virtualization Extensions");
3206
3207 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
3208 virt_set_highmem);
3209 object_class_property_set_description(oc, "highmem",
3210 "Set on/off to enable/disable using "
3211 "physical address space above 32 bits");
3212
3213 object_class_property_add_bool(oc, "compact-highmem",
3214 virt_get_compact_highmem,
3215 virt_set_compact_highmem);
3216 object_class_property_set_description(oc, "compact-highmem",
3217 "Set on/off to enable/disable compact "
3218 "layout for high memory regions");
3219
3220 object_class_property_add_bool(oc, "highmem-redists",
3221 virt_get_highmem_redists,
3222 virt_set_highmem_redists);
3223 object_class_property_set_description(oc, "highmem-redists",
3224 "Set on/off to enable/disable high "
3225 "memory region for GICv3 or GICv4 "
3226 "redistributor");
3227
3228 object_class_property_add_bool(oc, "highmem-ecam",
3229 virt_get_highmem_ecam,
3230 virt_set_highmem_ecam);
3231 object_class_property_set_description(oc, "highmem-ecam",
3232 "Set on/off to enable/disable high "
3233 "memory region for PCI ECAM");
3234
3235 object_class_property_add_bool(oc, "highmem-mmio",
3236 virt_get_highmem_mmio,
3237 virt_set_highmem_mmio);
3238 object_class_property_set_description(oc, "highmem-mmio",
3239 "Set on/off to enable/disable high "
3240 "memory region for PCI MMIO");
3241
3242 object_class_property_add(oc, "highmem-mmio-size", "size",
3243 virt_get_highmem_mmio_size,
3244 virt_set_highmem_mmio_size,
3245 NULL, NULL);
3246 object_class_property_set_description(oc, "highmem-mmio-size",
3247 "Set the high memory region size "
3248 "for PCI MMIO");
3249
3250 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3251 virt_set_gic_version);
3252 object_class_property_set_description(oc, "gic-version",
3253 "Set GIC version. "
3254 "Valid values are 2, 3, 4, host and max");
3255
3256 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
3257 object_class_property_set_description(oc, "iommu",
3258 "Set the IOMMU type. "
3259 "Valid values are none and smmuv3");
3260
3261 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3262 virt_get_default_bus_bypass_iommu,
3263 virt_set_default_bus_bypass_iommu);
3264 object_class_property_set_description(oc, "default-bus-bypass-iommu",
3265 "Set on/off to enable/disable "
3266 "bypass_iommu for default root bus");
3267
3268 object_class_property_add_bool(oc, "ras", virt_get_ras,
3269 virt_set_ras);
3270 object_class_property_set_description(oc, "ras",
3271 "Set on/off to enable/disable reporting host memory errors "
3272 "to a KVM guest using ACPI and guest external abort exceptions");
3273
3274 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
3275 object_class_property_set_description(oc, "mte",
3276 "Set on/off to enable/disable emulating a "
3277 "guest CPU which implements the ARM "
3278 "Memory Tagging Extension");
3279
3280 object_class_property_add_bool(oc, "its", virt_get_its,
3281 virt_set_its);
3282 object_class_property_set_description(oc, "its",
3283 "Set on/off to enable/disable "
3284 "ITS instantiation");
3285
3286 object_class_property_add_bool(oc, "dtb-randomness",
3287 virt_get_dtb_randomness,
3288 virt_set_dtb_randomness);
3289 object_class_property_set_description(oc, "dtb-randomness",
3290 "Set off to disable passing random or "
3291 "non-deterministic dtb nodes to guest");
3292
3293 object_class_property_add_bool(oc, "dtb-kaslr-seed",
3294 virt_get_dtb_randomness,
3295 virt_set_dtb_randomness);
3296 object_class_property_set_description(oc, "dtb-kaslr-seed",
3297 "Deprecated synonym of dtb-randomness");
3298
3299 object_class_property_add_str(oc, "x-oem-id",
3300 virt_get_oem_id,
3301 virt_set_oem_id);
3302 object_class_property_set_description(oc, "x-oem-id",
3303 "Override the default value of field OEMID "
3304 "in ACPI table header."
3305 "The string may be up to 6 bytes in size");
3306
3307
3308 object_class_property_add_str(oc, "x-oem-table-id",
3309 virt_get_oem_table_id,
3310 virt_set_oem_table_id);
3311 object_class_property_set_description(oc, "x-oem-table-id",
3312 "Override the default value of field OEM Table ID "
3313 "in ACPI table header."
3314 "The string may be up to 8 bytes in size");
3315
3316 }
3317
virt_instance_init(Object * obj)3318 static void virt_instance_init(Object *obj)
3319 {
3320 VirtMachineState *vms = VIRT_MACHINE(obj);
3321 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
3322
3323 /* EL3 is disabled by default on virt: this makes us consistent
3324 * between KVM and TCG for this board, and it also allows us to
3325 * boot UEFI blobs which assume no TrustZone support.
3326 */
3327 vms->secure = false;
3328
3329 /* EL2 is also disabled by default, for similar reasons */
3330 vms->virt = false;
3331
3332 /* High memory is enabled by default */
3333 vms->highmem = true;
3334 vms->highmem_compact = !vmc->no_highmem_compact;
3335 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3336
3337 vms->highmem_ecam = true;
3338 vms->highmem_mmio = true;
3339 vms->highmem_redists = true;
3340
3341 /* Default allows ITS instantiation */
3342 vms->its = true;
3343 /* Allow ITS emulation if the machine version supports it */
3344 vms->tcg_its = !vmc->no_tcg_its;
3345
3346 /* Default disallows iommu instantiation */
3347 vms->iommu = VIRT_IOMMU_NONE;
3348
3349 /* The default root bus is attached to iommu by default */
3350 vms->default_bus_bypass_iommu = false;
3351
3352 /* Default disallows RAS instantiation */
3353 vms->ras = false;
3354
3355 /* MTE is disabled by default. */
3356 vms->mte = false;
3357
3358 /* Supply kaslr-seed and rng-seed by default */
3359 vms->dtb_randomness = true;
3360
3361 vms->irqmap = a15irqmap;
3362
3363 virt_flash_create(vms);
3364
3365 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3366 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3367 }
3368
3369 static const TypeInfo virt_machine_info = {
3370 .name = TYPE_VIRT_MACHINE,
3371 .parent = TYPE_MACHINE,
3372 .abstract = true,
3373 .instance_size = sizeof(VirtMachineState),
3374 .class_size = sizeof(VirtMachineClass),
3375 .class_init = virt_machine_class_init,
3376 .instance_init = virt_instance_init,
3377 .interfaces = (const InterfaceInfo[]) {
3378 { TYPE_HOTPLUG_HANDLER },
3379 { }
3380 },
3381 };
3382
machvirt_machine_init(void)3383 static void machvirt_machine_init(void)
3384 {
3385 type_register_static(&virt_machine_info);
3386 }
3387 type_init(machvirt_machine_init);
3388
virt_machine_10_1_options(MachineClass * mc)3389 static void virt_machine_10_1_options(MachineClass *mc)
3390 {
3391 }
3392 DEFINE_VIRT_MACHINE_AS_LATEST(10, 1)
3393
virt_machine_10_0_options(MachineClass * mc)3394 static void virt_machine_10_0_options(MachineClass *mc)
3395 {
3396 virt_machine_10_1_options(mc);
3397 compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len);
3398 }
3399 DEFINE_VIRT_MACHINE(10, 0)
3400
virt_machine_9_2_options(MachineClass * mc)3401 static void virt_machine_9_2_options(MachineClass *mc)
3402 {
3403 virt_machine_10_0_options(mc);
3404 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len);
3405 }
3406 DEFINE_VIRT_MACHINE(9, 2)
3407
virt_machine_9_1_options(MachineClass * mc)3408 static void virt_machine_9_1_options(MachineClass *mc)
3409 {
3410 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3411
3412 virt_machine_9_2_options(mc);
3413 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len);
3414 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */
3415 vmc->no_nested_smmu = true;
3416 }
3417 DEFINE_VIRT_MACHINE(9, 1)
3418
virt_machine_9_0_options(MachineClass * mc)3419 static void virt_machine_9_0_options(MachineClass *mc)
3420 {
3421 virt_machine_9_1_options(mc);
3422 mc->smbios_memory_device_size = 16 * GiB;
3423 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len);
3424 }
3425 DEFINE_VIRT_MACHINE(9, 0)
3426
virt_machine_8_2_options(MachineClass * mc)3427 static void virt_machine_8_2_options(MachineClass *mc)
3428 {
3429 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3430
3431 virt_machine_9_0_options(mc);
3432 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
3433 /*
3434 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
3435 * earlier machines. (Exposing it tickles a bug in older EDK2
3436 * guest BIOS binaries.)
3437 */
3438 vmc->no_ns_el2_virt_timer_irq = true;
3439 }
3440 DEFINE_VIRT_MACHINE(8, 2)
3441
virt_machine_8_1_options(MachineClass * mc)3442 static void virt_machine_8_1_options(MachineClass *mc)
3443 {
3444 virt_machine_8_2_options(mc);
3445 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
3446 }
3447 DEFINE_VIRT_MACHINE(8, 1)
3448
virt_machine_8_0_options(MachineClass * mc)3449 static void virt_machine_8_0_options(MachineClass *mc)
3450 {
3451 virt_machine_8_1_options(mc);
3452 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3453 }
3454 DEFINE_VIRT_MACHINE(8, 0)
3455
virt_machine_7_2_options(MachineClass * mc)3456 static void virt_machine_7_2_options(MachineClass *mc)
3457 {
3458 virt_machine_8_0_options(mc);
3459 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3460 }
3461 DEFINE_VIRT_MACHINE(7, 2)
3462
virt_machine_7_1_options(MachineClass * mc)3463 static void virt_machine_7_1_options(MachineClass *mc)
3464 {
3465 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3466
3467 virt_machine_7_2_options(mc);
3468 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3469 /* Compact layout for high memory regions was introduced with 7.2 */
3470 vmc->no_highmem_compact = true;
3471 }
3472 DEFINE_VIRT_MACHINE(7, 1)
3473
virt_machine_7_0_options(MachineClass * mc)3474 static void virt_machine_7_0_options(MachineClass *mc)
3475 {
3476 virt_machine_7_1_options(mc);
3477 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3478 }
3479 DEFINE_VIRT_MACHINE(7, 0)
3480
virt_machine_6_2_options(MachineClass * mc)3481 static void virt_machine_6_2_options(MachineClass *mc)
3482 {
3483 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3484
3485 virt_machine_7_0_options(mc);
3486 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3487 vmc->no_tcg_lpa2 = true;
3488 }
3489 DEFINE_VIRT_MACHINE(6, 2)
3490
virt_machine_6_1_options(MachineClass * mc)3491 static void virt_machine_6_1_options(MachineClass *mc)
3492 {
3493 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3494
3495 virt_machine_6_2_options(mc);
3496 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3497 mc->smp_props.prefer_sockets = true;
3498 vmc->no_cpu_topology = true;
3499
3500 /* qemu ITS was introduced with 6.2 */
3501 vmc->no_tcg_its = true;
3502 }
3503 DEFINE_VIRT_MACHINE(6, 1)
3504
virt_machine_6_0_options(MachineClass * mc)3505 static void virt_machine_6_0_options(MachineClass *mc)
3506 {
3507 virt_machine_6_1_options(mc);
3508 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3509 }
3510 DEFINE_VIRT_MACHINE(6, 0)
3511
virt_machine_5_2_options(MachineClass * mc)3512 static void virt_machine_5_2_options(MachineClass *mc)
3513 {
3514 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3515
3516 virt_machine_6_0_options(mc);
3517 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3518 vmc->no_secure_gpio = true;
3519 }
3520 DEFINE_VIRT_MACHINE(5, 2)
3521
virt_machine_5_1_options(MachineClass * mc)3522 static void virt_machine_5_1_options(MachineClass *mc)
3523 {
3524 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3525
3526 virt_machine_5_2_options(mc);
3527 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3528 vmc->no_kvm_steal_time = true;
3529 }
3530 DEFINE_VIRT_MACHINE(5, 1)
3531
virt_machine_5_0_options(MachineClass * mc)3532 static void virt_machine_5_0_options(MachineClass *mc)
3533 {
3534 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3535
3536 virt_machine_5_1_options(mc);
3537 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3538 mc->numa_mem_supported = true;
3539 vmc->acpi_expose_flash = true;
3540 mc->auto_enable_numa_with_memdev = false;
3541 }
3542 DEFINE_VIRT_MACHINE(5, 0)
3543
virt_machine_4_2_options(MachineClass * mc)3544 static void virt_machine_4_2_options(MachineClass *mc)
3545 {
3546 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3547
3548 virt_machine_5_0_options(mc);
3549 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3550 vmc->kvm_no_adjvtime = true;
3551 }
3552 DEFINE_VIRT_MACHINE(4, 2)
3553
virt_machine_4_1_options(MachineClass * mc)3554 static void virt_machine_4_1_options(MachineClass *mc)
3555 {
3556 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3557
3558 virt_machine_4_2_options(mc);
3559 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3560 vmc->no_ged = true;
3561 mc->auto_enable_numa_with_memhp = false;
3562 }
3563 DEFINE_VIRT_MACHINE(4, 1)
3564