1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "hw/sysbus.h" 25 #include "hw/arm/arm.h" 26 #include "hw/arm/primecell.h" 27 #include "hw/devices.h" 28 #include "net/net.h" 29 #include "sysemu/sysemu.h" 30 #include "hw/boards.h" 31 #include "hw/loader.h" 32 #include "exec/address-spaces.h" 33 #include "sysemu/block-backend.h" 34 #include "hw/block/flash.h" 35 #include "sysemu/device_tree.h" 36 #include "qemu/error-report.h" 37 #include <libfdt.h> 38 39 #define VEXPRESS_BOARD_ID 0x8e0 40 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 41 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 42 43 /* Number of virtio transports to create (0..8; limited by 44 * number of available IRQ lines). 45 */ 46 #define NUM_VIRTIO_TRANSPORTS 4 47 48 /* Address maps for peripherals: 49 * the Versatile Express motherboard has two possible maps, 50 * the "legacy" one (used for A9) and the "Cortex-A Series" 51 * map (used for newer cores). 52 * Individual daughterboards can also have different maps for 53 * their peripherals. 54 */ 55 56 enum { 57 VE_SYSREGS, 58 VE_SP810, 59 VE_SERIALPCI, 60 VE_PL041, 61 VE_MMCI, 62 VE_KMI0, 63 VE_KMI1, 64 VE_UART0, 65 VE_UART1, 66 VE_UART2, 67 VE_UART3, 68 VE_WDT, 69 VE_TIMER01, 70 VE_TIMER23, 71 VE_SERIALDVI, 72 VE_RTC, 73 VE_COMPACTFLASH, 74 VE_CLCD, 75 VE_NORFLASH0, 76 VE_NORFLASH1, 77 VE_NORFLASHALIAS, 78 VE_SRAM, 79 VE_VIDEORAM, 80 VE_ETHERNET, 81 VE_USB, 82 VE_DAPROM, 83 VE_VIRTIO, 84 }; 85 86 static hwaddr motherboard_legacy_map[] = { 87 [VE_NORFLASHALIAS] = 0, 88 /* CS7: 0x10000000 .. 0x10020000 */ 89 [VE_SYSREGS] = 0x10000000, 90 [VE_SP810] = 0x10001000, 91 [VE_SERIALPCI] = 0x10002000, 92 [VE_PL041] = 0x10004000, 93 [VE_MMCI] = 0x10005000, 94 [VE_KMI0] = 0x10006000, 95 [VE_KMI1] = 0x10007000, 96 [VE_UART0] = 0x10009000, 97 [VE_UART1] = 0x1000a000, 98 [VE_UART2] = 0x1000b000, 99 [VE_UART3] = 0x1000c000, 100 [VE_WDT] = 0x1000f000, 101 [VE_TIMER01] = 0x10011000, 102 [VE_TIMER23] = 0x10012000, 103 [VE_VIRTIO] = 0x10013000, 104 [VE_SERIALDVI] = 0x10016000, 105 [VE_RTC] = 0x10017000, 106 [VE_COMPACTFLASH] = 0x1001a000, 107 [VE_CLCD] = 0x1001f000, 108 /* CS0: 0x40000000 .. 0x44000000 */ 109 [VE_NORFLASH0] = 0x40000000, 110 /* CS1: 0x44000000 .. 0x48000000 */ 111 [VE_NORFLASH1] = 0x44000000, 112 /* CS2: 0x48000000 .. 0x4a000000 */ 113 [VE_SRAM] = 0x48000000, 114 /* CS3: 0x4c000000 .. 0x50000000 */ 115 [VE_VIDEORAM] = 0x4c000000, 116 [VE_ETHERNET] = 0x4e000000, 117 [VE_USB] = 0x4f000000, 118 }; 119 120 static hwaddr motherboard_aseries_map[] = { 121 [VE_NORFLASHALIAS] = 0, 122 /* CS0: 0x08000000 .. 0x0c000000 */ 123 [VE_NORFLASH0] = 0x08000000, 124 /* CS4: 0x0c000000 .. 0x10000000 */ 125 [VE_NORFLASH1] = 0x0c000000, 126 /* CS5: 0x10000000 .. 0x14000000 */ 127 /* CS1: 0x14000000 .. 0x18000000 */ 128 [VE_SRAM] = 0x14000000, 129 /* CS2: 0x18000000 .. 0x1c000000 */ 130 [VE_VIDEORAM] = 0x18000000, 131 [VE_ETHERNET] = 0x1a000000, 132 [VE_USB] = 0x1b000000, 133 /* CS3: 0x1c000000 .. 0x20000000 */ 134 [VE_DAPROM] = 0x1c000000, 135 [VE_SYSREGS] = 0x1c010000, 136 [VE_SP810] = 0x1c020000, 137 [VE_SERIALPCI] = 0x1c030000, 138 [VE_PL041] = 0x1c040000, 139 [VE_MMCI] = 0x1c050000, 140 [VE_KMI0] = 0x1c060000, 141 [VE_KMI1] = 0x1c070000, 142 [VE_UART0] = 0x1c090000, 143 [VE_UART1] = 0x1c0a0000, 144 [VE_UART2] = 0x1c0b0000, 145 [VE_UART3] = 0x1c0c0000, 146 [VE_WDT] = 0x1c0f0000, 147 [VE_TIMER01] = 0x1c110000, 148 [VE_TIMER23] = 0x1c120000, 149 [VE_VIRTIO] = 0x1c130000, 150 [VE_SERIALDVI] = 0x1c160000, 151 [VE_RTC] = 0x1c170000, 152 [VE_COMPACTFLASH] = 0x1c1a0000, 153 [VE_CLCD] = 0x1c1f0000, 154 }; 155 156 /* Structure defining the peculiarities of a specific daughterboard */ 157 158 typedef struct VEDBoardInfo VEDBoardInfo; 159 160 typedef struct { 161 MachineClass parent; 162 VEDBoardInfo *daughterboard; 163 } VexpressMachineClass; 164 165 typedef struct { 166 MachineState parent; 167 bool secure; 168 } VexpressMachineState; 169 170 #define TYPE_VEXPRESS_MACHINE "vexpress" 171 #define VEXPRESS_A9_MACHINE_NAME "vexpress-a9" 172 #define VEXPRESS_A15_MACHINE_NAME "vexpress-a15" 173 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME(VEXPRESS_A9_MACHINE_NAME) 174 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME(VEXPRESS_A15_MACHINE_NAME) 175 #define VEXPRESS_MACHINE(obj) \ 176 OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE) 177 #define VEXPRESS_MACHINE_GET_CLASS(obj) \ 178 OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE) 179 #define VEXPRESS_MACHINE_CLASS(klass) \ 180 OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE) 181 182 typedef void DBoardInitFn(const VexpressMachineState *machine, 183 ram_addr_t ram_size, 184 const char *cpu_model, 185 qemu_irq *pic); 186 187 struct VEDBoardInfo { 188 struct arm_boot_info bootinfo; 189 const hwaddr *motherboard_map; 190 hwaddr loader_start; 191 const hwaddr gic_cpu_if_addr; 192 uint32_t proc_id; 193 uint32_t num_voltage_sensors; 194 const uint32_t *voltages; 195 uint32_t num_clocks; 196 const uint32_t *clocks; 197 DBoardInitFn *init; 198 }; 199 200 static void init_cpus(const char *cpu_model, const char *privdev, 201 hwaddr periphbase, qemu_irq *pic, bool secure) 202 { 203 ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 204 DeviceState *dev; 205 SysBusDevice *busdev; 206 int n; 207 208 if (!cpu_oc) { 209 fprintf(stderr, "Unable to find CPU definition\n"); 210 exit(1); 211 } 212 213 /* Create the actual CPUs */ 214 for (n = 0; n < smp_cpus; n++) { 215 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 216 Error *err = NULL; 217 218 if (!secure) { 219 object_property_set_bool(cpuobj, false, "has_el3", NULL); 220 } 221 222 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 223 object_property_set_int(cpuobj, periphbase, 224 "reset-cbar", &error_abort); 225 } 226 object_property_set_bool(cpuobj, true, "realized", &err); 227 if (err) { 228 error_report_err(err); 229 exit(1); 230 } 231 } 232 233 /* Create the private peripheral devices (including the GIC); 234 * this must happen after the CPUs are created because a15mpcore_priv 235 * wires itself up to the CPU's generic_timer gpio out lines. 236 */ 237 dev = qdev_create(NULL, privdev); 238 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 239 qdev_init_nofail(dev); 240 busdev = SYS_BUS_DEVICE(dev); 241 sysbus_mmio_map(busdev, 0, periphbase); 242 243 /* Interrupts [42:0] are from the motherboard; 244 * [47:43] are reserved; [63:48] are daughterboard 245 * peripherals. Note that some documentation numbers 246 * external interrupts starting from 32 (because there 247 * are internal interrupts 0..31). 248 */ 249 for (n = 0; n < 64; n++) { 250 pic[n] = qdev_get_gpio_in(dev, n); 251 } 252 253 /* Connect the CPUs to the GIC */ 254 for (n = 0; n < smp_cpus; n++) { 255 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 256 257 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 258 sysbus_connect_irq(busdev, n + smp_cpus, 259 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 260 } 261 } 262 263 static void a9_daughterboard_init(const VexpressMachineState *vms, 264 ram_addr_t ram_size, 265 const char *cpu_model, 266 qemu_irq *pic) 267 { 268 MemoryRegion *sysmem = get_system_memory(); 269 MemoryRegion *ram = g_new(MemoryRegion, 1); 270 MemoryRegion *lowram = g_new(MemoryRegion, 1); 271 ram_addr_t low_ram_size; 272 273 if (!cpu_model) { 274 cpu_model = "cortex-a9"; 275 } 276 277 if (ram_size > 0x40000000) { 278 /* 1GB is the maximum the address space permits */ 279 fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); 280 exit(1); 281 } 282 283 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 284 ram_size); 285 low_ram_size = ram_size; 286 if (low_ram_size > 0x4000000) { 287 low_ram_size = 0x4000000; 288 } 289 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 290 * address space should in theory be remappable to various 291 * things including ROM or RAM; we always map the RAM there. 292 */ 293 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 294 memory_region_add_subregion(sysmem, 0x0, lowram); 295 memory_region_add_subregion(sysmem, 0x60000000, ram); 296 297 /* 0x1e000000 A9MPCore (SCU) private memory region */ 298 init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic, vms->secure); 299 300 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 301 302 /* 0x10020000 PL111 CLCD (daughterboard) */ 303 sysbus_create_simple("pl111", 0x10020000, pic[44]); 304 305 /* 0x10060000 AXI RAM */ 306 /* 0x100e0000 PL341 Dynamic Memory Controller */ 307 /* 0x100e1000 PL354 Static Memory Controller */ 308 /* 0x100e2000 System Configuration Controller */ 309 310 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 311 /* 0x100e5000 SP805 Watchdog module */ 312 /* 0x100e6000 BP147 TrustZone Protection Controller */ 313 /* 0x100e9000 PL301 'Fast' AXI matrix */ 314 /* 0x100ea000 PL301 'Slow' AXI matrix */ 315 /* 0x100ec000 TrustZone Address Space Controller */ 316 /* 0x10200000 CoreSight debug APB */ 317 /* 0x1e00a000 PL310 L2 Cache Controller */ 318 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 319 } 320 321 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 322 * values are in microvolts. 323 */ 324 static const uint32_t a9_voltages[] = { 325 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 326 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 327 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 328 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 329 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 330 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 331 }; 332 333 /* Reset values for daughterboard oscillators (in Hz) */ 334 static const uint32_t a9_clocks[] = { 335 45000000, /* AMBA AXI ACLK: 45MHz */ 336 23750000, /* daughterboard CLCD clock: 23.75MHz */ 337 66670000, /* Test chip reference clock: 66.67MHz */ 338 }; 339 340 static VEDBoardInfo a9_daughterboard = { 341 .motherboard_map = motherboard_legacy_map, 342 .loader_start = 0x60000000, 343 .gic_cpu_if_addr = 0x1e000100, 344 .proc_id = 0x0c000191, 345 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 346 .voltages = a9_voltages, 347 .num_clocks = ARRAY_SIZE(a9_clocks), 348 .clocks = a9_clocks, 349 .init = a9_daughterboard_init, 350 }; 351 352 static void a15_daughterboard_init(const VexpressMachineState *vms, 353 ram_addr_t ram_size, 354 const char *cpu_model, 355 qemu_irq *pic) 356 { 357 MemoryRegion *sysmem = get_system_memory(); 358 MemoryRegion *ram = g_new(MemoryRegion, 1); 359 MemoryRegion *sram = g_new(MemoryRegion, 1); 360 361 if (!cpu_model) { 362 cpu_model = "cortex-a15"; 363 } 364 365 { 366 /* We have to use a separate 64 bit variable here to avoid the gcc 367 * "comparison is always false due to limited range of data type" 368 * warning if we are on a host where ram_addr_t is 32 bits. 369 */ 370 uint64_t rsz = ram_size; 371 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 372 fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); 373 exit(1); 374 } 375 } 376 377 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 378 ram_size); 379 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 380 memory_region_add_subregion(sysmem, 0x80000000, ram); 381 382 /* 0x2c000000 A15MPCore private memory region (GIC) */ 383 init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic, vms->secure); 384 385 /* A15 daughterboard peripherals: */ 386 387 /* 0x20000000: CoreSight interfaces: not modelled */ 388 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 389 /* 0x2a420000: SCC: not modelled */ 390 /* 0x2a430000: system counter: not modelled */ 391 /* 0x2b000000: HDLCD controller: not modelled */ 392 /* 0x2b060000: SP805 watchdog: not modelled */ 393 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 394 /* 0x2e000000: system SRAM */ 395 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, 396 &error_fatal); 397 vmstate_register_ram_global(sram); 398 memory_region_add_subregion(sysmem, 0x2e000000, sram); 399 400 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 401 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 402 } 403 404 static const uint32_t a15_voltages[] = { 405 900000, /* Vcore: 0.9V : CPU core voltage */ 406 }; 407 408 static const uint32_t a15_clocks[] = { 409 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 410 0, /* OSCCLK1: reserved */ 411 0, /* OSCCLK2: reserved */ 412 0, /* OSCCLK3: reserved */ 413 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 414 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 415 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 416 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 417 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 418 }; 419 420 static VEDBoardInfo a15_daughterboard = { 421 .motherboard_map = motherboard_aseries_map, 422 .loader_start = 0x80000000, 423 .gic_cpu_if_addr = 0x2c002000, 424 .proc_id = 0x14000237, 425 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 426 .voltages = a15_voltages, 427 .num_clocks = ARRAY_SIZE(a15_clocks), 428 .clocks = a15_clocks, 429 .init = a15_daughterboard_init, 430 }; 431 432 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 433 hwaddr addr, hwaddr size, uint32_t intc, 434 int irq) 435 { 436 /* Add a virtio_mmio node to the device tree blob: 437 * virtio_mmio@ADDRESS { 438 * compatible = "virtio,mmio"; 439 * reg = <ADDRESS, SIZE>; 440 * interrupt-parent = <&intc>; 441 * interrupts = <0, irq, 1>; 442 * } 443 * (Note that the format of the interrupts property is dependent on the 444 * interrupt controller that interrupt-parent points to; these are for 445 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 446 */ 447 int rc; 448 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 449 450 rc = qemu_fdt_add_subnode(fdt, nodename); 451 rc |= qemu_fdt_setprop_string(fdt, nodename, 452 "compatible", "virtio,mmio"); 453 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 454 acells, addr, scells, size); 455 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 456 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 457 g_free(nodename); 458 if (rc) { 459 return -1; 460 } 461 return 0; 462 } 463 464 static uint32_t find_int_controller(void *fdt) 465 { 466 /* Find the FDT node corresponding to the interrupt controller 467 * for virtio-mmio devices. We do this by scanning the fdt for 468 * a node with the right compatibility, since we know there is 469 * only one GIC on a vexpress board. 470 * We return the phandle of the node, or 0 if none was found. 471 */ 472 const char *compat = "arm,cortex-a9-gic"; 473 int offset; 474 475 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 476 if (offset >= 0) { 477 return fdt_get_phandle(fdt, offset); 478 } 479 return 0; 480 } 481 482 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 483 { 484 uint32_t acells, scells, intc; 485 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 486 487 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells"); 488 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells"); 489 intc = find_int_controller(fdt); 490 if (!intc) { 491 /* Not fatal, we just won't provide virtio. This will 492 * happen with older device tree blobs. 493 */ 494 fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in " 495 "dtb; will not include virtio-mmio devices in the dtb.\n"); 496 } else { 497 int i; 498 const hwaddr *map = daughterboard->motherboard_map; 499 500 /* We iterate backwards here because adding nodes 501 * to the dtb puts them in last-first. 502 */ 503 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 504 add_virtio_mmio_node(fdt, acells, scells, 505 map[VE_VIRTIO] + 0x200 * i, 506 0x200, intc, 40 + i); 507 } 508 } 509 } 510 511 512 /* Open code a private version of pflash registration since we 513 * need to set non-default device width for VExpress platform. 514 */ 515 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, 516 DriveInfo *di) 517 { 518 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 519 520 if (di) { 521 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di), 522 &error_abort); 523 } 524 525 qdev_prop_set_uint32(dev, "num-blocks", 526 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 527 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 528 qdev_prop_set_uint8(dev, "width", 4); 529 qdev_prop_set_uint8(dev, "device-width", 2); 530 qdev_prop_set_bit(dev, "big-endian", false); 531 qdev_prop_set_uint16(dev, "id0", 0x89); 532 qdev_prop_set_uint16(dev, "id1", 0x18); 533 qdev_prop_set_uint16(dev, "id2", 0x00); 534 qdev_prop_set_uint16(dev, "id3", 0x00); 535 qdev_prop_set_string(dev, "name", name); 536 qdev_init_nofail(dev); 537 538 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 539 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 540 } 541 542 static void vexpress_common_init(MachineState *machine) 543 { 544 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 545 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 546 VEDBoardInfo *daughterboard = vmc->daughterboard; 547 DeviceState *dev, *sysctl, *pl041; 548 qemu_irq pic[64]; 549 uint32_t sys_id; 550 DriveInfo *dinfo; 551 pflash_t *pflash0; 552 ram_addr_t vram_size, sram_size; 553 MemoryRegion *sysmem = get_system_memory(); 554 MemoryRegion *vram = g_new(MemoryRegion, 1); 555 MemoryRegion *sram = g_new(MemoryRegion, 1); 556 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 557 MemoryRegion *flash0mem; 558 const hwaddr *map = daughterboard->motherboard_map; 559 int i; 560 561 daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic); 562 563 /* 564 * If a bios file was provided, attempt to map it into memory 565 */ 566 if (bios_name) { 567 char *fn; 568 int image_size; 569 570 if (drive_get(IF_PFLASH, 0, 0)) { 571 error_report("The contents of the first flash device may be " 572 "specified with -bios or with -drive if=pflash... " 573 "but you cannot use both options at once"); 574 exit(1); 575 } 576 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 577 if (!fn) { 578 error_report("Could not find ROM image '%s'", bios_name); 579 exit(1); 580 } 581 image_size = load_image_targphys(fn, map[VE_NORFLASH0], 582 VEXPRESS_FLASH_SIZE); 583 g_free(fn); 584 if (image_size < 0) { 585 error_report("Could not load ROM image '%s'", bios_name); 586 exit(1); 587 } 588 } 589 590 /* Motherboard peripherals: the wiring is the same but the 591 * addresses vary between the legacy and A-Series memory maps. 592 */ 593 594 sys_id = 0x1190f500; 595 596 sysctl = qdev_create(NULL, "realview_sysctl"); 597 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 598 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 599 qdev_prop_set_uint32(sysctl, "len-db-voltage", 600 daughterboard->num_voltage_sensors); 601 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 602 char *propname = g_strdup_printf("db-voltage[%d]", i); 603 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 604 g_free(propname); 605 } 606 qdev_prop_set_uint32(sysctl, "len-db-clock", 607 daughterboard->num_clocks); 608 for (i = 0; i < daughterboard->num_clocks; i++) { 609 char *propname = g_strdup_printf("db-clock[%d]", i); 610 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 611 g_free(propname); 612 } 613 qdev_init_nofail(sysctl); 614 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 615 616 /* VE_SP810: not modelled */ 617 /* VE_SERIALPCI: not modelled */ 618 619 pl041 = qdev_create(NULL, "pl041"); 620 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 621 qdev_init_nofail(pl041); 622 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 623 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 624 625 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 626 /* Wire up MMC card detect and read-only signals */ 627 qdev_connect_gpio_out(dev, 0, 628 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 629 qdev_connect_gpio_out(dev, 1, 630 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 631 632 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 633 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 634 635 sysbus_create_simple("pl011", map[VE_UART0], pic[5]); 636 sysbus_create_simple("pl011", map[VE_UART1], pic[6]); 637 sysbus_create_simple("pl011", map[VE_UART2], pic[7]); 638 sysbus_create_simple("pl011", map[VE_UART3], pic[8]); 639 640 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 641 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 642 643 /* VE_SERIALDVI: not modelled */ 644 645 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 646 647 /* VE_COMPACTFLASH: not modelled */ 648 649 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 650 651 dinfo = drive_get_next(IF_PFLASH); 652 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 653 dinfo); 654 if (!pflash0) { 655 fprintf(stderr, "vexpress: error registering flash 0.\n"); 656 exit(1); 657 } 658 659 if (map[VE_NORFLASHALIAS] != -1) { 660 /* Map flash 0 as an alias into low memory */ 661 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 662 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 663 flash0mem, 0, VEXPRESS_FLASH_SIZE); 664 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 665 } 666 667 dinfo = drive_get_next(IF_PFLASH); 668 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 669 dinfo)) { 670 fprintf(stderr, "vexpress: error registering flash 1.\n"); 671 exit(1); 672 } 673 674 sram_size = 0x2000000; 675 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, 676 &error_fatal); 677 vmstate_register_ram_global(sram); 678 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 679 680 vram_size = 0x800000; 681 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, 682 &error_fatal); 683 vmstate_register_ram_global(vram); 684 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 685 686 /* 0x4e000000 LAN9118 Ethernet */ 687 if (nd_table[0].used) { 688 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 689 } 690 691 /* VE_USB: not modelled */ 692 693 /* VE_DAPROM: not modelled */ 694 695 /* Create mmio transports, so the user can create virtio backends 696 * (which will be automatically plugged in to the transports). If 697 * no backend is created the transport will just sit harmlessly idle. 698 */ 699 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 700 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 701 pic[40 + i]); 702 } 703 704 daughterboard->bootinfo.ram_size = machine->ram_size; 705 daughterboard->bootinfo.kernel_filename = machine->kernel_filename; 706 daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline; 707 daughterboard->bootinfo.initrd_filename = machine->initrd_filename; 708 daughterboard->bootinfo.nb_cpus = smp_cpus; 709 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 710 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 711 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 712 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 713 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 714 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 715 /* Indicate that when booting Linux we should be in secure state */ 716 daughterboard->bootinfo.secure_boot = true; 717 arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); 718 } 719 720 static bool vexpress_get_secure(Object *obj, Error **errp) 721 { 722 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 723 724 return vms->secure; 725 } 726 727 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 728 { 729 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 730 731 vms->secure = value; 732 } 733 734 static void vexpress_instance_init(Object *obj) 735 { 736 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 737 738 /* EL3 is enabled by default on vexpress */ 739 vms->secure = true; 740 object_property_add_bool(obj, "secure", vexpress_get_secure, 741 vexpress_set_secure, NULL); 742 object_property_set_description(obj, "secure", 743 "Set on/off to enable/disable the ARM " 744 "Security Extensions (TrustZone)", 745 NULL); 746 } 747 748 static void vexpress_class_init(ObjectClass *oc, void *data) 749 { 750 MachineClass *mc = MACHINE_CLASS(oc); 751 752 mc->desc = "ARM Versatile Express"; 753 mc->init = vexpress_common_init; 754 mc->block_default_type = IF_SCSI; 755 mc->max_cpus = 4; 756 } 757 758 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 759 { 760 MachineClass *mc = MACHINE_CLASS(oc); 761 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 762 763 mc->name = VEXPRESS_A9_MACHINE_NAME; 764 mc->desc = "ARM Versatile Express for Cortex-A9"; 765 766 vmc->daughterboard = &a9_daughterboard; 767 } 768 769 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 770 { 771 MachineClass *mc = MACHINE_CLASS(oc); 772 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 773 774 mc->name = VEXPRESS_A15_MACHINE_NAME; 775 mc->desc = "ARM Versatile Express for Cortex-A15"; 776 777 vmc->daughterboard = &a15_daughterboard; 778 } 779 780 static const TypeInfo vexpress_info = { 781 .name = TYPE_VEXPRESS_MACHINE, 782 .parent = TYPE_MACHINE, 783 .abstract = true, 784 .instance_size = sizeof(VexpressMachineState), 785 .instance_init = vexpress_instance_init, 786 .class_size = sizeof(VexpressMachineClass), 787 .class_init = vexpress_class_init, 788 }; 789 790 static const TypeInfo vexpress_a9_info = { 791 .name = TYPE_VEXPRESS_A9_MACHINE, 792 .parent = TYPE_VEXPRESS_MACHINE, 793 .class_init = vexpress_a9_class_init, 794 }; 795 796 static const TypeInfo vexpress_a15_info = { 797 .name = TYPE_VEXPRESS_A15_MACHINE, 798 .parent = TYPE_VEXPRESS_MACHINE, 799 .class_init = vexpress_a15_class_init, 800 }; 801 802 static void vexpress_machine_init(void) 803 { 804 type_register_static(&vexpress_info); 805 type_register_static(&vexpress_a9_info); 806 type_register_static(&vexpress_a15_info); 807 } 808 809 machine_init(vexpress_machine_init); 810