1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "hw/sysbus.h" 25 #include "hw/arm/arm.h" 26 #include "hw/arm/primecell.h" 27 #include "hw/devices.h" 28 #include "net/net.h" 29 #include "sysemu/sysemu.h" 30 #include "hw/boards.h" 31 #include "hw/loader.h" 32 #include "exec/address-spaces.h" 33 #include "sysemu/block-backend.h" 34 #include "sysemu/blockdev.h" 35 #include "hw/block/flash.h" 36 #include "sysemu/device_tree.h" 37 #include "qemu/error-report.h" 38 #include <libfdt.h> 39 40 #define VEXPRESS_BOARD_ID 0x8e0 41 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 42 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 43 44 /* Number of virtio transports to create (0..8; limited by 45 * number of available IRQ lines). 46 */ 47 #define NUM_VIRTIO_TRANSPORTS 4 48 49 /* Address maps for peripherals: 50 * the Versatile Express motherboard has two possible maps, 51 * the "legacy" one (used for A9) and the "Cortex-A Series" 52 * map (used for newer cores). 53 * Individual daughterboards can also have different maps for 54 * their peripherals. 55 */ 56 57 enum { 58 VE_SYSREGS, 59 VE_SP810, 60 VE_SERIALPCI, 61 VE_PL041, 62 VE_MMCI, 63 VE_KMI0, 64 VE_KMI1, 65 VE_UART0, 66 VE_UART1, 67 VE_UART2, 68 VE_UART3, 69 VE_WDT, 70 VE_TIMER01, 71 VE_TIMER23, 72 VE_SERIALDVI, 73 VE_RTC, 74 VE_COMPACTFLASH, 75 VE_CLCD, 76 VE_NORFLASH0, 77 VE_NORFLASH1, 78 VE_NORFLASHALIAS, 79 VE_SRAM, 80 VE_VIDEORAM, 81 VE_ETHERNET, 82 VE_USB, 83 VE_DAPROM, 84 VE_VIRTIO, 85 }; 86 87 static hwaddr motherboard_legacy_map[] = { 88 [VE_NORFLASHALIAS] = 0, 89 /* CS7: 0x10000000 .. 0x10020000 */ 90 [VE_SYSREGS] = 0x10000000, 91 [VE_SP810] = 0x10001000, 92 [VE_SERIALPCI] = 0x10002000, 93 [VE_PL041] = 0x10004000, 94 [VE_MMCI] = 0x10005000, 95 [VE_KMI0] = 0x10006000, 96 [VE_KMI1] = 0x10007000, 97 [VE_UART0] = 0x10009000, 98 [VE_UART1] = 0x1000a000, 99 [VE_UART2] = 0x1000b000, 100 [VE_UART3] = 0x1000c000, 101 [VE_WDT] = 0x1000f000, 102 [VE_TIMER01] = 0x10011000, 103 [VE_TIMER23] = 0x10012000, 104 [VE_VIRTIO] = 0x10013000, 105 [VE_SERIALDVI] = 0x10016000, 106 [VE_RTC] = 0x10017000, 107 [VE_COMPACTFLASH] = 0x1001a000, 108 [VE_CLCD] = 0x1001f000, 109 /* CS0: 0x40000000 .. 0x44000000 */ 110 [VE_NORFLASH0] = 0x40000000, 111 /* CS1: 0x44000000 .. 0x48000000 */ 112 [VE_NORFLASH1] = 0x44000000, 113 /* CS2: 0x48000000 .. 0x4a000000 */ 114 [VE_SRAM] = 0x48000000, 115 /* CS3: 0x4c000000 .. 0x50000000 */ 116 [VE_VIDEORAM] = 0x4c000000, 117 [VE_ETHERNET] = 0x4e000000, 118 [VE_USB] = 0x4f000000, 119 }; 120 121 static hwaddr motherboard_aseries_map[] = { 122 [VE_NORFLASHALIAS] = 0, 123 /* CS0: 0x08000000 .. 0x0c000000 */ 124 [VE_NORFLASH0] = 0x08000000, 125 /* CS4: 0x0c000000 .. 0x10000000 */ 126 [VE_NORFLASH1] = 0x0c000000, 127 /* CS5: 0x10000000 .. 0x14000000 */ 128 /* CS1: 0x14000000 .. 0x18000000 */ 129 [VE_SRAM] = 0x14000000, 130 /* CS2: 0x18000000 .. 0x1c000000 */ 131 [VE_VIDEORAM] = 0x18000000, 132 [VE_ETHERNET] = 0x1a000000, 133 [VE_USB] = 0x1b000000, 134 /* CS3: 0x1c000000 .. 0x20000000 */ 135 [VE_DAPROM] = 0x1c000000, 136 [VE_SYSREGS] = 0x1c010000, 137 [VE_SP810] = 0x1c020000, 138 [VE_SERIALPCI] = 0x1c030000, 139 [VE_PL041] = 0x1c040000, 140 [VE_MMCI] = 0x1c050000, 141 [VE_KMI0] = 0x1c060000, 142 [VE_KMI1] = 0x1c070000, 143 [VE_UART0] = 0x1c090000, 144 [VE_UART1] = 0x1c0a0000, 145 [VE_UART2] = 0x1c0b0000, 146 [VE_UART3] = 0x1c0c0000, 147 [VE_WDT] = 0x1c0f0000, 148 [VE_TIMER01] = 0x1c110000, 149 [VE_TIMER23] = 0x1c120000, 150 [VE_VIRTIO] = 0x1c130000, 151 [VE_SERIALDVI] = 0x1c160000, 152 [VE_RTC] = 0x1c170000, 153 [VE_COMPACTFLASH] = 0x1c1a0000, 154 [VE_CLCD] = 0x1c1f0000, 155 }; 156 157 /* Structure defining the peculiarities of a specific daughterboard */ 158 159 typedef struct VEDBoardInfo VEDBoardInfo; 160 161 typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, 162 ram_addr_t ram_size, 163 const char *cpu_model, 164 qemu_irq *pic); 165 166 struct VEDBoardInfo { 167 struct arm_boot_info bootinfo; 168 const hwaddr *motherboard_map; 169 hwaddr loader_start; 170 const hwaddr gic_cpu_if_addr; 171 uint32_t proc_id; 172 uint32_t num_voltage_sensors; 173 const uint32_t *voltages; 174 uint32_t num_clocks; 175 const uint32_t *clocks; 176 DBoardInitFn *init; 177 }; 178 179 static void init_cpus(const char *cpu_model, const char *privdev, 180 hwaddr periphbase, qemu_irq *pic) 181 { 182 ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 183 DeviceState *dev; 184 SysBusDevice *busdev; 185 int n; 186 187 if (!cpu_oc) { 188 fprintf(stderr, "Unable to find CPU definition\n"); 189 exit(1); 190 } 191 192 /* Create the actual CPUs */ 193 for (n = 0; n < smp_cpus; n++) { 194 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 195 Error *err = NULL; 196 197 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 198 object_property_set_int(cpuobj, periphbase, 199 "reset-cbar", &error_abort); 200 } 201 object_property_set_bool(cpuobj, true, "realized", &err); 202 if (err) { 203 error_report("%s", error_get_pretty(err)); 204 exit(1); 205 } 206 } 207 208 /* Create the private peripheral devices (including the GIC); 209 * this must happen after the CPUs are created because a15mpcore_priv 210 * wires itself up to the CPU's generic_timer gpio out lines. 211 */ 212 dev = qdev_create(NULL, privdev); 213 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 214 qdev_init_nofail(dev); 215 busdev = SYS_BUS_DEVICE(dev); 216 sysbus_mmio_map(busdev, 0, periphbase); 217 218 /* Interrupts [42:0] are from the motherboard; 219 * [47:43] are reserved; [63:48] are daughterboard 220 * peripherals. Note that some documentation numbers 221 * external interrupts starting from 32 (because there 222 * are internal interrupts 0..31). 223 */ 224 for (n = 0; n < 64; n++) { 225 pic[n] = qdev_get_gpio_in(dev, n); 226 } 227 228 /* Connect the CPUs to the GIC */ 229 for (n = 0; n < smp_cpus; n++) { 230 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 231 232 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 233 } 234 } 235 236 static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, 237 ram_addr_t ram_size, 238 const char *cpu_model, 239 qemu_irq *pic) 240 { 241 MemoryRegion *sysmem = get_system_memory(); 242 MemoryRegion *ram = g_new(MemoryRegion, 1); 243 MemoryRegion *lowram = g_new(MemoryRegion, 1); 244 ram_addr_t low_ram_size; 245 246 if (!cpu_model) { 247 cpu_model = "cortex-a9"; 248 } 249 250 if (ram_size > 0x40000000) { 251 /* 1GB is the maximum the address space permits */ 252 fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); 253 exit(1); 254 } 255 256 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size, 257 &error_abort); 258 vmstate_register_ram_global(ram); 259 low_ram_size = ram_size; 260 if (low_ram_size > 0x4000000) { 261 low_ram_size = 0x4000000; 262 } 263 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 264 * address space should in theory be remappable to various 265 * things including ROM or RAM; we always map the RAM there. 266 */ 267 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 268 memory_region_add_subregion(sysmem, 0x0, lowram); 269 memory_region_add_subregion(sysmem, 0x60000000, ram); 270 271 /* 0x1e000000 A9MPCore (SCU) private memory region */ 272 init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic); 273 274 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 275 276 /* 0x10020000 PL111 CLCD (daughterboard) */ 277 sysbus_create_simple("pl111", 0x10020000, pic[44]); 278 279 /* 0x10060000 AXI RAM */ 280 /* 0x100e0000 PL341 Dynamic Memory Controller */ 281 /* 0x100e1000 PL354 Static Memory Controller */ 282 /* 0x100e2000 System Configuration Controller */ 283 284 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 285 /* 0x100e5000 SP805 Watchdog module */ 286 /* 0x100e6000 BP147 TrustZone Protection Controller */ 287 /* 0x100e9000 PL301 'Fast' AXI matrix */ 288 /* 0x100ea000 PL301 'Slow' AXI matrix */ 289 /* 0x100ec000 TrustZone Address Space Controller */ 290 /* 0x10200000 CoreSight debug APB */ 291 /* 0x1e00a000 PL310 L2 Cache Controller */ 292 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 293 } 294 295 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 296 * values are in microvolts. 297 */ 298 static const uint32_t a9_voltages[] = { 299 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 300 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 301 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 302 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 303 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 304 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 305 }; 306 307 /* Reset values for daughterboard oscillators (in Hz) */ 308 static const uint32_t a9_clocks[] = { 309 45000000, /* AMBA AXI ACLK: 45MHz */ 310 23750000, /* daughterboard CLCD clock: 23.75MHz */ 311 66670000, /* Test chip reference clock: 66.67MHz */ 312 }; 313 314 static VEDBoardInfo a9_daughterboard = { 315 .motherboard_map = motherboard_legacy_map, 316 .loader_start = 0x60000000, 317 .gic_cpu_if_addr = 0x1e000100, 318 .proc_id = 0x0c000191, 319 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 320 .voltages = a9_voltages, 321 .num_clocks = ARRAY_SIZE(a9_clocks), 322 .clocks = a9_clocks, 323 .init = a9_daughterboard_init, 324 }; 325 326 static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, 327 ram_addr_t ram_size, 328 const char *cpu_model, 329 qemu_irq *pic) 330 { 331 MemoryRegion *sysmem = get_system_memory(); 332 MemoryRegion *ram = g_new(MemoryRegion, 1); 333 MemoryRegion *sram = g_new(MemoryRegion, 1); 334 335 if (!cpu_model) { 336 cpu_model = "cortex-a15"; 337 } 338 339 { 340 /* We have to use a separate 64 bit variable here to avoid the gcc 341 * "comparison is always false due to limited range of data type" 342 * warning if we are on a host where ram_addr_t is 32 bits. 343 */ 344 uint64_t rsz = ram_size; 345 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 346 fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); 347 exit(1); 348 } 349 } 350 351 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size, 352 &error_abort); 353 vmstate_register_ram_global(ram); 354 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 355 memory_region_add_subregion(sysmem, 0x80000000, ram); 356 357 /* 0x2c000000 A15MPCore private memory region (GIC) */ 358 init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic); 359 360 /* A15 daughterboard peripherals: */ 361 362 /* 0x20000000: CoreSight interfaces: not modelled */ 363 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 364 /* 0x2a420000: SCC: not modelled */ 365 /* 0x2a430000: system counter: not modelled */ 366 /* 0x2b000000: HDLCD controller: not modelled */ 367 /* 0x2b060000: SP805 watchdog: not modelled */ 368 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 369 /* 0x2e000000: system SRAM */ 370 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, 371 &error_abort); 372 vmstate_register_ram_global(sram); 373 memory_region_add_subregion(sysmem, 0x2e000000, sram); 374 375 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 376 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 377 } 378 379 static const uint32_t a15_voltages[] = { 380 900000, /* Vcore: 0.9V : CPU core voltage */ 381 }; 382 383 static const uint32_t a15_clocks[] = { 384 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 385 0, /* OSCCLK1: reserved */ 386 0, /* OSCCLK2: reserved */ 387 0, /* OSCCLK3: reserved */ 388 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 389 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 390 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 391 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 392 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 393 }; 394 395 static VEDBoardInfo a15_daughterboard = { 396 .motherboard_map = motherboard_aseries_map, 397 .loader_start = 0x80000000, 398 .gic_cpu_if_addr = 0x2c002000, 399 .proc_id = 0x14000237, 400 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 401 .voltages = a15_voltages, 402 .num_clocks = ARRAY_SIZE(a15_clocks), 403 .clocks = a15_clocks, 404 .init = a15_daughterboard_init, 405 }; 406 407 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 408 hwaddr addr, hwaddr size, uint32_t intc, 409 int irq) 410 { 411 /* Add a virtio_mmio node to the device tree blob: 412 * virtio_mmio@ADDRESS { 413 * compatible = "virtio,mmio"; 414 * reg = <ADDRESS, SIZE>; 415 * interrupt-parent = <&intc>; 416 * interrupts = <0, irq, 1>; 417 * } 418 * (Note that the format of the interrupts property is dependent on the 419 * interrupt controller that interrupt-parent points to; these are for 420 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 421 */ 422 int rc; 423 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 424 425 rc = qemu_fdt_add_subnode(fdt, nodename); 426 rc |= qemu_fdt_setprop_string(fdt, nodename, 427 "compatible", "virtio,mmio"); 428 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 429 acells, addr, scells, size); 430 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 431 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 432 g_free(nodename); 433 if (rc) { 434 return -1; 435 } 436 return 0; 437 } 438 439 static uint32_t find_int_controller(void *fdt) 440 { 441 /* Find the FDT node corresponding to the interrupt controller 442 * for virtio-mmio devices. We do this by scanning the fdt for 443 * a node with the right compatibility, since we know there is 444 * only one GIC on a vexpress board. 445 * We return the phandle of the node, or 0 if none was found. 446 */ 447 const char *compat = "arm,cortex-a9-gic"; 448 int offset; 449 450 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 451 if (offset >= 0) { 452 return fdt_get_phandle(fdt, offset); 453 } 454 return 0; 455 } 456 457 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 458 { 459 uint32_t acells, scells, intc; 460 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 461 462 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells"); 463 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells"); 464 intc = find_int_controller(fdt); 465 if (!intc) { 466 /* Not fatal, we just won't provide virtio. This will 467 * happen with older device tree blobs. 468 */ 469 fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in " 470 "dtb; will not include virtio-mmio devices in the dtb.\n"); 471 } else { 472 int i; 473 const hwaddr *map = daughterboard->motherboard_map; 474 475 /* We iterate backwards here because adding nodes 476 * to the dtb puts them in last-first. 477 */ 478 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 479 add_virtio_mmio_node(fdt, acells, scells, 480 map[VE_VIRTIO] + 0x200 * i, 481 0x200, intc, 40 + i); 482 } 483 } 484 } 485 486 487 /* Open code a private version of pflash registration since we 488 * need to set non-default device width for VExpress platform. 489 */ 490 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, 491 DriveInfo *di) 492 { 493 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 494 495 if (di && qdev_prop_set_drive(dev, "drive", 496 blk_bs(blk_by_legacy_dinfo(di)))) { 497 abort(); 498 } 499 500 qdev_prop_set_uint32(dev, "num-blocks", 501 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 502 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 503 qdev_prop_set_uint8(dev, "width", 4); 504 qdev_prop_set_uint8(dev, "device-width", 2); 505 qdev_prop_set_uint8(dev, "big-endian", 0); 506 qdev_prop_set_uint16(dev, "id0", 0x89); 507 qdev_prop_set_uint16(dev, "id1", 0x18); 508 qdev_prop_set_uint16(dev, "id2", 0x00); 509 qdev_prop_set_uint16(dev, "id3", 0x00); 510 qdev_prop_set_string(dev, "name", name); 511 qdev_init_nofail(dev); 512 513 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 514 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 515 } 516 517 static void vexpress_common_init(VEDBoardInfo *daughterboard, 518 MachineState *machine) 519 { 520 DeviceState *dev, *sysctl, *pl041; 521 qemu_irq pic[64]; 522 uint32_t sys_id; 523 DriveInfo *dinfo; 524 pflash_t *pflash0; 525 ram_addr_t vram_size, sram_size; 526 MemoryRegion *sysmem = get_system_memory(); 527 MemoryRegion *vram = g_new(MemoryRegion, 1); 528 MemoryRegion *sram = g_new(MemoryRegion, 1); 529 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 530 MemoryRegion *flash0mem; 531 const hwaddr *map = daughterboard->motherboard_map; 532 int i; 533 534 daughterboard->init(daughterboard, machine->ram_size, machine->cpu_model, 535 pic); 536 537 /* 538 * If a bios file was provided, attempt to map it into memory 539 */ 540 if (bios_name) { 541 const char *fn; 542 543 if (drive_get(IF_PFLASH, 0, 0)) { 544 error_report("The contents of the first flash device may be " 545 "specified with -bios or with -drive if=pflash... " 546 "but you cannot use both options at once"); 547 exit(1); 548 } 549 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 550 if (!fn || load_image_targphys(fn, map[VE_NORFLASH0], 551 VEXPRESS_FLASH_SIZE) < 0) { 552 error_report("Could not load ROM image '%s'", bios_name); 553 exit(1); 554 } 555 } 556 557 /* Motherboard peripherals: the wiring is the same but the 558 * addresses vary between the legacy and A-Series memory maps. 559 */ 560 561 sys_id = 0x1190f500; 562 563 sysctl = qdev_create(NULL, "realview_sysctl"); 564 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 565 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 566 qdev_prop_set_uint32(sysctl, "len-db-voltage", 567 daughterboard->num_voltage_sensors); 568 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 569 char *propname = g_strdup_printf("db-voltage[%d]", i); 570 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 571 g_free(propname); 572 } 573 qdev_prop_set_uint32(sysctl, "len-db-clock", 574 daughterboard->num_clocks); 575 for (i = 0; i < daughterboard->num_clocks; i++) { 576 char *propname = g_strdup_printf("db-clock[%d]", i); 577 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 578 g_free(propname); 579 } 580 qdev_init_nofail(sysctl); 581 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 582 583 /* VE_SP810: not modelled */ 584 /* VE_SERIALPCI: not modelled */ 585 586 pl041 = qdev_create(NULL, "pl041"); 587 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 588 qdev_init_nofail(pl041); 589 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 590 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 591 592 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 593 /* Wire up MMC card detect and read-only signals */ 594 qdev_connect_gpio_out(dev, 0, 595 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 596 qdev_connect_gpio_out(dev, 1, 597 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 598 599 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 600 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 601 602 sysbus_create_simple("pl011", map[VE_UART0], pic[5]); 603 sysbus_create_simple("pl011", map[VE_UART1], pic[6]); 604 sysbus_create_simple("pl011", map[VE_UART2], pic[7]); 605 sysbus_create_simple("pl011", map[VE_UART3], pic[8]); 606 607 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 608 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 609 610 /* VE_SERIALDVI: not modelled */ 611 612 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 613 614 /* VE_COMPACTFLASH: not modelled */ 615 616 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 617 618 dinfo = drive_get_next(IF_PFLASH); 619 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 620 dinfo); 621 if (!pflash0) { 622 fprintf(stderr, "vexpress: error registering flash 0.\n"); 623 exit(1); 624 } 625 626 if (map[VE_NORFLASHALIAS] != -1) { 627 /* Map flash 0 as an alias into low memory */ 628 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 629 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 630 flash0mem, 0, VEXPRESS_FLASH_SIZE); 631 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 632 } 633 634 dinfo = drive_get_next(IF_PFLASH); 635 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 636 dinfo)) { 637 fprintf(stderr, "vexpress: error registering flash 1.\n"); 638 exit(1); 639 } 640 641 sram_size = 0x2000000; 642 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, 643 &error_abort); 644 vmstate_register_ram_global(sram); 645 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 646 647 vram_size = 0x800000; 648 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, 649 &error_abort); 650 vmstate_register_ram_global(vram); 651 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 652 653 /* 0x4e000000 LAN9118 Ethernet */ 654 if (nd_table[0].used) { 655 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 656 } 657 658 /* VE_USB: not modelled */ 659 660 /* VE_DAPROM: not modelled */ 661 662 /* Create mmio transports, so the user can create virtio backends 663 * (which will be automatically plugged in to the transports). If 664 * no backend is created the transport will just sit harmlessly idle. 665 */ 666 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 667 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 668 pic[40 + i]); 669 } 670 671 daughterboard->bootinfo.ram_size = machine->ram_size; 672 daughterboard->bootinfo.kernel_filename = machine->kernel_filename; 673 daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline; 674 daughterboard->bootinfo.initrd_filename = machine->initrd_filename; 675 daughterboard->bootinfo.nb_cpus = smp_cpus; 676 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 677 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 678 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 679 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 680 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 681 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 682 arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); 683 } 684 685 static void vexpress_a9_init(MachineState *machine) 686 { 687 vexpress_common_init(&a9_daughterboard, machine); 688 } 689 690 static void vexpress_a15_init(MachineState *machine) 691 { 692 vexpress_common_init(&a15_daughterboard, machine); 693 } 694 695 static QEMUMachine vexpress_a9_machine = { 696 .name = "vexpress-a9", 697 .desc = "ARM Versatile Express for Cortex-A9", 698 .init = vexpress_a9_init, 699 .block_default_type = IF_SCSI, 700 .max_cpus = 4, 701 }; 702 703 static QEMUMachine vexpress_a15_machine = { 704 .name = "vexpress-a15", 705 .desc = "ARM Versatile Express for Cortex-A15", 706 .init = vexpress_a15_init, 707 .block_default_type = IF_SCSI, 708 .max_cpus = 4, 709 }; 710 711 static void vexpress_machine_init(void) 712 { 713 qemu_register_machine(&vexpress_a9_machine); 714 qemu_register_machine(&vexpress_a15_machine); 715 } 716 717 machine_init(vexpress_machine_init); 718