1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "hw/sysbus.h" 25 #include "hw/arm/arm.h" 26 #include "hw/arm/primecell.h" 27 #include "hw/devices.h" 28 #include "net/net.h" 29 #include "sysemu/sysemu.h" 30 #include "hw/boards.h" 31 #include "hw/loader.h" 32 #include "exec/address-spaces.h" 33 #include "sysemu/block-backend.h" 34 #include "hw/block/flash.h" 35 #include "sysemu/device_tree.h" 36 #include "qemu/error-report.h" 37 #include <libfdt.h> 38 39 #define VEXPRESS_BOARD_ID 0x8e0 40 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 41 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 42 43 /* Number of virtio transports to create (0..8; limited by 44 * number of available IRQ lines). 45 */ 46 #define NUM_VIRTIO_TRANSPORTS 4 47 48 /* Address maps for peripherals: 49 * the Versatile Express motherboard has two possible maps, 50 * the "legacy" one (used for A9) and the "Cortex-A Series" 51 * map (used for newer cores). 52 * Individual daughterboards can also have different maps for 53 * their peripherals. 54 */ 55 56 enum { 57 VE_SYSREGS, 58 VE_SP810, 59 VE_SERIALPCI, 60 VE_PL041, 61 VE_MMCI, 62 VE_KMI0, 63 VE_KMI1, 64 VE_UART0, 65 VE_UART1, 66 VE_UART2, 67 VE_UART3, 68 VE_WDT, 69 VE_TIMER01, 70 VE_TIMER23, 71 VE_SERIALDVI, 72 VE_RTC, 73 VE_COMPACTFLASH, 74 VE_CLCD, 75 VE_NORFLASH0, 76 VE_NORFLASH1, 77 VE_NORFLASHALIAS, 78 VE_SRAM, 79 VE_VIDEORAM, 80 VE_ETHERNET, 81 VE_USB, 82 VE_DAPROM, 83 VE_VIRTIO, 84 }; 85 86 static hwaddr motherboard_legacy_map[] = { 87 [VE_NORFLASHALIAS] = 0, 88 /* CS7: 0x10000000 .. 0x10020000 */ 89 [VE_SYSREGS] = 0x10000000, 90 [VE_SP810] = 0x10001000, 91 [VE_SERIALPCI] = 0x10002000, 92 [VE_PL041] = 0x10004000, 93 [VE_MMCI] = 0x10005000, 94 [VE_KMI0] = 0x10006000, 95 [VE_KMI1] = 0x10007000, 96 [VE_UART0] = 0x10009000, 97 [VE_UART1] = 0x1000a000, 98 [VE_UART2] = 0x1000b000, 99 [VE_UART3] = 0x1000c000, 100 [VE_WDT] = 0x1000f000, 101 [VE_TIMER01] = 0x10011000, 102 [VE_TIMER23] = 0x10012000, 103 [VE_VIRTIO] = 0x10013000, 104 [VE_SERIALDVI] = 0x10016000, 105 [VE_RTC] = 0x10017000, 106 [VE_COMPACTFLASH] = 0x1001a000, 107 [VE_CLCD] = 0x1001f000, 108 /* CS0: 0x40000000 .. 0x44000000 */ 109 [VE_NORFLASH0] = 0x40000000, 110 /* CS1: 0x44000000 .. 0x48000000 */ 111 [VE_NORFLASH1] = 0x44000000, 112 /* CS2: 0x48000000 .. 0x4a000000 */ 113 [VE_SRAM] = 0x48000000, 114 /* CS3: 0x4c000000 .. 0x50000000 */ 115 [VE_VIDEORAM] = 0x4c000000, 116 [VE_ETHERNET] = 0x4e000000, 117 [VE_USB] = 0x4f000000, 118 }; 119 120 static hwaddr motherboard_aseries_map[] = { 121 [VE_NORFLASHALIAS] = 0, 122 /* CS0: 0x08000000 .. 0x0c000000 */ 123 [VE_NORFLASH0] = 0x08000000, 124 /* CS4: 0x0c000000 .. 0x10000000 */ 125 [VE_NORFLASH1] = 0x0c000000, 126 /* CS5: 0x10000000 .. 0x14000000 */ 127 /* CS1: 0x14000000 .. 0x18000000 */ 128 [VE_SRAM] = 0x14000000, 129 /* CS2: 0x18000000 .. 0x1c000000 */ 130 [VE_VIDEORAM] = 0x18000000, 131 [VE_ETHERNET] = 0x1a000000, 132 [VE_USB] = 0x1b000000, 133 /* CS3: 0x1c000000 .. 0x20000000 */ 134 [VE_DAPROM] = 0x1c000000, 135 [VE_SYSREGS] = 0x1c010000, 136 [VE_SP810] = 0x1c020000, 137 [VE_SERIALPCI] = 0x1c030000, 138 [VE_PL041] = 0x1c040000, 139 [VE_MMCI] = 0x1c050000, 140 [VE_KMI0] = 0x1c060000, 141 [VE_KMI1] = 0x1c070000, 142 [VE_UART0] = 0x1c090000, 143 [VE_UART1] = 0x1c0a0000, 144 [VE_UART2] = 0x1c0b0000, 145 [VE_UART3] = 0x1c0c0000, 146 [VE_WDT] = 0x1c0f0000, 147 [VE_TIMER01] = 0x1c110000, 148 [VE_TIMER23] = 0x1c120000, 149 [VE_VIRTIO] = 0x1c130000, 150 [VE_SERIALDVI] = 0x1c160000, 151 [VE_RTC] = 0x1c170000, 152 [VE_COMPACTFLASH] = 0x1c1a0000, 153 [VE_CLCD] = 0x1c1f0000, 154 }; 155 156 /* Structure defining the peculiarities of a specific daughterboard */ 157 158 typedef struct VEDBoardInfo VEDBoardInfo; 159 160 typedef struct { 161 MachineClass parent; 162 VEDBoardInfo *daughterboard; 163 } VexpressMachineClass; 164 165 typedef struct { 166 MachineState parent; 167 bool secure; 168 } VexpressMachineState; 169 170 #define TYPE_VEXPRESS_MACHINE "vexpress" 171 #define TYPE_VEXPRESS_A9_MACHINE "vexpress-a9" 172 #define TYPE_VEXPRESS_A15_MACHINE "vexpress-a15" 173 #define VEXPRESS_MACHINE(obj) \ 174 OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE) 175 #define VEXPRESS_MACHINE_GET_CLASS(obj) \ 176 OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE) 177 #define VEXPRESS_MACHINE_CLASS(klass) \ 178 OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE) 179 180 typedef void DBoardInitFn(const VexpressMachineState *machine, 181 ram_addr_t ram_size, 182 const char *cpu_model, 183 qemu_irq *pic); 184 185 struct VEDBoardInfo { 186 struct arm_boot_info bootinfo; 187 const hwaddr *motherboard_map; 188 hwaddr loader_start; 189 const hwaddr gic_cpu_if_addr; 190 uint32_t proc_id; 191 uint32_t num_voltage_sensors; 192 const uint32_t *voltages; 193 uint32_t num_clocks; 194 const uint32_t *clocks; 195 DBoardInitFn *init; 196 }; 197 198 static void init_cpus(const char *cpu_model, const char *privdev, 199 hwaddr periphbase, qemu_irq *pic) 200 { 201 ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 202 DeviceState *dev; 203 SysBusDevice *busdev; 204 int n; 205 206 if (!cpu_oc) { 207 fprintf(stderr, "Unable to find CPU definition\n"); 208 exit(1); 209 } 210 211 /* Create the actual CPUs */ 212 for (n = 0; n < smp_cpus; n++) { 213 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 214 Error *err = NULL; 215 216 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 217 object_property_set_int(cpuobj, periphbase, 218 "reset-cbar", &error_abort); 219 } 220 object_property_set_bool(cpuobj, true, "realized", &err); 221 if (err) { 222 error_report("%s", error_get_pretty(err)); 223 exit(1); 224 } 225 } 226 227 /* Create the private peripheral devices (including the GIC); 228 * this must happen after the CPUs are created because a15mpcore_priv 229 * wires itself up to the CPU's generic_timer gpio out lines. 230 */ 231 dev = qdev_create(NULL, privdev); 232 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 233 qdev_init_nofail(dev); 234 busdev = SYS_BUS_DEVICE(dev); 235 sysbus_mmio_map(busdev, 0, periphbase); 236 237 /* Interrupts [42:0] are from the motherboard; 238 * [47:43] are reserved; [63:48] are daughterboard 239 * peripherals. Note that some documentation numbers 240 * external interrupts starting from 32 (because there 241 * are internal interrupts 0..31). 242 */ 243 for (n = 0; n < 64; n++) { 244 pic[n] = qdev_get_gpio_in(dev, n); 245 } 246 247 /* Connect the CPUs to the GIC */ 248 for (n = 0; n < smp_cpus; n++) { 249 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 250 251 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 252 } 253 } 254 255 static void a9_daughterboard_init(const VexpressMachineState *vms, 256 ram_addr_t ram_size, 257 const char *cpu_model, 258 qemu_irq *pic) 259 { 260 MemoryRegion *sysmem = get_system_memory(); 261 MemoryRegion *ram = g_new(MemoryRegion, 1); 262 MemoryRegion *lowram = g_new(MemoryRegion, 1); 263 ram_addr_t low_ram_size; 264 265 if (!cpu_model) { 266 cpu_model = "cortex-a9"; 267 } 268 269 if (ram_size > 0x40000000) { 270 /* 1GB is the maximum the address space permits */ 271 fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); 272 exit(1); 273 } 274 275 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size, 276 &error_abort); 277 vmstate_register_ram_global(ram); 278 low_ram_size = ram_size; 279 if (low_ram_size > 0x4000000) { 280 low_ram_size = 0x4000000; 281 } 282 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 283 * address space should in theory be remappable to various 284 * things including ROM or RAM; we always map the RAM there. 285 */ 286 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 287 memory_region_add_subregion(sysmem, 0x0, lowram); 288 memory_region_add_subregion(sysmem, 0x60000000, ram); 289 290 /* 0x1e000000 A9MPCore (SCU) private memory region */ 291 init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic); 292 293 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 294 295 /* 0x10020000 PL111 CLCD (daughterboard) */ 296 sysbus_create_simple("pl111", 0x10020000, pic[44]); 297 298 /* 0x10060000 AXI RAM */ 299 /* 0x100e0000 PL341 Dynamic Memory Controller */ 300 /* 0x100e1000 PL354 Static Memory Controller */ 301 /* 0x100e2000 System Configuration Controller */ 302 303 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 304 /* 0x100e5000 SP805 Watchdog module */ 305 /* 0x100e6000 BP147 TrustZone Protection Controller */ 306 /* 0x100e9000 PL301 'Fast' AXI matrix */ 307 /* 0x100ea000 PL301 'Slow' AXI matrix */ 308 /* 0x100ec000 TrustZone Address Space Controller */ 309 /* 0x10200000 CoreSight debug APB */ 310 /* 0x1e00a000 PL310 L2 Cache Controller */ 311 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 312 } 313 314 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 315 * values are in microvolts. 316 */ 317 static const uint32_t a9_voltages[] = { 318 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 319 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 320 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 321 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 322 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 323 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 324 }; 325 326 /* Reset values for daughterboard oscillators (in Hz) */ 327 static const uint32_t a9_clocks[] = { 328 45000000, /* AMBA AXI ACLK: 45MHz */ 329 23750000, /* daughterboard CLCD clock: 23.75MHz */ 330 66670000, /* Test chip reference clock: 66.67MHz */ 331 }; 332 333 static VEDBoardInfo a9_daughterboard = { 334 .motherboard_map = motherboard_legacy_map, 335 .loader_start = 0x60000000, 336 .gic_cpu_if_addr = 0x1e000100, 337 .proc_id = 0x0c000191, 338 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 339 .voltages = a9_voltages, 340 .num_clocks = ARRAY_SIZE(a9_clocks), 341 .clocks = a9_clocks, 342 .init = a9_daughterboard_init, 343 }; 344 345 static void a15_daughterboard_init(const VexpressMachineState *vms, 346 ram_addr_t ram_size, 347 const char *cpu_model, 348 qemu_irq *pic) 349 { 350 MemoryRegion *sysmem = get_system_memory(); 351 MemoryRegion *ram = g_new(MemoryRegion, 1); 352 MemoryRegion *sram = g_new(MemoryRegion, 1); 353 354 if (!cpu_model) { 355 cpu_model = "cortex-a15"; 356 } 357 358 { 359 /* We have to use a separate 64 bit variable here to avoid the gcc 360 * "comparison is always false due to limited range of data type" 361 * warning if we are on a host where ram_addr_t is 32 bits. 362 */ 363 uint64_t rsz = ram_size; 364 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 365 fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); 366 exit(1); 367 } 368 } 369 370 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size, 371 &error_abort); 372 vmstate_register_ram_global(ram); 373 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 374 memory_region_add_subregion(sysmem, 0x80000000, ram); 375 376 /* 0x2c000000 A15MPCore private memory region (GIC) */ 377 init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic); 378 379 /* A15 daughterboard peripherals: */ 380 381 /* 0x20000000: CoreSight interfaces: not modelled */ 382 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 383 /* 0x2a420000: SCC: not modelled */ 384 /* 0x2a430000: system counter: not modelled */ 385 /* 0x2b000000: HDLCD controller: not modelled */ 386 /* 0x2b060000: SP805 watchdog: not modelled */ 387 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 388 /* 0x2e000000: system SRAM */ 389 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, 390 &error_abort); 391 vmstate_register_ram_global(sram); 392 memory_region_add_subregion(sysmem, 0x2e000000, sram); 393 394 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 395 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 396 } 397 398 static const uint32_t a15_voltages[] = { 399 900000, /* Vcore: 0.9V : CPU core voltage */ 400 }; 401 402 static const uint32_t a15_clocks[] = { 403 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 404 0, /* OSCCLK1: reserved */ 405 0, /* OSCCLK2: reserved */ 406 0, /* OSCCLK3: reserved */ 407 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 408 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 409 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 410 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 411 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 412 }; 413 414 static VEDBoardInfo a15_daughterboard = { 415 .motherboard_map = motherboard_aseries_map, 416 .loader_start = 0x80000000, 417 .gic_cpu_if_addr = 0x2c002000, 418 .proc_id = 0x14000237, 419 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 420 .voltages = a15_voltages, 421 .num_clocks = ARRAY_SIZE(a15_clocks), 422 .clocks = a15_clocks, 423 .init = a15_daughterboard_init, 424 }; 425 426 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 427 hwaddr addr, hwaddr size, uint32_t intc, 428 int irq) 429 { 430 /* Add a virtio_mmio node to the device tree blob: 431 * virtio_mmio@ADDRESS { 432 * compatible = "virtio,mmio"; 433 * reg = <ADDRESS, SIZE>; 434 * interrupt-parent = <&intc>; 435 * interrupts = <0, irq, 1>; 436 * } 437 * (Note that the format of the interrupts property is dependent on the 438 * interrupt controller that interrupt-parent points to; these are for 439 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 440 */ 441 int rc; 442 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 443 444 rc = qemu_fdt_add_subnode(fdt, nodename); 445 rc |= qemu_fdt_setprop_string(fdt, nodename, 446 "compatible", "virtio,mmio"); 447 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 448 acells, addr, scells, size); 449 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 450 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 451 g_free(nodename); 452 if (rc) { 453 return -1; 454 } 455 return 0; 456 } 457 458 static uint32_t find_int_controller(void *fdt) 459 { 460 /* Find the FDT node corresponding to the interrupt controller 461 * for virtio-mmio devices. We do this by scanning the fdt for 462 * a node with the right compatibility, since we know there is 463 * only one GIC on a vexpress board. 464 * We return the phandle of the node, or 0 if none was found. 465 */ 466 const char *compat = "arm,cortex-a9-gic"; 467 int offset; 468 469 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 470 if (offset >= 0) { 471 return fdt_get_phandle(fdt, offset); 472 } 473 return 0; 474 } 475 476 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 477 { 478 uint32_t acells, scells, intc; 479 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 480 481 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells"); 482 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells"); 483 intc = find_int_controller(fdt); 484 if (!intc) { 485 /* Not fatal, we just won't provide virtio. This will 486 * happen with older device tree blobs. 487 */ 488 fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in " 489 "dtb; will not include virtio-mmio devices in the dtb.\n"); 490 } else { 491 int i; 492 const hwaddr *map = daughterboard->motherboard_map; 493 494 /* We iterate backwards here because adding nodes 495 * to the dtb puts them in last-first. 496 */ 497 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 498 add_virtio_mmio_node(fdt, acells, scells, 499 map[VE_VIRTIO] + 0x200 * i, 500 0x200, intc, 40 + i); 501 } 502 } 503 } 504 505 506 /* Open code a private version of pflash registration since we 507 * need to set non-default device width for VExpress platform. 508 */ 509 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, 510 DriveInfo *di) 511 { 512 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 513 514 if (di && qdev_prop_set_drive(dev, "drive", 515 blk_by_legacy_dinfo(di))) { 516 abort(); 517 } 518 519 qdev_prop_set_uint32(dev, "num-blocks", 520 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 521 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 522 qdev_prop_set_uint8(dev, "width", 4); 523 qdev_prop_set_uint8(dev, "device-width", 2); 524 qdev_prop_set_uint8(dev, "big-endian", 0); 525 qdev_prop_set_uint16(dev, "id0", 0x89); 526 qdev_prop_set_uint16(dev, "id1", 0x18); 527 qdev_prop_set_uint16(dev, "id2", 0x00); 528 qdev_prop_set_uint16(dev, "id3", 0x00); 529 qdev_prop_set_string(dev, "name", name); 530 qdev_init_nofail(dev); 531 532 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 533 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 534 } 535 536 static void vexpress_common_init(MachineState *machine) 537 { 538 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 539 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 540 VEDBoardInfo *daughterboard = vmc->daughterboard;; 541 DeviceState *dev, *sysctl, *pl041; 542 qemu_irq pic[64]; 543 uint32_t sys_id; 544 DriveInfo *dinfo; 545 pflash_t *pflash0; 546 ram_addr_t vram_size, sram_size; 547 MemoryRegion *sysmem = get_system_memory(); 548 MemoryRegion *vram = g_new(MemoryRegion, 1); 549 MemoryRegion *sram = g_new(MemoryRegion, 1); 550 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 551 MemoryRegion *flash0mem; 552 const hwaddr *map = daughterboard->motherboard_map; 553 int i; 554 555 daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic); 556 557 /* 558 * If a bios file was provided, attempt to map it into memory 559 */ 560 if (bios_name) { 561 const char *fn; 562 563 if (drive_get(IF_PFLASH, 0, 0)) { 564 error_report("The contents of the first flash device may be " 565 "specified with -bios or with -drive if=pflash... " 566 "but you cannot use both options at once"); 567 exit(1); 568 } 569 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 570 if (!fn || load_image_targphys(fn, map[VE_NORFLASH0], 571 VEXPRESS_FLASH_SIZE) < 0) { 572 error_report("Could not load ROM image '%s'", bios_name); 573 exit(1); 574 } 575 } 576 577 /* Motherboard peripherals: the wiring is the same but the 578 * addresses vary between the legacy and A-Series memory maps. 579 */ 580 581 sys_id = 0x1190f500; 582 583 sysctl = qdev_create(NULL, "realview_sysctl"); 584 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 585 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 586 qdev_prop_set_uint32(sysctl, "len-db-voltage", 587 daughterboard->num_voltage_sensors); 588 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 589 char *propname = g_strdup_printf("db-voltage[%d]", i); 590 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 591 g_free(propname); 592 } 593 qdev_prop_set_uint32(sysctl, "len-db-clock", 594 daughterboard->num_clocks); 595 for (i = 0; i < daughterboard->num_clocks; i++) { 596 char *propname = g_strdup_printf("db-clock[%d]", i); 597 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 598 g_free(propname); 599 } 600 qdev_init_nofail(sysctl); 601 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 602 603 /* VE_SP810: not modelled */ 604 /* VE_SERIALPCI: not modelled */ 605 606 pl041 = qdev_create(NULL, "pl041"); 607 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 608 qdev_init_nofail(pl041); 609 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 610 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 611 612 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 613 /* Wire up MMC card detect and read-only signals */ 614 qdev_connect_gpio_out(dev, 0, 615 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 616 qdev_connect_gpio_out(dev, 1, 617 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 618 619 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 620 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 621 622 sysbus_create_simple("pl011", map[VE_UART0], pic[5]); 623 sysbus_create_simple("pl011", map[VE_UART1], pic[6]); 624 sysbus_create_simple("pl011", map[VE_UART2], pic[7]); 625 sysbus_create_simple("pl011", map[VE_UART3], pic[8]); 626 627 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 628 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 629 630 /* VE_SERIALDVI: not modelled */ 631 632 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 633 634 /* VE_COMPACTFLASH: not modelled */ 635 636 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 637 638 dinfo = drive_get_next(IF_PFLASH); 639 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 640 dinfo); 641 if (!pflash0) { 642 fprintf(stderr, "vexpress: error registering flash 0.\n"); 643 exit(1); 644 } 645 646 if (map[VE_NORFLASHALIAS] != -1) { 647 /* Map flash 0 as an alias into low memory */ 648 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 649 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 650 flash0mem, 0, VEXPRESS_FLASH_SIZE); 651 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 652 } 653 654 dinfo = drive_get_next(IF_PFLASH); 655 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 656 dinfo)) { 657 fprintf(stderr, "vexpress: error registering flash 1.\n"); 658 exit(1); 659 } 660 661 sram_size = 0x2000000; 662 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, 663 &error_abort); 664 vmstate_register_ram_global(sram); 665 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 666 667 vram_size = 0x800000; 668 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, 669 &error_abort); 670 vmstate_register_ram_global(vram); 671 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 672 673 /* 0x4e000000 LAN9118 Ethernet */ 674 if (nd_table[0].used) { 675 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 676 } 677 678 /* VE_USB: not modelled */ 679 680 /* VE_DAPROM: not modelled */ 681 682 /* Create mmio transports, so the user can create virtio backends 683 * (which will be automatically plugged in to the transports). If 684 * no backend is created the transport will just sit harmlessly idle. 685 */ 686 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 687 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 688 pic[40 + i]); 689 } 690 691 daughterboard->bootinfo.ram_size = machine->ram_size; 692 daughterboard->bootinfo.kernel_filename = machine->kernel_filename; 693 daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline; 694 daughterboard->bootinfo.initrd_filename = machine->initrd_filename; 695 daughterboard->bootinfo.nb_cpus = smp_cpus; 696 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 697 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 698 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 699 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 700 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 701 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 702 arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); 703 } 704 705 static bool vexpress_get_secure(Object *obj, Error **errp) 706 { 707 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 708 709 return vms->secure; 710 } 711 712 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 713 { 714 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 715 716 vms->secure = value; 717 } 718 719 static void vexpress_instance_init(Object *obj) 720 { 721 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 722 723 /* EL3 is enabled by default on vexpress */ 724 vms->secure = true; 725 object_property_add_bool(obj, "secure", vexpress_get_secure, 726 vexpress_set_secure, NULL); 727 object_property_set_description(obj, "secure", 728 "Set on/off to enable/disable the ARM " 729 "Security Extensions (TrustZone)", 730 NULL); 731 } 732 733 static void vexpress_class_init(ObjectClass *oc, void *data) 734 { 735 MachineClass *mc = MACHINE_CLASS(oc); 736 737 mc->name = TYPE_VEXPRESS_MACHINE; 738 mc->desc = "ARM Versatile Express"; 739 mc->init = vexpress_common_init; 740 mc->block_default_type = IF_SCSI; 741 mc->max_cpus = 4; 742 } 743 744 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 745 { 746 MachineClass *mc = MACHINE_CLASS(oc); 747 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 748 749 mc->name = TYPE_VEXPRESS_A9_MACHINE; 750 mc->desc = "ARM Versatile Express for Cortex-A9"; 751 752 vmc->daughterboard = &a9_daughterboard;; 753 } 754 755 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 756 { 757 MachineClass *mc = MACHINE_CLASS(oc); 758 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 759 760 mc->name = TYPE_VEXPRESS_A15_MACHINE; 761 mc->desc = "ARM Versatile Express for Cortex-A15"; 762 763 vmc->daughterboard = &a15_daughterboard; 764 } 765 766 static const TypeInfo vexpress_info = { 767 .name = TYPE_VEXPRESS_MACHINE, 768 .parent = TYPE_MACHINE, 769 .abstract = true, 770 .instance_size = sizeof(VexpressMachineState), 771 .instance_init = vexpress_instance_init, 772 .class_size = sizeof(VexpressMachineClass), 773 .class_init = vexpress_class_init, 774 }; 775 776 static const TypeInfo vexpress_a9_info = { 777 .name = TYPE_VEXPRESS_A9_MACHINE, 778 .parent = TYPE_VEXPRESS_MACHINE, 779 .class_init = vexpress_a9_class_init, 780 }; 781 782 static const TypeInfo vexpress_a15_info = { 783 .name = TYPE_VEXPRESS_A15_MACHINE, 784 .parent = TYPE_VEXPRESS_MACHINE, 785 .class_init = vexpress_a15_class_init, 786 }; 787 788 static void vexpress_machine_init(void) 789 { 790 type_register_static(&vexpress_info); 791 type_register_static(&vexpress_a9_info); 792 type_register_static(&vexpress_a15_info); 793 } 794 795 machine_init(vexpress_machine_init); 796