1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "hw/sysbus.h" 25 #include "hw/arm/arm.h" 26 #include "hw/arm/primecell.h" 27 #include "hw/devices.h" 28 #include "net/net.h" 29 #include "sysemu/sysemu.h" 30 #include "hw/boards.h" 31 #include "hw/loader.h" 32 #include "exec/address-spaces.h" 33 #include "sysemu/block-backend.h" 34 #include "hw/block/flash.h" 35 #include "sysemu/device_tree.h" 36 #include "qemu/error-report.h" 37 #include <libfdt.h> 38 39 #define VEXPRESS_BOARD_ID 0x8e0 40 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 41 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 42 43 /* Number of virtio transports to create (0..8; limited by 44 * number of available IRQ lines). 45 */ 46 #define NUM_VIRTIO_TRANSPORTS 4 47 48 /* Address maps for peripherals: 49 * the Versatile Express motherboard has two possible maps, 50 * the "legacy" one (used for A9) and the "Cortex-A Series" 51 * map (used for newer cores). 52 * Individual daughterboards can also have different maps for 53 * their peripherals. 54 */ 55 56 enum { 57 VE_SYSREGS, 58 VE_SP810, 59 VE_SERIALPCI, 60 VE_PL041, 61 VE_MMCI, 62 VE_KMI0, 63 VE_KMI1, 64 VE_UART0, 65 VE_UART1, 66 VE_UART2, 67 VE_UART3, 68 VE_WDT, 69 VE_TIMER01, 70 VE_TIMER23, 71 VE_SERIALDVI, 72 VE_RTC, 73 VE_COMPACTFLASH, 74 VE_CLCD, 75 VE_NORFLASH0, 76 VE_NORFLASH1, 77 VE_NORFLASHALIAS, 78 VE_SRAM, 79 VE_VIDEORAM, 80 VE_ETHERNET, 81 VE_USB, 82 VE_DAPROM, 83 VE_VIRTIO, 84 }; 85 86 static hwaddr motherboard_legacy_map[] = { 87 [VE_NORFLASHALIAS] = 0, 88 /* CS7: 0x10000000 .. 0x10020000 */ 89 [VE_SYSREGS] = 0x10000000, 90 [VE_SP810] = 0x10001000, 91 [VE_SERIALPCI] = 0x10002000, 92 [VE_PL041] = 0x10004000, 93 [VE_MMCI] = 0x10005000, 94 [VE_KMI0] = 0x10006000, 95 [VE_KMI1] = 0x10007000, 96 [VE_UART0] = 0x10009000, 97 [VE_UART1] = 0x1000a000, 98 [VE_UART2] = 0x1000b000, 99 [VE_UART3] = 0x1000c000, 100 [VE_WDT] = 0x1000f000, 101 [VE_TIMER01] = 0x10011000, 102 [VE_TIMER23] = 0x10012000, 103 [VE_VIRTIO] = 0x10013000, 104 [VE_SERIALDVI] = 0x10016000, 105 [VE_RTC] = 0x10017000, 106 [VE_COMPACTFLASH] = 0x1001a000, 107 [VE_CLCD] = 0x1001f000, 108 /* CS0: 0x40000000 .. 0x44000000 */ 109 [VE_NORFLASH0] = 0x40000000, 110 /* CS1: 0x44000000 .. 0x48000000 */ 111 [VE_NORFLASH1] = 0x44000000, 112 /* CS2: 0x48000000 .. 0x4a000000 */ 113 [VE_SRAM] = 0x48000000, 114 /* CS3: 0x4c000000 .. 0x50000000 */ 115 [VE_VIDEORAM] = 0x4c000000, 116 [VE_ETHERNET] = 0x4e000000, 117 [VE_USB] = 0x4f000000, 118 }; 119 120 static hwaddr motherboard_aseries_map[] = { 121 [VE_NORFLASHALIAS] = 0, 122 /* CS0: 0x08000000 .. 0x0c000000 */ 123 [VE_NORFLASH0] = 0x08000000, 124 /* CS4: 0x0c000000 .. 0x10000000 */ 125 [VE_NORFLASH1] = 0x0c000000, 126 /* CS5: 0x10000000 .. 0x14000000 */ 127 /* CS1: 0x14000000 .. 0x18000000 */ 128 [VE_SRAM] = 0x14000000, 129 /* CS2: 0x18000000 .. 0x1c000000 */ 130 [VE_VIDEORAM] = 0x18000000, 131 [VE_ETHERNET] = 0x1a000000, 132 [VE_USB] = 0x1b000000, 133 /* CS3: 0x1c000000 .. 0x20000000 */ 134 [VE_DAPROM] = 0x1c000000, 135 [VE_SYSREGS] = 0x1c010000, 136 [VE_SP810] = 0x1c020000, 137 [VE_SERIALPCI] = 0x1c030000, 138 [VE_PL041] = 0x1c040000, 139 [VE_MMCI] = 0x1c050000, 140 [VE_KMI0] = 0x1c060000, 141 [VE_KMI1] = 0x1c070000, 142 [VE_UART0] = 0x1c090000, 143 [VE_UART1] = 0x1c0a0000, 144 [VE_UART2] = 0x1c0b0000, 145 [VE_UART3] = 0x1c0c0000, 146 [VE_WDT] = 0x1c0f0000, 147 [VE_TIMER01] = 0x1c110000, 148 [VE_TIMER23] = 0x1c120000, 149 [VE_VIRTIO] = 0x1c130000, 150 [VE_SERIALDVI] = 0x1c160000, 151 [VE_RTC] = 0x1c170000, 152 [VE_COMPACTFLASH] = 0x1c1a0000, 153 [VE_CLCD] = 0x1c1f0000, 154 }; 155 156 /* Structure defining the peculiarities of a specific daughterboard */ 157 158 typedef struct VEDBoardInfo VEDBoardInfo; 159 160 typedef struct { 161 MachineClass parent; 162 VEDBoardInfo *daughterboard; 163 } VexpressMachineClass; 164 165 typedef struct { 166 MachineState parent; 167 } VexpressMachineState; 168 169 #define TYPE_VEXPRESS_MACHINE "vexpress" 170 #define TYPE_VEXPRESS_A9_MACHINE "vexpress-a9" 171 #define TYPE_VEXPRESS_A15_MACHINE "vexpress-a15" 172 #define VEXPRESS_MACHINE(obj) \ 173 OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE) 174 #define VEXPRESS_MACHINE_GET_CLASS(obj) \ 175 OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE) 176 #define VEXPRESS_MACHINE_CLASS(klass) \ 177 OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE) 178 179 typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, 180 ram_addr_t ram_size, 181 const char *cpu_model, 182 qemu_irq *pic); 183 184 struct VEDBoardInfo { 185 struct arm_boot_info bootinfo; 186 const hwaddr *motherboard_map; 187 hwaddr loader_start; 188 const hwaddr gic_cpu_if_addr; 189 uint32_t proc_id; 190 uint32_t num_voltage_sensors; 191 const uint32_t *voltages; 192 uint32_t num_clocks; 193 const uint32_t *clocks; 194 DBoardInitFn *init; 195 }; 196 197 static void init_cpus(const char *cpu_model, const char *privdev, 198 hwaddr periphbase, qemu_irq *pic) 199 { 200 ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 201 DeviceState *dev; 202 SysBusDevice *busdev; 203 int n; 204 205 if (!cpu_oc) { 206 fprintf(stderr, "Unable to find CPU definition\n"); 207 exit(1); 208 } 209 210 /* Create the actual CPUs */ 211 for (n = 0; n < smp_cpus; n++) { 212 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 213 Error *err = NULL; 214 215 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 216 object_property_set_int(cpuobj, periphbase, 217 "reset-cbar", &error_abort); 218 } 219 object_property_set_bool(cpuobj, true, "realized", &err); 220 if (err) { 221 error_report("%s", error_get_pretty(err)); 222 exit(1); 223 } 224 } 225 226 /* Create the private peripheral devices (including the GIC); 227 * this must happen after the CPUs are created because a15mpcore_priv 228 * wires itself up to the CPU's generic_timer gpio out lines. 229 */ 230 dev = qdev_create(NULL, privdev); 231 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 232 qdev_init_nofail(dev); 233 busdev = SYS_BUS_DEVICE(dev); 234 sysbus_mmio_map(busdev, 0, periphbase); 235 236 /* Interrupts [42:0] are from the motherboard; 237 * [47:43] are reserved; [63:48] are daughterboard 238 * peripherals. Note that some documentation numbers 239 * external interrupts starting from 32 (because there 240 * are internal interrupts 0..31). 241 */ 242 for (n = 0; n < 64; n++) { 243 pic[n] = qdev_get_gpio_in(dev, n); 244 } 245 246 /* Connect the CPUs to the GIC */ 247 for (n = 0; n < smp_cpus; n++) { 248 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 249 250 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 251 } 252 } 253 254 static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, 255 ram_addr_t ram_size, 256 const char *cpu_model, 257 qemu_irq *pic) 258 { 259 MemoryRegion *sysmem = get_system_memory(); 260 MemoryRegion *ram = g_new(MemoryRegion, 1); 261 MemoryRegion *lowram = g_new(MemoryRegion, 1); 262 ram_addr_t low_ram_size; 263 264 if (!cpu_model) { 265 cpu_model = "cortex-a9"; 266 } 267 268 if (ram_size > 0x40000000) { 269 /* 1GB is the maximum the address space permits */ 270 fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); 271 exit(1); 272 } 273 274 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size, 275 &error_abort); 276 vmstate_register_ram_global(ram); 277 low_ram_size = ram_size; 278 if (low_ram_size > 0x4000000) { 279 low_ram_size = 0x4000000; 280 } 281 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 282 * address space should in theory be remappable to various 283 * things including ROM or RAM; we always map the RAM there. 284 */ 285 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 286 memory_region_add_subregion(sysmem, 0x0, lowram); 287 memory_region_add_subregion(sysmem, 0x60000000, ram); 288 289 /* 0x1e000000 A9MPCore (SCU) private memory region */ 290 init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic); 291 292 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 293 294 /* 0x10020000 PL111 CLCD (daughterboard) */ 295 sysbus_create_simple("pl111", 0x10020000, pic[44]); 296 297 /* 0x10060000 AXI RAM */ 298 /* 0x100e0000 PL341 Dynamic Memory Controller */ 299 /* 0x100e1000 PL354 Static Memory Controller */ 300 /* 0x100e2000 System Configuration Controller */ 301 302 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 303 /* 0x100e5000 SP805 Watchdog module */ 304 /* 0x100e6000 BP147 TrustZone Protection Controller */ 305 /* 0x100e9000 PL301 'Fast' AXI matrix */ 306 /* 0x100ea000 PL301 'Slow' AXI matrix */ 307 /* 0x100ec000 TrustZone Address Space Controller */ 308 /* 0x10200000 CoreSight debug APB */ 309 /* 0x1e00a000 PL310 L2 Cache Controller */ 310 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 311 } 312 313 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 314 * values are in microvolts. 315 */ 316 static const uint32_t a9_voltages[] = { 317 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 318 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 319 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 320 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 321 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 322 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 323 }; 324 325 /* Reset values for daughterboard oscillators (in Hz) */ 326 static const uint32_t a9_clocks[] = { 327 45000000, /* AMBA AXI ACLK: 45MHz */ 328 23750000, /* daughterboard CLCD clock: 23.75MHz */ 329 66670000, /* Test chip reference clock: 66.67MHz */ 330 }; 331 332 static VEDBoardInfo a9_daughterboard = { 333 .motherboard_map = motherboard_legacy_map, 334 .loader_start = 0x60000000, 335 .gic_cpu_if_addr = 0x1e000100, 336 .proc_id = 0x0c000191, 337 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 338 .voltages = a9_voltages, 339 .num_clocks = ARRAY_SIZE(a9_clocks), 340 .clocks = a9_clocks, 341 .init = a9_daughterboard_init, 342 }; 343 344 static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, 345 ram_addr_t ram_size, 346 const char *cpu_model, 347 qemu_irq *pic) 348 { 349 MemoryRegion *sysmem = get_system_memory(); 350 MemoryRegion *ram = g_new(MemoryRegion, 1); 351 MemoryRegion *sram = g_new(MemoryRegion, 1); 352 353 if (!cpu_model) { 354 cpu_model = "cortex-a15"; 355 } 356 357 { 358 /* We have to use a separate 64 bit variable here to avoid the gcc 359 * "comparison is always false due to limited range of data type" 360 * warning if we are on a host where ram_addr_t is 32 bits. 361 */ 362 uint64_t rsz = ram_size; 363 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 364 fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); 365 exit(1); 366 } 367 } 368 369 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size, 370 &error_abort); 371 vmstate_register_ram_global(ram); 372 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 373 memory_region_add_subregion(sysmem, 0x80000000, ram); 374 375 /* 0x2c000000 A15MPCore private memory region (GIC) */ 376 init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic); 377 378 /* A15 daughterboard peripherals: */ 379 380 /* 0x20000000: CoreSight interfaces: not modelled */ 381 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 382 /* 0x2a420000: SCC: not modelled */ 383 /* 0x2a430000: system counter: not modelled */ 384 /* 0x2b000000: HDLCD controller: not modelled */ 385 /* 0x2b060000: SP805 watchdog: not modelled */ 386 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 387 /* 0x2e000000: system SRAM */ 388 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, 389 &error_abort); 390 vmstate_register_ram_global(sram); 391 memory_region_add_subregion(sysmem, 0x2e000000, sram); 392 393 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 394 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 395 } 396 397 static const uint32_t a15_voltages[] = { 398 900000, /* Vcore: 0.9V : CPU core voltage */ 399 }; 400 401 static const uint32_t a15_clocks[] = { 402 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 403 0, /* OSCCLK1: reserved */ 404 0, /* OSCCLK2: reserved */ 405 0, /* OSCCLK3: reserved */ 406 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 407 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 408 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 409 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 410 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 411 }; 412 413 static VEDBoardInfo a15_daughterboard = { 414 .motherboard_map = motherboard_aseries_map, 415 .loader_start = 0x80000000, 416 .gic_cpu_if_addr = 0x2c002000, 417 .proc_id = 0x14000237, 418 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 419 .voltages = a15_voltages, 420 .num_clocks = ARRAY_SIZE(a15_clocks), 421 .clocks = a15_clocks, 422 .init = a15_daughterboard_init, 423 }; 424 425 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 426 hwaddr addr, hwaddr size, uint32_t intc, 427 int irq) 428 { 429 /* Add a virtio_mmio node to the device tree blob: 430 * virtio_mmio@ADDRESS { 431 * compatible = "virtio,mmio"; 432 * reg = <ADDRESS, SIZE>; 433 * interrupt-parent = <&intc>; 434 * interrupts = <0, irq, 1>; 435 * } 436 * (Note that the format of the interrupts property is dependent on the 437 * interrupt controller that interrupt-parent points to; these are for 438 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 439 */ 440 int rc; 441 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 442 443 rc = qemu_fdt_add_subnode(fdt, nodename); 444 rc |= qemu_fdt_setprop_string(fdt, nodename, 445 "compatible", "virtio,mmio"); 446 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 447 acells, addr, scells, size); 448 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 449 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 450 g_free(nodename); 451 if (rc) { 452 return -1; 453 } 454 return 0; 455 } 456 457 static uint32_t find_int_controller(void *fdt) 458 { 459 /* Find the FDT node corresponding to the interrupt controller 460 * for virtio-mmio devices. We do this by scanning the fdt for 461 * a node with the right compatibility, since we know there is 462 * only one GIC on a vexpress board. 463 * We return the phandle of the node, or 0 if none was found. 464 */ 465 const char *compat = "arm,cortex-a9-gic"; 466 int offset; 467 468 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 469 if (offset >= 0) { 470 return fdt_get_phandle(fdt, offset); 471 } 472 return 0; 473 } 474 475 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 476 { 477 uint32_t acells, scells, intc; 478 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 479 480 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells"); 481 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells"); 482 intc = find_int_controller(fdt); 483 if (!intc) { 484 /* Not fatal, we just won't provide virtio. This will 485 * happen with older device tree blobs. 486 */ 487 fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in " 488 "dtb; will not include virtio-mmio devices in the dtb.\n"); 489 } else { 490 int i; 491 const hwaddr *map = daughterboard->motherboard_map; 492 493 /* We iterate backwards here because adding nodes 494 * to the dtb puts them in last-first. 495 */ 496 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 497 add_virtio_mmio_node(fdt, acells, scells, 498 map[VE_VIRTIO] + 0x200 * i, 499 0x200, intc, 40 + i); 500 } 501 } 502 } 503 504 505 /* Open code a private version of pflash registration since we 506 * need to set non-default device width for VExpress platform. 507 */ 508 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, 509 DriveInfo *di) 510 { 511 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 512 513 if (di && qdev_prop_set_drive(dev, "drive", 514 blk_by_legacy_dinfo(di))) { 515 abort(); 516 } 517 518 qdev_prop_set_uint32(dev, "num-blocks", 519 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 520 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 521 qdev_prop_set_uint8(dev, "width", 4); 522 qdev_prop_set_uint8(dev, "device-width", 2); 523 qdev_prop_set_uint8(dev, "big-endian", 0); 524 qdev_prop_set_uint16(dev, "id0", 0x89); 525 qdev_prop_set_uint16(dev, "id1", 0x18); 526 qdev_prop_set_uint16(dev, "id2", 0x00); 527 qdev_prop_set_uint16(dev, "id3", 0x00); 528 qdev_prop_set_string(dev, "name", name); 529 qdev_init_nofail(dev); 530 531 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 532 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 533 } 534 535 static void vexpress_common_init(VEDBoardInfo *daughterboard, 536 MachineState *machine) 537 { 538 DeviceState *dev, *sysctl, *pl041; 539 qemu_irq pic[64]; 540 uint32_t sys_id; 541 DriveInfo *dinfo; 542 pflash_t *pflash0; 543 ram_addr_t vram_size, sram_size; 544 MemoryRegion *sysmem = get_system_memory(); 545 MemoryRegion *vram = g_new(MemoryRegion, 1); 546 MemoryRegion *sram = g_new(MemoryRegion, 1); 547 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 548 MemoryRegion *flash0mem; 549 const hwaddr *map = daughterboard->motherboard_map; 550 int i; 551 552 daughterboard->init(daughterboard, machine->ram_size, machine->cpu_model, 553 pic); 554 555 /* 556 * If a bios file was provided, attempt to map it into memory 557 */ 558 if (bios_name) { 559 const char *fn; 560 561 if (drive_get(IF_PFLASH, 0, 0)) { 562 error_report("The contents of the first flash device may be " 563 "specified with -bios or with -drive if=pflash... " 564 "but you cannot use both options at once"); 565 exit(1); 566 } 567 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 568 if (!fn || load_image_targphys(fn, map[VE_NORFLASH0], 569 VEXPRESS_FLASH_SIZE) < 0) { 570 error_report("Could not load ROM image '%s'", bios_name); 571 exit(1); 572 } 573 } 574 575 /* Motherboard peripherals: the wiring is the same but the 576 * addresses vary between the legacy and A-Series memory maps. 577 */ 578 579 sys_id = 0x1190f500; 580 581 sysctl = qdev_create(NULL, "realview_sysctl"); 582 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 583 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 584 qdev_prop_set_uint32(sysctl, "len-db-voltage", 585 daughterboard->num_voltage_sensors); 586 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 587 char *propname = g_strdup_printf("db-voltage[%d]", i); 588 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 589 g_free(propname); 590 } 591 qdev_prop_set_uint32(sysctl, "len-db-clock", 592 daughterboard->num_clocks); 593 for (i = 0; i < daughterboard->num_clocks; i++) { 594 char *propname = g_strdup_printf("db-clock[%d]", i); 595 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 596 g_free(propname); 597 } 598 qdev_init_nofail(sysctl); 599 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 600 601 /* VE_SP810: not modelled */ 602 /* VE_SERIALPCI: not modelled */ 603 604 pl041 = qdev_create(NULL, "pl041"); 605 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 606 qdev_init_nofail(pl041); 607 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 608 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 609 610 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 611 /* Wire up MMC card detect and read-only signals */ 612 qdev_connect_gpio_out(dev, 0, 613 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 614 qdev_connect_gpio_out(dev, 1, 615 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 616 617 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 618 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 619 620 sysbus_create_simple("pl011", map[VE_UART0], pic[5]); 621 sysbus_create_simple("pl011", map[VE_UART1], pic[6]); 622 sysbus_create_simple("pl011", map[VE_UART2], pic[7]); 623 sysbus_create_simple("pl011", map[VE_UART3], pic[8]); 624 625 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 626 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 627 628 /* VE_SERIALDVI: not modelled */ 629 630 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 631 632 /* VE_COMPACTFLASH: not modelled */ 633 634 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 635 636 dinfo = drive_get_next(IF_PFLASH); 637 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 638 dinfo); 639 if (!pflash0) { 640 fprintf(stderr, "vexpress: error registering flash 0.\n"); 641 exit(1); 642 } 643 644 if (map[VE_NORFLASHALIAS] != -1) { 645 /* Map flash 0 as an alias into low memory */ 646 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 647 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 648 flash0mem, 0, VEXPRESS_FLASH_SIZE); 649 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 650 } 651 652 dinfo = drive_get_next(IF_PFLASH); 653 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 654 dinfo)) { 655 fprintf(stderr, "vexpress: error registering flash 1.\n"); 656 exit(1); 657 } 658 659 sram_size = 0x2000000; 660 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, 661 &error_abort); 662 vmstate_register_ram_global(sram); 663 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 664 665 vram_size = 0x800000; 666 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, 667 &error_abort); 668 vmstate_register_ram_global(vram); 669 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 670 671 /* 0x4e000000 LAN9118 Ethernet */ 672 if (nd_table[0].used) { 673 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 674 } 675 676 /* VE_USB: not modelled */ 677 678 /* VE_DAPROM: not modelled */ 679 680 /* Create mmio transports, so the user can create virtio backends 681 * (which will be automatically plugged in to the transports). If 682 * no backend is created the transport will just sit harmlessly idle. 683 */ 684 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 685 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 686 pic[40 + i]); 687 } 688 689 daughterboard->bootinfo.ram_size = machine->ram_size; 690 daughterboard->bootinfo.kernel_filename = machine->kernel_filename; 691 daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline; 692 daughterboard->bootinfo.initrd_filename = machine->initrd_filename; 693 daughterboard->bootinfo.nb_cpus = smp_cpus; 694 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 695 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 696 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 697 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 698 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 699 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 700 arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); 701 } 702 703 static void vexpress_init(MachineState *machine) 704 { 705 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 706 707 vexpress_common_init(vmc->daughterboard, machine); 708 } 709 710 static void vexpress_a9_init(MachineState *machine) 711 { 712 vexpress_common_init(&a9_daughterboard, machine); 713 } 714 715 static void vexpress_a15_init(MachineState *machine) 716 { 717 vexpress_common_init(&a15_daughterboard, machine); 718 } 719 720 static void vexpress_class_init(ObjectClass *oc, void *data) 721 { 722 MachineClass *mc = MACHINE_CLASS(oc); 723 724 mc->name = TYPE_VEXPRESS_MACHINE; 725 mc->desc = "ARM Versatile Express"; 726 mc->init = vexpress_init; 727 mc->block_default_type = IF_SCSI; 728 mc->max_cpus = 4; 729 } 730 731 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 732 { 733 MachineClass *mc = MACHINE_CLASS(oc); 734 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 735 736 mc->name = TYPE_VEXPRESS_A9_MACHINE; 737 mc->desc = "ARM Versatile Express for Cortex-A9"; 738 mc->init = vexpress_a9_init; 739 740 vmc->daughterboard = &a9_daughterboard;; 741 } 742 743 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 744 { 745 MachineClass *mc = MACHINE_CLASS(oc); 746 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 747 748 mc->name = TYPE_VEXPRESS_A15_MACHINE; 749 mc->desc = "ARM Versatile Express for Cortex-A15"; 750 mc->init = vexpress_a15_init; 751 752 vmc->daughterboard = &a15_daughterboard; 753 } 754 755 static const TypeInfo vexpress_info = { 756 .name = TYPE_VEXPRESS_MACHINE, 757 .parent = TYPE_MACHINE, 758 .abstract = true, 759 .instance_size = sizeof(VexpressMachineState), 760 .class_size = sizeof(VexpressMachineClass), 761 .class_init = vexpress_class_init, 762 }; 763 764 static const TypeInfo vexpress_a9_info = { 765 .name = TYPE_VEXPRESS_A9_MACHINE, 766 .parent = TYPE_VEXPRESS_MACHINE, 767 .class_init = vexpress_a9_class_init, 768 }; 769 770 static const TypeInfo vexpress_a15_info = { 771 .name = TYPE_VEXPRESS_A15_MACHINE, 772 .parent = TYPE_VEXPRESS_MACHINE, 773 .class_init = vexpress_a15_class_init, 774 }; 775 776 static void vexpress_machine_init(void) 777 { 778 type_register_static(&vexpress_info); 779 type_register_static(&vexpress_a9_info); 780 type_register_static(&vexpress_a15_info); 781 } 782 783 machine_init(vexpress_machine_init); 784